@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.INCLUDE    "/src/inc/base.inc"

@.ITEM     APB2PERIPH_BASE
.EQU  SPI1_BASE          , APB2PERIPH_BASE + 0x3000
.EQU  SPI1               , PERIPH_BASE + SPI1_BASE

@.ITEM     APB1PERIPH_BASE
.EQU  SPI2_BASE          , APB1PERIPH_BASE + 0x3800
.EQU  SPI2               , PERIPH_BASE + SPI2_BASE

@.ITEM     SPI1 SPI1_BASE SPI2 SPI2_BASE
.EQU  SPI_CR1            , 0x00                    @ SPI control register 1 (SPI_CR1)
.EQU  SPI_CR2            , 0x04                    @ SPI control register 2 (SPI_CR2)
.EQU  SPI_SR             , 0X08                    @ SPI status register (SPI_SR)
.EQU  SPI_DR             , 0X0C                    @ SPI data register (SPI_DR)
.EQU  SPI_CRCPR          , 0X10                    @ SPI CRC polynomial register (SPI_CRCPR)
.EQU  SPI_RXCRCR         , 0X14                    @ SPI RX CRC register (SPI_RXCRCR)
.EQU  SPI_TXCRCR         , 0X18                    @ SPI TX CRC register (SPI_TXCRCR)

@.ITEM     SPI_CR1
.EQU  SPI_CR1_BIDIMODE   , 1 << 15                 @ Bit 15 BIDIMODE: Bidirectional data mode enable
.EQU  SPI_CR1_BIDIOE     , 1 << 14                 @ Bit 14 BIDIOE: Output enable in bidirectional mode
.EQU  SPI_CR1_CRCEN      , 1 << 13                 @ Bit 13 CRCEN: Hardware CRC calculation enable
.EQU  SPI_CR1_CRCNEXT    , 1 << 12                 @ Bit 12 CRCNEXT: CRC transfer next
.EQU  SPI_CR1_DFF        , 1 << 11                 @ Bit 11 DFF: Data frame format
.EQU  SPI_CR1_RXONLY     , 1 << 10                 @ Bit 10 RXONLY: Receive only
.EQU  SPI_CR1_SSM        , 1 << 9                  @ Bit 9 SSM: Software slave management
.EQU  SPI_CR1_SSI        , 1 << 8                  @ Bit 8 SSI: Internal slave select
.EQU  SPI_CR1_LSBFIRST   , 1 << 7                  @ Bit 7 LSBFIRST: Frame format
.EQU  SPI_CR1_SPE        , 1 << 6                  @ Bit 6 SPE: SPI enable
.EQU  SPI_CR1_BR_N       , 3                       @ Bits 5:3 BR[2:0]: Baud rate control
.EQU  SPI_CR1_BR_DIV2    , 0                       @ 000: fPCLK/2
.EQU  SPI_CR1_BR_DIV4    , 1 << 3                  @ 001: fPCLK/4
.EQU  SPI_CR1_BR_DIV8    , 2 << 3                  @ 010: fPCLK/8
.EQU  SPI_CR1_BR_DIV16   , 3 << 3                  @ 011: fPCLK/16
.EQU  SPI_CR1_BR_DIV32   , 4 << 3                  @ 100: fPCLK/32
.EQU  SPI_CR1_BR_DIV64   , 5 << 3                  @ 101: fPCLK/64
.EQU  SPI_CR1_BR_DIV128  , 6 << 3                  @ 110: fPCLK/128
.EQU  SPI_CR1_BR_DIV256  , 7 << 3                  @ 111: fPCLK/256
.EQU  SPI_CR1_MSTR       , 1 << 2                  @ Bit 2 MSTR: Master selection
.EQU  SPI_CR1_CPOL       , 1 << 1                  @ Bit1 CPOL: Clock polarity
.EQU  SPI_CR1_CPHA       , 1                       @ Bit 0 CPHA: Clock phase

@.ITEM     SPI_CR2
.EQU  SPI_CR2_TXEIE      , 1 << 7                  @ Bit 7 TXEIE: Tx buffer empty interrupt enable
.EQU  SPI_CR2_RXNEIE     , 1 << 6                  @ Bit 6 RXNEIE: RX buffer not empty interrupt enable
.EQU  SPI_CR2_ERRIE      , 1 << 5                  @ Bit 5 ERRIE: Error interrupt enable
.EQU  SPI_CR2_SSOE       , 1 << 2                  @ Bit 2 SSOE: SS output enable
.EQU  SPI_CR2_TXDMAEN_N  , 1                      @ Bit 1 TXDMAEN: Tx buffer DMA enable
.EQU  SPI_CR2_TXDMAEN    , 1 << 1                  @ Bit 1 TXDMAEN: Tx buffer DMA enable
.EQU  SPI_CR2_RXDMAEN    , 1                       @ Bit 0 RXDMAEN: Rx buffer DMA enable

@.ITEM     SPI_SR
.EQU  SPI_SR_BSY         , 1 << 7                  @ Bit 7 BSY: Busy flag
.EQU  SPI_SR_OVR         , 1 << 6                  @ Bit 6 OVR: Overrun flag
.EQU  SPI_SR_MODF        , 1 << 5                  @ Bit 5 MODF: Mode fault
.EQU  SPI_SR_CRCERR      , 1 << 4                  @ Bit 4 CRCERR: CRC error flag
.EQU  SPI_SR_TXE         , 1 << 1                  @ Bit 1 TXE: Transmit buffer empty
.EQU  SPI_SR_RXNE        , 1                       @ Bit 0 RXNE: Receive buffer not empty
