@.CHARSET CP1251

@ +------------------------------------------------------------------+
@ |                     Оределения GPIO (раздел 8)                   |
@ |                    STM32F030Fxx \ STM32F070Fxx                   |
@ |                          корпус TSSOP-20                         |
@ +------------------------------------------------------------------+
@ GP = general-purpose,
@ PP = push-pull,
@ PU = pull-up,
@ PD = pull-down,
@ OD = open-drain,
@ AF = alternate function.

.include "/src/inc/base.inc"

@ константы GPIO
@.item AHB2PERIPH_BASE
.equ GPIOA_BASE                 , AHB2PERIPH_BASE + 0x0000
.equ GPIOB_BASE                 , AHB2PERIPH_BASE + 0x0400
.equ GPIOC_BASE                 , AHB2PERIPH_BASE + 0x0800
.equ GPIOD_BASE                 , AHB2PERIPH_BASE + 0x0C00
.equ GPIOF_BASE                 , AHB2PERIPH_BASE + 0x1400
.equ GPIOA                      , PERIPH_BASE + GPIOA_BASE
.equ GPIOB                      , PERIPH_BASE + GPIOB_BASE
.equ GPIOC                      , PERIPH_BASE + GPIOC_BASE
.equ GPIOD                      , PERIPH_BASE + GPIOD_BASE
.equ GPIOF                      , PERIPH_BASE + GPIOF_BASE

@.end

@.CHARSET CP1251

@.item GPIOA GPIOB GPIOC GPIOD GPIOF GPIOA_BASE GPIOB_BASE GPIOC_BASE  GPIOD_BASE GPIOF_BASE
.equ GPIO_MODER                    , 0x00 @ GPIO port mode register
.equ GPIO_OTYPER                   , 0x04 @ GPIO port output type register
.equ GPIO_OSPEEDR                  , 0x08 @ GPIO port output speed register
.equ GPIO_PUPDR                    , 0x0C @ GPIO port pull-up/pull-down register
.equ GPIO_IDR                      , 0x10 @ GPIO port input data register
.equ GPIO_ODR                      , 0x14 @ GPIO port output data register
.equ GPIO_BSRR                     , 0x18 @ GPIO port bit set/reset register
.equ GPIO_LCKR                     , 0x1C @ GPIO port configuration lock register
.equ GPIO_AFRL                     , 0x20 @ GPIO alternate function low register
.equ GPIO_AFRH                     , 0x24 @ GPIO alternate function high register
.equ GPIO_BRR                      , 0x28 @ GPIO port bit reset register
@.end

@ Описание битов настройки
@.ITEM     GPIO_MODER
.EQU GPIO_MODER_A_RST_VAL          , 0x28000000 @ 0010 1000 - 4й байт
.EQU GPIO_MODER_B_RST_VAL          , 0x00000000
.EQU GPIO_MODER_C_RST_VAL          , 0x00000000
.EQU GPIO_MODER_D_RST_VAL          , 0x00000000
.EQU GPIO_MODER_F_RST_VAL          , 0x00000000
.EQU GPIO_MODER_0_N                , 0
.EQU GPIO_MODER_1_N                , 2
.EQU GPIO_MODER_2_N                , 4
.EQU GPIO_MODER_3_N                , 6
.EQU GPIO_MODER_4_N                , 8
.EQU GPIO_MODER_5_N                , 10
.EQU GPIO_MODER_6_N                , 12
.EQU GPIO_MODER_7_N                , 14
.EQU GPIO_MODER_8_N                , 16
.EQU GPIO_MODER_9_N                , 18
.EQU GPIO_MODER_10_N                , 20
.EQU GPIO_MODER_11_N                , 22
.EQU GPIO_MODER_12_N                , 24
.EQU GPIO_MODER_13_N                , 26
.EQU GPIO_MODER_14_N                , 28
.EQU GPIO_MODER_15_N                , 30
.equ GPIO_MODER_INPUT              , 0x00 @ Вход 00: Input mode (reset state)
.equ GPIO_MODER_GENERAL_OUT        , 0x01 @ Выход 01: General purpose output mode
.equ GPIO_MODER_ALT_MODE           , 0x02 @ Альтернативные функции 10: Alternate function mode
.equ GPIO_MODER_ANALOG             , 0x03 @ Аналоговый ввод/вывод 11: Analog mode
@.END


@ Описание битов настройки
@.item GPIO_OTYPER
.EQU GPIO_OTYPER_RST_VAL, 0x00000000
.EQU GPIO_OTYPER_OT0_N, 1  @ Bits 15:0 OTy: Port x configuration bits (y = 0..15)
                           @ These bits are written by software to configure the I/O output type.
.EQU GPIO_OTYPER_OT1_N, 1<<1
.EQU GPIO_OTYPER_OT2_N, 1<<2
.EQU GPIO_OTYPER_OT3_N, 1<<3
.EQU GPIO_OTYPER_OT4_N, 1<<4
.EQU GPIO_OTYPER_OT5_N, 1<<5
.EQU GPIO_OTYPER_OT6_N, 1<<6
.EQU GPIO_OTYPER_OT7_N, 1<<7
.EQU GPIO_OTYPER_OT8_N, 1<<8
.EQU GPIO_OTYPER_OT9_N, 1<<9
.EQU GPIO_OTYPER_OT10_N, 1<<10
.EQU GPIO_OTYPER_OT11_N, 1<<11
.EQU GPIO_OTYPER_OT12_N, 1<<12
.EQU GPIO_OTYPER_OT13_N, 1<<13
.EQU GPIO_OTYPER_OT14_N, 1<<14
.EQU GPIO_OTYPER_OT15_N, 1<<15
.EQU  GPIO_OTYPER_PP, 0x00    @ Push-Pull  0: Output push-pull (reset state)
.EQU  GPIO_OTYPER_OD, 0x01    @ Open Drain 1: Output open-drain
@.END

@ Описание битов настройки
@.item GPIO_OSPEEDR
.equ GPIO_OSPEEDR_A_RST_VAL        , 0x0C000000
.equ GPIO_OSPEEDR_B_RST_VAL        , 0x000000C0
.equ GPIO_OSPEEDR_0_N              , 0
.equ GPIO_OSPEEDR_1_N              , 2
.equ GPIO_OSPEEDR_2_N              , 4
.equ GPIO_OSPEEDR_3_N              , 6
.equ GPIO_OSPEEDR_4_N              , 8
.equ GPIO_OSPEEDR_5_N              , 10
.equ GPIO_OSPEEDR_6_N              , 12
.equ GPIO_OSPEEDR_7_N              , 14
.equ GPIO_OSPEEDR_8_N              , 16
.equ GPIO_OSPEEDR_9_N              , 18
.equ GPIO_OSPEEDR_10_N              , 20
.equ GPIO_OSPEEDR_11_N              , 22
.equ GPIO_OSPEEDR_12_N              , 24
.equ GPIO_OSPEEDR_13_N              , 26
.equ GPIO_OSPEEDR_14_N              , 28
.equ GPIO_OSPEEDR_15_N              , 30
.equ GPIO_OSPEEDR_LOW_SPEED        , 0x00 @ LOW SPEED
.equ GPIO_OSPEEDR_MEDIUM_SPEED     , 0x01 @ MEDIUM SPEED
.equ GPIO_OSPEEDR_HIGH_SPEED       , 0x02 @ HIGH SPEED
@.END

@ Описание битов настройки
@.item GPIO_PUPDR
.equ GPIO_PUPDR_A_RST_VAL          , 0x24000000 @ Reset values: 0x2400 0000 for port A
.equ GPIO_PUPDR_B_RST_VAL          , 0x00000000 @ Reset values: 0x0000 0000 for other ports
.EQU GPIO_PUPDR_C_RST_VAL          , 0x00000000
.equ GPIO_PUPDR_D_RST_VAL          , 0x00000000
.equ GPIO_PUPDR_F_RST_VAL          , 0x00000000
.equ GPIO_PUPDR_0_N                , 0
.equ GPIO_PUPDR_1_N                , 2
.equ GPIO_PUPDR_2_N                , 4
.equ GPIO_PUPDR_3_N                , 6
.equ GPIO_PUPDR_4_N                , 8
.equ GPIO_PUPDR_5_N                , 10
.equ GPIO_PUPDR_6_N                , 12
.equ GPIO_PUPDR_7_N                , 14
.equ GPIO_PUPDR_8_N                , 16
.equ GPIO_PUPDR_9_N                , 18
.equ GPIO_PUPDR_10_N                , 20
.equ GPIO_PUPDR_11_N                , 22
.equ GPIO_PUPDR_12_N                , 24
.equ GPIO_PUPDR_13_N                , 26
.equ GPIO_PUPDR_14_N                , 28
.equ GPIO_PUPDR_15_N                , 30
.equ GPIO_PUPDR_NPU_NPD            , 0x00 @ Нет подтяжки 00: No pull-up, pull-down
.equ GPIO_PUPDR_PU                 , 0x01 @ Подтяжка к питанию 01: Pull-up
.equ GPIO_PUPDR_PD                 , 0x02 @ Подтяжка к земле 10: Pull-down
.equ GPIO_PUPDR_RESERVED           , 0x03 @ 11: Reserved
@.END

@ Описание битов настройки
@.item GPIO_IDR
.EQU  GPIO_IDR_A_RST_VAL, 0x00000000    @ Reset value: 0x0000 XXXX (where X means undefined)
.EQU  GPIO_IDR_B_RST_VAL, 0x00000000
.EQU  GPIO_IDR_C_RST_VAL, 0x00000000
.EQU  GPIO_IDR_D_RST_VAL, 0x00000000
.EQU  GPIO_IDR_F_RST_VAL, 0x00000000    @ Bits 31:16 Reserved, must be kept at reset value.
                                        @ Bits 15:0 IDRy: Port input data bit (y = 0..15)
                                        @ These bits are read-only. They contain the input value of the corresponding I/O port.
@.END




@ Описание битов настройки
@.ITEM GPIO_ODR
.EQU  GPIO_ODR_A_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_ODR_B_RST_VAL, 0x00000000
.EQU  GPIO_ODR_C_RST_VAL, 0x00000000
.EQU  GPIO_ODR_D_RST_VAL, 0x00000000
.EQU  GPIO_ODR_F_RST_VAL, 0x00000000    @ Bits 31:16 Reserved, must be kept at reset value.
                                        @ Bits 15:0 ODRy: Port output data bit (y = 0..15)
                                        @ These bits can be read and written by software.
                                        @ Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to
                                        @ the GPIOx_BSRR or GPIOx_BRR registers (x = A..D, F).
@.END



@ Описание битов настройки
@.ITEM GPIO_BSRR
.EQU  GPIO_BSRR_A_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_BSRR_B_RST_VAL, 0x00000000
.EQU  GPIO_BSRR_C_RST_VAL, 0x00000000
.EQU  GPIO_BSRR_D_RST_VAL, 0x00000000
.EQU  GPIO_BSRR_F_RST_VAL, 0x00000000
.EQU  GPIO_BSRR_BR_0, 1 << 16
.EQU  GPIO_BSRR_BR_1, 1 << 17
.EQU  GPIO_BSRR_BR_2, 1 << 18
.EQU  GPIO_BSRR_BR_3, 1 << 19
.EQU  GPIO_BSRR_BR_4, 1 << 20
.EQU  GPIO_BSRR_BR_5, 1 << 21
.EQU  GPIO_BSRR_BR_6, 1 << 22
.EQU  GPIO_BSRR_BR_7, 1 << 23
.EQU  GPIO_BSRR_BR_8, 1 << 24
.EQU  GPIO_BSRR_BR_9, 1 << 25
.EQU  GPIO_BSRR_BR_10, 1 << 26
.EQU  GPIO_BSRR_BR_11, 1 << 27
.EQU  GPIO_BSRR_BR_12, 1 << 28
.EQU  GPIO_BSRR_BR_13, 1 << 29
.EQU  GPIO_BSRR_BR_14, 1 << 30
.EQU  GPIO_BSRR_BR_15, 1 << 31           @ Bits 31:16 BRy: Port x reset bit y (y = 0..15)
                                         @ These bits are write-only. A read to these bits returns the value 0x0000.
                                         @ 0: No action on the corresponding ODRx bit
                                         @ 1: Resets the corresponding ODRx bit
                                         @ Note: If both BSx and BRx are set, BSx has priority.
.EQU  GPIO_BSRR_BS_0, 1
.EQU  GPIO_BSRR_BS_1, 1 << 1
.EQU  GPIO_BSRR_BS_2, 1 << 2
.EQU  GPIO_BSRR_BS_3, 1 << 3
.EQU  GPIO_BSRR_BS_4, 1 << 4
.EQU  GPIO_BSRR_BS_5, 1 << 5
.EQU  GPIO_BSRR_BS_6, 1 << 6
.EQU  GPIO_BSRR_BS_7, 1 << 7
.EQU  GPIO_BSRR_BS_8, 1 << 8
.EQU  GPIO_BSRR_BS_9, 1 << 9
.EQU  GPIO_BSRR_BS_10, 1 << 10
.EQU  GPIO_BSRR_BS_11, 1 << 11
.EQU  GPIO_BSRR_BS_12, 1 << 12
.EQU  GPIO_BSRR_BS_13, 1 << 13
.EQU  GPIO_BSRR_BS_14, 1 << 14
.EQU  GPIO_BSRR_BS_15, 1 << 15           @ Bits 15:0 BSy: Port x set bit y (y= 0..15)
                                         @ These bits are write-only. A read to these bits returns the value 0x0000.
                                         @ 0: No action on the corresponding ODRx bit
                                         @ 1: Sets the corresponding ODRx bit
@.END


@ Описание битов настройки
@.item GPIO_LCKR
.EQU  GPIO_LCKR_A_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_LCKR_B_RST_VAL, 0x00000000
.EQU  GPIO_LCKR_C_RST_VAL, 0x00000000
.EQU  GPIO_LCKR_D_RST_VAL, 0x00000000
.EQU  GPIO_LCKR_F_RST_VAL, 0x00000000    @ This register is used to lock the configuration of the port bits
                                         @ when a correct write sequence is applied to bit 16 (LCKK).
                                         @ The value of bits [15:0] is used to lock the configuration of the GPIO.
                                         @ During the write sequence, the value of LCKR[15:0] must not change.
                                         @ When the LOCK sequence has been applied on a port bit,
                                         @ the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.
                                         @ Note:A specific write sequence is used to write to the GPIOx_LCKR register.
                                         @ Only word access (32-bit long) is allowed during this locking sequence.
                                         @ Each lock bit freezes a specific configuration register (control and alternate function registers).
.EQU  GPIO_LCKR_LVKK, 1 << 16  @ флаг включения блокировки битов
.EQU  GPIO_LCKR_LVK0, 1
.EQU  GPIO_LCKR_LVK1, 1 << 1
.EQU  GPIO_LCKR_LVK2, 1 << 2
.EQU  GPIO_LCKR_LVK3, 1 << 3
.EQU  GPIO_LCKR_LVK4, 1 << 4
.EQU  GPIO_LCKR_LVK5, 1 << 5
.EQU  GPIO_LCKR_LVK6, 1 << 6
.EQU  GPIO_LCKR_LVK7, 1 << 7
.EQU  GPIO_LCKR_LVK8, 1 << 8
.EQU  GPIO_LCKR_LVK9, 1 << 9
.EQU  GPIO_LCKR_LVK10, 1 << 10
.EQU  GPIO_LCKR_LVK11, 1 << 11
.EQU  GPIO_LCKR_LVK12, 1 << 12
.EQU  GPIO_LCKR_LVK13, 1 << 13
.EQU  GPIO_LCKR_LVK14, 1 << 14
.EQU  GPIO_LCKR_LVK15, 1 << 15               @ Bits 31:17 Reserved, must be kept at reset value.
                                             @ Bit 16 LCKK: Lock key
                                             @ This bit can be read any time. It can only be modified using the lock key write sequence.
                                             @ 0: Port configuration lock key not active
                                             @ 1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
                                             @ reset or peripheral reset.
                                             @ LOCK key write sequence:
                                             @ WR LCKR[16] = ‘1’ + LCKR[15:0]
                                             @ WR LCKR[16] = ‘0’ + LCKR[15:0]
                                             @ WR LCKR[16] = ‘1’ + LCKR[15:0]
                                             @ RD LCKR
                                             @ RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
                                             @ Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
                                             @ Any error in the lock sequence aborts the lock.
                                             @ After the first lock sequence on any bit of the port, any read access on the LCKK bit will
                                             @ return ‘1’ until the next MCU reset or peripheral reset.
                                             @ For code example refer to the Appendix section A.4.1: Lock sequence code example.
                                             @ Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
                                             @ These bits are read/write but can only be written when the LCKK bit is ‘0.
                                             @ 0: Port configuration not locked
                                             @ 1: Port configuration locked
@.END







@ Описание битов настройки
@.item GPIO_AFRL GPIO_AFRH
.EQU  GPIO_AFR_RST_VAL, 0x00000000
.EQU  GPIO_AFR_AFSEL_0, 0
.EQU  GPIO_AFR_AFSEL_1, 0 << 4
.EQU  GPIO_AFR_AFSEL_2, 0 << 8
.EQU  GPIO_AFR_AFSEL_3, 0 << 12
.EQU  GPIO_AFR_AFSEL_4, 0 << 16
.EQU  GPIO_AFR_AFSEL_5, 0 << 20
.EQU  GPIO_AFR_AFSEL_6, 0 << 24
.EQU  GPIO_AFR_AFSEL_7, 0 << 28
.EQU  GPIO_AFR_AFSEL_8, 0
.EQU  GPIO_AFR_AFSEL_9, 0 << 4
.EQU  GPIO_AFR_AFSEL_10, 0 << 8
.EQU  GPIO_AFR_AFSEL_11, 0 << 12
.EQU  GPIO_AFR_AFSEL_12, 0 << 16
.EQU  GPIO_AFR_AFSEL_13, 0 << 20
.EQU  GPIO_AFR_AFSEL_14, 0 << 24
.EQU  GPIO_AFR_AFSEL_15, 0 << 28
@ Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7)
@ These bits are written by software to configure alternate function I/Os
@ AFSELy selection:
@ 0000: AF0
@ 0001: AF1
@ 0010: AF2
@ 0011: AF3
@ 0100: AF4
@ 0101: AF5
@ 0110: AF6
@ 0111: AF7
@ .equ GPIO_AFR_0                    , 0x00  @ SYS
@ .equ GPIO_AFR_1                    , 0x01  @
@ .equ GPIO_AFR_2                    , 0x02  @
@ .equ GPIO_AFR_3                    , 0x03  @
@ .equ GPIO_AFR_4                    , 0x04  @
@ .equ GPIO_AFR_5                    , 0x05  @
@ .equ GPIO_AFR_6                    , 0x06  @
@ .equ GPIO_AFR_7                    , 0x07  @
@.end

@.ITEM GPIO_BRR
.EQU  GPIO_BRR_A_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_BRR_B_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_BRR_C_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_BRR_D_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_BRR_F_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  GPIO_BRR_BR_0 , 1
.EQU  GPIO_BRR_BR_1 , 1 << 1
.EQU  GPIO_BRR_BR_2 , 1 << 2
.EQU  GPIO_BRR_BR_3 , 1 << 3
.EQU  GPIO_BRR_BR_4 , 1 << 4
.EQU  GPIO_BRR_BR_5 , 1 << 5
.EQU  GPIO_BRR_BR_6 , 1 << 6
.EQU  GPIO_BRR_BR_7 , 1 << 7
.EQU  GPIO_BRR_BR_8 , 1 << 8
.EQU  GPIO_BRR_BR_9 , 1 << 9
.EQU  GPIO_BRR_BR_10, 1 << 10
.EQU  GPIO_BRR_BR_11, 1 << 11
.EQU  GPIO_BRR_BR_12, 1 << 12
.EQU  GPIO_BRR_BR_13, 1 << 13
.EQU  GPIO_BRR_BR_14, 1 << 14
.EQU  GPIO_BRR_BR_15, 1 << 15           @ Bits 31:16 Reserved
                                        @ Bits 15:0 BRy: Port x Reset bit y (y= 0..15)
                                        @ These bits are write-only. A read to these bits returns the value 0x0000
                                        @ 0: No action on the corresponding ODx bit
                                        @ 1: Reset the corresponding ODx bit
@.END



