@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы TIM1, TIM8                 |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APB2PERIPH_BASE
.EQU  TIM1_BASE          , APB2PERIPH_BASE
.EQU  TIM8_BASE          , APB2PERIPH_BASE + 0x400
.EQU  TIM1               , PERIPH_BASE + APB2PERIPH_BASE
.EQU  TIM8               , PERIPH_BASE + APB2PERIPH_BASE + 0x400


@.ITEM     TIM1 TIM8 TIM1_BASE TIM8_BASE
.EQU  TIM18_CR1          , 0x00
.EQU  TIM18_CR2          , 0x04
.EQU  TIM18_SMCR         , 0x08
.EQU  TIM18_DIER         , 0x0C
.EQU  TIM18_SR           , 0x10
.EQU  TIM18_EGR          , 0x14
.EQU  TIM18_CCMR1        , 0x18
.EQU  TIM18_CCMR2        , 0x1C
.EQU  TIM18_CCER         , 0x20
.EQU  TIM18_CNT          , 0x24
.EQU  TIM18_PSC          , 0x28
.EQU  TIM18_ARR          , 0x2C
.EQU  TIM18_RCR          , 0x30
.EQU  TIM18_CCR1         , 0x34
.EQU  TIM18_CCR2         , 0x38
.EQU  TIM18_CCR3         , 0x3C
.EQU  TIM18_CCR4         , 0x40
.EQU  TIM18_BDTR         , 0x44
.EQU  TIM18_DCR          , 0x48
.EQU  TIM18_DMAR         , 0x4C


@.ITEM     TIM18_CR1
.EQU  TIM18_CR1_CKD_N    , 8
.EQU  TIM18_CR1_CKD_CK   , 0
.EQU  TIM18_CR1_CKD_2CK  , 1 << 8
.EQU  TIM18_CR1_CKD_4CK  , 2 << 8
.EQU  TIM18_CR1_ARPE     , 1 << 7
.EQU  TIM18_CR1_CMS_N    , 5
.EQU  TIM18_CR1_EDGE     , 0
.EQU  TIM18_CR1_CENTER1  , 1 << 5
.EQU  TIM18_CR1_CENTER2  , 2 << 5
.EQU  TIM18_CR1_CENTER3  , 3 << 5
.EQU  TIM18_CR1_DIR      , 1 << 4
.EQU  TIM18_CR1_OPM      , 1 << 3
.EQU  TIM18_CR1_URS      , 1 << 2
.EQU  TIM18_CR1_UDIS     , 1 << 1
.EQU  TIM18_CR1_CEN      , 1

@.ITEM     TIM18_CR2
.EQU  TIM18_CR2_OIS4     , 1 << 14
.EQU  TIM18_CR2_OIS3N    , 1 << 13
.EQU  TIM18_CR2_OIS3     , 1 << 12
.EQU  TIM18_CR2_OIS2N    , 1 << 11
.EQU  TIM18_CR2_OIS2     , 1 << 10
.EQU  TIM18_CR2_OIS1N    , 1 << 9
.EQU  TIM18_CR2_OIS1     , 1 << 8
.EQU  TIM18_CR2_TI1S     , 1 << 7
.EQU  TIM18_CR2_MMS_N    , 4
.EQU  TIM18_CR2_MMS_OC1REF, 4 << 4
.EQU  TIM18_CR2_MMS_OC2REF, 5 << 4
.EQU  TIM18_CR2_MMS_OC3REF, 6 << 4
.EQU  TIM18_CR2_MMS_OC4REF, 7 << 4
.EQU  TIM18_CR2_CCDS     , 1 << 3
.EQU  TIM18_CR2_CCUS     , 1 << 2
.EQU  TIM18_CR2_CCPS     , 1

@.ITEM     TIM18_SMCR
.EQU  TIM18_SMCR_ETP     , 1 << 15
.EQU  TIM18_SMCR_ECE     , 1 << 14
.EQU  TIM18_SMCR_ETPS_N  , 12
.EQU  TIM18_SMCR_ETPS_PROFF, 0
.EQU  TIM18_SMCR_ETPS_DIV2, 1 << 12
.EQU  TIM18_SMCR_ETPS_DIV4, 2 << 12
.EQU  TIM18_SMCR_ETPS_DIV8, 3 << 12
.EQU  TIM18_SMCR_ETF_N   , 8
.EQU  TIM18_SMCR_ETF_NOF , 0
.EQU  TIM18_SMCR_ETF_N2  , 1 << 8
.EQU  TIM18_SMCR_ETF_N4  , 2 << 8
.EQU  TIM18_SMCR_ETF_N8  , 3 << 8
.EQU  TIM18_SMCR_ETF_2N6 , 4 << 8
.EQU  TIM18_SMCR_ETF_2N8 , 5 << 8
.EQU  TIM18_SMCR_ETF_4N6 , 6 << 8
.EQU  TIM18_SMCR_ETF_4N8 , 7 << 8
.EQU  TIM18_SMCR_ETF_8N6 , 8 << 8
.EQU  TIM18_SMCR_ETF_8N8 , 9 << 8
.EQU  TIM18_SMCR_ETF_16N5, 10 << 8
.EQU  TIM18_SMCR_ETF_16N6, 11 << 8
.EQU  TIM18_SMCR_ETF_16N8, 12 << 8
.EQU  TIM18_SMCR_ETF_32N5, 13 << 8
.EQU  TIM18_SMCR_ETF_32N6, 14 << 8
.EQU  TIM18_SMCR_ETF_32N8, 15 << 8
.EQU  TIM18_SMCR_MSM     , 1 << 7
.EQU  TIM18_SMCR_TS_N    , 4
.EQU  TIM18_SMCR_TS_ITR0 , 0
.EQU  TIM18_SMCR_TS_ITR1 , 1 << 4
.EQU  TIM18_SMCR_TS_ITR2 , 2 << 4
.EQU  TIM18_SMCR_TS_ITR3 , 3 << 4
.EQU  TIM18_SMCR_TS_TI1F_ED, 4 << 4
.EQU  TIM18_SMCR_TS_TI1FP1, 5 << 4
.EQU  TIM18_SMCR_TS_TI2FP2, 6 << 4
.EQU  TIM18_SMCR_TS_ETRF , 7 << 4
.EQU  TIM18_SMCR_SMS_N   , 0
.EQU  TIM18_SMCR_SMS_SMD , 0
.EQU  TIM18_SMCR_SMS_ENCM1, 1
.EQU  TIM18_SMCR_SMS_ENCM2, 2
.EQU  TIM18_SMCR_SMS_ENCM3, 3
.EQU  TIM18_SMCR_SMS_RSTM, 4
.EQU  TIM18_SMCR_SMS_GTDM, 5
.EQU  TIM18_SMCR_TS_TRIGM, 6
.EQU  TIM18_SMCR_TS_EXTCLK, 7

@         Table 95. TIMx internal trigger connection
@ Slave TIM     ITR0        ITR1        ITR2        ITR3
@            (TS = 000)  (TS = 001)  (TS = 010)  (TS = 011)
@  TIM2      TIM1_TRGO   TIM8_TRGO   TIM3_TRGO   TIM4_TRGO
@  TIM3      TIM1_TRGO   TIM2_TRGO   TIM5_TRGO   TIM4_TRGO
@  TIM4      TIM1_TRGO   TIM2_TRGO   TIM3_TRGO   TIM8_TRGO
@  TIM5      TIM2_TRGO   TIM3_TRGO   TIM4_TRGO   TIM8_TRGO


@.ITEM     TIM18_DIER
.EQU  TIM18_DIER_TDE     , 1 << 14
.EQU  TIM18_DIER_COMDE   , 1 << 13
.EQU  TIM18_DIER_CC4DE   , 1 << 12
.EQU  TIM18_DIER_CC3DE   , 1 << 11
.EQU  TIM18_DIER_CC2DE   , 1 << 10
.EQU  TIM18_DIER_CC1DE   , 1 << 9
.EQU  TIM18_DIER_UDE     , 1 << 8
.EQU  TIM18_DIER_BIE     , 1 << 7
.EQU  TIM18_DIER_TIE     , 1 << 6
.EQU  TIM18_DIER_COMIE   , 1 << 5
.EQU  TIM18_DIER_CC4IE   , 1 << 4
.EQU  TIM18_DIER_CC3IE   , 1 << 3
.EQU  TIM18_DIER_CC2IE   , 1 << 2
.EQU  TIM18_DIER_CC1IE   , 1 << 1
.EQU  TIM18_DIER_UIE     , 1

@.ITEM     TIM18_SR
.EQU  TIM18_SR_CC4OF     , 1 << 12
.EQU  TIM18_SR_CC3OF     , 1 << 11
.EQU  TIM18_SR_CC2OF     , 1 << 10
.EQU  TIM18_SR_CC1OF     , 1 << 9
.EQU  TIM18_SR_BIF       , 1 << 7
.EQU  TIM18_SR_TIF       , 1 << 6
.EQU  TIM18_SR_COMIF     , 1 << 5
.EQU  TIM18_SR_CO4IF     , 1 << 4
.EQU  TIM18_SR_CO3IF     , 1 << 3
.EQU  TIM18_SR_CO2IF     , 1 << 2
.EQU  TIM18_SR_CO1IF     , 1 << 1
.EQU  TIM18_SR_UIF       , 1

@.ITEM     TIM18_EGR
.EQU  TIM18_EGR_BG       , 1 << 7
.EQU  TIM18_EGR_TG       , 1 << 6
.EQU  TIM18_EGR_COMG     , 1 << 5
.EQU  TIM18_EGR_CC4G     , 1 << 4
.EQU  TIM18_EGR_CC3G     , 1 << 3
.EQU  TIM18_EGR_CC2G     , 1 << 2
.EQU  TIM18_EGR_CC1G     , 1 << 1
.EQU  TIM18_EGR_UG       , 1

@.ITEM     TIM18_CCMR1
.EQU  TIM18_CCMR1_OC2CE  , 1 << 15
.EQU  TIM18_CCMR1_OC2M_N , 12
.EQU  TIM18_CCMR1_OC2PE  , 1 << 11
.EQU  TIM18_CCMR1_OC2FE  , 1 << 10
.EQU  TIM18_CCMR1_CC2S_N , 1 << 8
.EQU  TIM18_CCMR1_OC1CE  , 1 << 7
.EQU  TIM18_CCMR1_OC1M_N , 4
.EQU  TIM18_CCMR1_OC1PE  , 1 << 3
.EQU  TIM18_CCMR1_OC1FE  , 1 << 2
.EQU  TIM18_CCMR1_CC1S_N , 0
.EQU  TIM18_CCMR1_IC2F_N , 12
.EQU  TIM18_CCMR1_IC2PSC , 10
.EQU  TIM18_CCMR1_CC2S_N , 8
.EQU  TIM18_CCMR1_CC2S_OUT, 0
.EQU  TIM18_CCMR1_CC2S_TI2, 1 << 8
.EQU  TIM18_CCMR1_CC2S_TI1, 2 << 8
.EQU  TIM18_CCMR1_CC2S_TRC, 3 << 8
.EQU  TIM18_CCMR1_IC1F_N , 4
.EQU  TIM18_CCMR1_IC1F_NOF, 0
.EQU  TIM18_CCMR1_IC1F_N2, 1 << 4
.EQU  TIM18_CCMR1_IC1F_N4, 2 << 4
.EQU  TIM18_CCMR1_IC1F_N8, 3 << 4
.EQU  TIM18_CCMR1_IC1F_2N6, 4 << 4
.EQU  TIM18_CCMR1_IC1F_2N8, 5 << 4
.EQU  TIM18_CCMR1_IC1F_4N6, 6 << 4
.EQU  TIM18_CCMR1_IC1F_4N8, 7 << 4
.EQU  TIM18_CCMR1_IC1F_8N6, 8 << 4
.EQU  TIM18_CCMR1_IC1F_8N8, 9 << 4
.EQU  TIM18_CCMR1_IC1F_16N5, 10 << 4
.EQU  TIM18_CCMR1_IC1F_16N6, 11 << 4
.EQU  TIM18_CCMR1_IC1F_16N8, 12 << 4
.EQU  TIM18_CCMR1_IC1F_32N5, 13 << 4
.EQU  TIM18_CCMR1_IC1F_32N6, 14 << 4
.EQU  TIM18_CCMR1_IC1F_32N8, 15 << 4
.EQU  TIM18_CCMR1_IC1PSC_N, 2
.EQU  TIM18_CCMR1_IC1PSC_1, 0
.EQU  TIM18_CCMR1_IC1PSC_2, 1 << 2
.EQU  TIM18_CCMR1_IC1PSC_4, 2 << 2
.EQU  TIM18_CCMR1_IC1PSC_8, 3 << 2
.EQU  TIM18_CCMR1_CC1S_N , 0
.EQU  TIM18_CCMR1_CC1S_OUT, 0
.EQU  TIM18_CCMR1_CC1S_TI1, 1
.EQU  TIM18_CCMR1_CC1S_TI2, 2
.EQU  TIM18_CCMR1_CC1S_TRC, 3

@.ITEM     TIM18_CCMR2
.EQU  TIM18_CCMR2_OC4CE  , 1 << 15
.EQU  TIM18_CCMR2_OC4M_N , 12
.EQU  TIM18_CCMR2_OC4PE  , 1 << 11
.EQU  TIM18_CCMR2_OC4FE  , 1 << 10
.EQU  TIM18_CCMR2_CC4S_N , 1 << 8
.EQU  TIM18_CCMR2_OC3CE  , 1 << 7
.EQU  TIM18_CCMR2_OC3M_N , 4
.EQU  TIM18_CCMR2_OC3PE  , 1 << 3
.EQU  TIM18_CCMR2_OC3FE  , 1 << 2
.EQU  TIM18_CCMR2_CC3S_N , 0
.EQU  TIM18_CCMR2_IC4F_N , 12
.EQU  TIM18_CCMR2_IC4PSC , 10
.EQU  TIM18_CCMR2_CC4S_N , 8
.EQU  TIM18_CCMR2_CC4S_OUT, 0
.EQU  TIM18_CCMR2_CC4S_TI2, 1 << 8
.EQU  TIM18_CCMR2_CC4S_TI1, 2 << 8
.EQU  TIM18_CCMR2_CC4S_TRC, 3 << 8
.EQU  TIM18_CCMR2_IC3F_N , 4
.EQU  TIM18_CCMR2_IC3F_NOF, 0
.EQU  TIM18_CCMR2_IC3F_N2, 1 << 4
.EQU  TIM18_CCMR2_IC3F_N4, 2 << 4
.EQU  TIM18_CCMR2_IC3F_N8, 3 << 4
.EQU  TIM18_CCMR2_IC3F_2N6, 4 << 4
.EQU  TIM18_CCMR2_IC3F_2N8, 5 << 4
.EQU  TIM18_CCMR2_IC3F_4N6, 6 << 4
.EQU  TIM18_CCMR2_IC3F_4N8, 7 << 4
.EQU  TIM18_CCMR2_IC3F_8N6, 8 << 4
.EQU  TIM18_CCMR2_IC3F_8N8, 9 << 4
.EQU  TIM18_CCMR2_IC3F_16N5, 10 << 4
.EQU  TIM18_CCMR2_IC3F_16N6, 11 << 4
.EQU  TIM18_CCMR2_IC3F_16N8, 12 << 4
.EQU  TIM18_CCMR2_IC3F_32N5, 13 << 4
.EQU  TIM18_CCMR2_IC3F_32N6, 14 << 4
.EQU  TIM18_CCMR2_IC3F_32N8, 15 << 4
.EQU  TIM18_CCMR2_IC3PSC_N, 2
.EQU  TIM18_CCMR2_IC3PSC_1, 0
.EQU  TIM18_CCMR2_IC3PSC_2, 1 << 2
.EQU  TIM18_CCMR2_IC3PSC_4, 2 << 2
.EQU  TIM18_CCMR2_IC3PSC_8, 3 << 2
.EQU  TIM18_CCMR2_CC3S_N , 0
.EQU  TIM18_CCMR2_CC3S_OUT, 0
.EQU  TIM18_CCMR2_CC3S_TI1, 1
.EQU  TIM18_CCMR2_CC3S_TI2, 2
.EQU  TIM18_CCMR2_CC3S_TRC, 3

@.ITEM     TIM18_CCER
.EQU  TIM18_CCER_CC4P    , 1 << 13
.EQU  TIM18_CCER_CC4E    , 1 << 12
.EQU  TIM18_CCER_CC3NP   , 1 << 11
.EQU  TIM18_CCER_CC3NE   , 1 << 10
.EQU  TIM18_CCER_CC3P    , 1 << 9
.EQU  TIM18_CCER_CC3E    , 1 << 8
.EQU  TIM18_CCER_CC2NP   , 1 << 7
.EQU  TIM18_CCER_CC2NE   , 1 << 6
.EQU  TIM18_CCER_CC2P    , 1 << 5
.EQU  TIM18_CCER_CC2E    , 1 << 4
.EQU  TIM18_CCER_CC1NP   , 1 << 3
.EQU  TIM18_CCER_CC1NE   , 1 << 2
.EQU  TIM18_CCER_CC1P    , 1 << 1
.EQU  TIM18_CCER_CC1E    , 1

@.ITEM     TIM18_RCR
.EQU  TIM18_RCR_REP_M    , 0X00FF

@.ITEM     TIM18_BDTRR
.EQU  TIM18_BDTR_MOE     , 1 << 15
.EQU  TIM18_BDTR_AOE     , 1 << 14
.EQU  TIM18_BDTR_BKP     , 1 << 13
.EQU  TIM18_BDTR_BKE     , 1 << 12
.EQU  TIM18_BDTR_OSSR    , 1 << 11
.EQU  TIM18_BDTR_OSSI    , 1 << 10
.EQU  TIM18_BDTR_LOCK_N  , 8
.EQU  TIM18_BDTR_LOCK_OFF, 0
.EQU  TIM18_BDTR_LOCK_LEV1, 1 << 8
.EQU  TIM18_BDTR_LOCK_LEV2, 2 << 8
.EQU  TIM18_BDTR_LOCK_LEV3, 3 << 8
.EQU  TIM18_BDTR_LOCK_DTG_M, 0xFF
.EQU  TIM18_BDTR_LOCK_DTG_N, 0

@.ITEM     TIM18_DCR
.EQU  TIM18_DCR_DBL_N    , 8
.EQU  TIM18_DCR_DBA_N    , 0


