@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                           Îïðåäåëåíèÿ I2C                        |
@ |                             STM32F401xxx                         |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@ êîíñòàíòû I2C

@.item     APB1PERIPH_BASE
.equ I2C1_BASE          , APB1PERIPH_BASE + 0x5400
.equ I2C2_BASE          , APB1PERIPH_BASE + 0x5800
.equ I2C1               , PERIPH_BASE + I2C1_BASE
.equ I2C2               , PERIPH_BASE + I2C2_BASE
@.end


@.item     I2C1 I2C1_BASE I2C2 I2C2_BASE I2C3 I2C3_BASE
.equ  I2C_CR1            , 0x00    @ I2C Control register 1
.equ  I2C_CR2            , 0x04    @ I2C Control register 2
.equ  I2C_OAR1           , 0x08    @ I2C Own address register 1
.equ  I2C_OAR2           , 0x0C    @ I2C Own address register 2
.equ  I2C_DR             , 0x10    @ I2C Data register
.equ  I2C_SR1            , 0x14    @ I2C Status register 1
.equ  I2C_SR2            , 0x18    @ I2C Status register 2
.equ  I2C_CCR            , 0x1C    @ I2C Clock control register
.equ  I2C_TRISE          , 0x20    @ I2C TRISE register
@.end

@.item     I2C_CR1
.EQU  I2C_CR1_PE_N        , 0            @ Bit 0 PE: Peripheral enable
                                         @ 0: Peripheral disable
.EQU  I2C_CR1_PE    , 1                  @ 1: Peripheral enable
                                   @ Note: If this bit is reset while a communication is on going, the peripheral is disabled at the
                                         @ end of the current communication, when back to IDLE state.
                                         @ All bit resets due to PE=0 occur at the end of the communication.
                                         @ In master mode, this bit must not be reset before the end of the communication.
.EQU  I2C_CR1_SMBUS_N    , 1             @ Bit 1 SMBUS: SMBus mode
.EQU  I2C_CR1_SMBUS_I2C  , 0 << 1        @ 0: I2C mode
.EQU  I2C_CR1_SMBUS      , 1 << 1        @ 1: SMBus mode
.EQU  I2C_CR1_SMBTYPE_N  , 3             @ Bit 3 SMBTYPE: SMBus type
.EQU  I2C_CR1_SMBTYPE_D  , 0             @ 0: SMBus Device
.EQU  I2C_CR1_SMBTYPE_H  , 1 << 3        @ 1: SMBus Host
.EQU  I2C_CR1_ENARP_N    , 4             @ Bit 4 ENARP: ARP enable
.EQU  I2C_CR1_ENARP_D    , 0             @ 0: ARP disable
.EQU  I2C_CR1_ENARP      , 1 << 4        @ 1: ARP enable
.EQU  I2C_CR1_ENPEC_N    , 5             @ Bit 5 ENPEC: PEC enable
.EQU  I2C_CR1_ENPEC_D    , 0             @ 0: PEC calculation disabled
.EQU  I2C_CR1_ENPEC      , 1 << 5        @ 1: PEC calculation enabled
.EQU  I2C_CR1_ENGC_N     , 6             @ Bit 6 ENGC: General call enable
.EQU  I2C_CR1_ENGC_D     , 0             @ 0: General call disabled. Address 00h is NACKed.
.EQU  I2C_CR1_ENGC       , 1 << 6        @ 1: General call enabled. Address 00h is ACKed.
.EQU  I2C_CR1_NOSTRETCH_N, 7             @ Bit 7 NOSTRETCH: Clock stretching disable (Slave mode)
                                         @ This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until
                                         @ it is reset by software.
.EQU  I2C_CR1_NOSTRETCH_D, 0             @ 0: Clock stretching enabled
.EQU  I2C_CR1_NOSTRETCH  , 1 << 7        @ 1: Clock stretching disabled
.EQU  I2C_CR1_START_N    , 8             @ Bit 8 START: Start generation
                                         @ This bit is set and cleared by software and cleared by hardware when start is sent or PE=0.
                                         @ In Master Mode:
.EQU  I2C_CR1_START_NOT  , 0             @ 0: No Start generation
.EQU  I2C_CR1_START      , 1 << 8        @ 1: Repeated start generation
                                         @ In Slave mode:
                                         @ 0: No Start generation
                                         @ 1: Start generation when the bus is free
.EQU  I2C_CR1_STOP_N     , 9             @ Bit 9 STOP: Stop generation
                                         @ The bit is set and cleared by software, cleared by hardware when a Stop condition is
                                         @ detected, set by hardware when a timeout error is detected.
                                         @ In Master Mode:
.EQU  I2C_CR1_STOP_NOT   , 0             @ 0: No Stop generation.
.EQU  I2C_CR1_STOP       , 1 << 9        @ 1: Stop generation after the current byte transfer or after the current Start condition is sent.
                                         @ In Slave mode:
                                         @ 0: No Stop generation.
                                         @ 1: Release the SCL and SDA lines after the current byte transfer.
.EQU  I2C_CR1_ACK_N      , 10            @ Bit 10 ACK: Acknowledge enable
                                         @ This bit is set and cleared by software and cleared by hardware when PE=0.
.EQU  I2C_CR1_ACK_NOACK  , 0             @ 0: No acknowledge returned
.EQU  I2C_CR1_ACK        , 1 << 10       @ 1: Acknowledge returned after a byte is received (matched address or data)
.EQU  I2C_CR1_POS_N      , 11            @ Bit 11 POS: Acknowledge/PEC Position (for data reception)
                                         @ This bit is set and cleared by software and cleared by hardware when PE=0.
.EQU  I2C_CR1_POS_NOT    , 0             @ 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The
                                         @ PEC bit indicates that current byte in shift register is a PEC.
.EQU  I2C_CR1_POS        , 1 << 11       @ 1: ACK bit controls the (N)ACK of the next byte which is received in the shift register. The
                                         @ PEC bit indicates that the next byte in the shift register is a PEC
                                   @ Note: The POS bit must be used only in 2-byte reception configuration in master mode. It
                                         @ must be configured before data reception starts, as described in the 2-byte reception
                                         @ procedure recommended in Section : Master receiver on page 669.
.EQU  I2C_CR1_PEC_N      , 12            @  Bit 12 PEC: Packet error checking
                                         @ This bit is set and cleared by software, and cleared by hardware when PEC is transferred or
                                         @ by a START or Stop condition or when PE=0.
.EQU  I2C_CR1_PEC_NOT    , 0             @ 0: No PEC transfer
.EQU  I2C_CR1_PEC        , 1 << 12       @ 1: PEC transfer (in Tx or Rx mode)
                                   @ Note: PEC calculation is corrupted by an arbitration loss.
.EQU  I2C_CR1_ALERT_N      , 13          @  Bit 13 ALERT: SMBus alert
                                         @ This bit is set and cleared by software, and cleared by hardware when PE=0.
                                         @ 0: Releases SMBA pin high. Alert Response Address Header followed by NACK.
.EQU  I2C_CR1_ALERT , 1 << 13            @ 1: Drives SMBA pin low. Alert Response Address Header followed by ACK.
.EQU  I2C_CR1_SWRST_N    , 15            @  Bit 15 SWRST: Software reset
                                         @ When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are
                                         @ released and the bus is free.
                                         @ 0: I2C Peripheral not under reset
.EQU  I2C_CR1_SWRST      , 1 << 15       @ 1: I2C Peripheral under reset state
                                         @ Note: This bit can be used to reinitialize the peripheral after an error or a locked state. As an
                                         @ example, if the BUSY bit is set and remains locked due to a glitch on the bus, the
                                         @ SWRST bit can be used to exit from this state.
@.end

@.item     I2C_CR2
.EQU  I2C_CR2_FREQ_N, 0                  @ Bits 5:0 FREQ[5:0]: Peripheral clock frequency
                                         @ The FREQ bits must be configured with the APB clock frequency value (I2C peripheral
                                         @ connected to APB). The FREQ field is used by the peripheral to generate data setup and
                                         @ hold times compliant with the I2C specifications. The minimum allowed frequency is 2 MHz,
                                         @ the maximum frequency is limited by the maximum APB1 frequency and cannot exceed
                                         @ 50 MHz (peripheral intrinsic maximum limit).
                                         @ 0b000000: Not allowed
                                         @ 0b000001: Not allowed
                                         @ 0b000010: 2 MHz
                                         @ ...
                                         @ 0b110010: 50 MHz
                                         @ Higher than 0b101010: Not allowed
.EQU  I2C_CR2_FREQ_0     , 0x0001        @ Bit 0
.EQU  I2C_CR2_FREQ_1     , 0x0002        @ Bit 1
.EQU  I2C_CR2_FREQ_2     , 0x0004        @ Bit 2
.EQU  I2C_CR2_FREQ_3     , 0x0008        @ Bit 3
.EQU  I2C_CR2_FREQ_4     , 0x0010        @ Bit 4
.EQU  I2C_CR2_FREQ_5     , 0x0020        @ Bit 5
.EQU  I2C_CR2_ITERREN    , 1<<8          @ Bit 8 ITERREN: Error interrupt enable
                                         @ 0: Error interrupt disabled
                                         @ 1: Error interrupt enabled
                                         @ This interrupt is generated when:
                                         @ –BERR =1
                                         @ –ARLO =1
                                         @ –AF =1
                                         @ –OVR =1
                                         @ – PECERR = 1
                                         @ – TIMEOUT = 1
                                         @ – SMBALERT = 1
.EQU  I2C_CR2_ITEVTEN    , 1<<9          @ Bit 9 ITEVTEN: Event interrupt enable
                                         @ 0: Event interrupt disabled
                                         @ 1: Event interrupt enabled
                                         @ This interrupt is generated when:
                                         @ – SB = 1 (Master)
                                         @ – ADDR = 1 (Master/Slave)
                                         @ – ADD10= 1 (Master)
                                         @ – STOPF = 1 (Slave)
                                         @ – BTF = 1 with no TxE or RxNE event
                                         @ – TxE event to 1 if ITBUFEN = 1
                                         @ – RxNE event to 1if ITBUFEN = 1
.EQU  I2C_CR2_ITBUFEN    , 1<<10         @ Bit 10 ITBUFEN: Buffer interrupt enable
                                         @ 0: TxE = 1 or RxNE = 1 does not generate any interrupt.
                                         @ 1: TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)
.EQU  I2C_CR2_DMAEN      , 1<<11         @ Bit 11 DMAEN: DMA requests enable
                                         @ 0: DMA requests disabled
                                         @ 1: DMA request enabled when TxE=1 or RxNE =1
.EQU  I2C_CR2_LAST       , 1<<12         @ Bit 12 LAST: DMA last transfer
                                         @ 0: Next DMA EOT is not the last transfer
                                         @ 1: Next DMA EOT is the last transfer
                                   @ Note: This bit is used in master receiver mode to permit the generation of a NACK on the last
                                         @ received data.
@.end

@.item     I2C_OAR1
.EQU  I2C_OAR1_ADD0_N, 0           @ Bit 0 ADD0: Interface address
                                   @ 7-bit addressing mode: don’t care
                                   @ 10-bit addressing mode: bit 0 of address
.EQU  I2C_OAR1_ADD71_N, 1          @ Bits 7:1 ADD[7:1]: Interface address
                                   @ bits 7:1 of address
.EQU  I2C_OAR1_ADD98_N, 8          @ Bits 9:8 ADD[9:8]: Interface address
                                   @ 7-bit addressing mode: don’t care
                                   @ 10-bit addressing mode: bits9:8 of address
.EQU  I2C_OAR1_ADDMODE, 1 << 15    @ Bit 15 ADDMODE Addressing mode (slave mode)
                                   @ 0: 7-bit slave address (10-bit address not acknowledged)
                                   @ 1: 10-bit slave address (7-bit address not acknowledged)
@.end

@.item     I2C_OAR2
.EQU  I2C_OAR2_ENDUAL    , 1       @ Bit 0 ENDUAL: Dual addressing mode enable
                                   @ 0: Only OAR1 is recognized in 7-bit addressing mode
                                   @ 1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode
.EQU  I2C_OAR2_ADD2_N    , 1       @ Bits 7:1 ADD2[7:1]: Interface address
                                   @ bits 7:1 of address in dual addressing mode
@.END

@.item     I2C_DR
.EQU  I2C_DR_DR          , 0xFF          @ 8-bit Data Register
@.end

@.item     I2C_SR1
.EQU  I2C_SR1_SB         , 1             @ Bit 0 SB: Start bit (Master mode)
                                         @ 0: No Start condition
                                         @ 1: Start condition generated.
                                         @ – Set when a Start condition generated.
                                         @ – Cleared by software by reading the SR1 register followed by writing the DR register, or by
                                         @ hardware when PE=0
.EQU  I2C_SR1_SB_N       , 0
.EQU  I2C_SR1_ADDR       , 1<<1          @ Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
                                         @ This bit is cleared by software reading SR1 register followed reading SR2, or by hardware
                                         @ when PE=0.
                                         @ Address matched (Slave)
                                         @ 0: Address mismatched or not received.
                                         @ 1: Received address matched.
                                         @ – Set by hardware as soon as the received slave address matched with the OAR registers
                                         @ content or a general call or a SMBus Device Default Address or SMBus Host or SMBus Alert
                                         @ is recognized. (when enabled depending on configuration).
                                   @ Note: In slave mode, it is recommended to perform the complete clearing sequence (READ
                                         @ SR1 then READ SR2) after ADDR is set. Refer to Figure 211.
                                         @ Address sent (Master)
                                         @ 0: No end of address transmission
                                         @ 1: End of address transmission
                                         @ – For 10-bit addressing, the bit is set after the ACK of the 2nd byte.
                                         @ – For 7-bit addressing, the bit is set after the ACK of the byte.
                                   @ Note: ADDR is not set after a NACK reception
.EQU  I2C_SR1_ADDR_N     , 1
.EQU  I2C_SR1_BTF        , 1<<2          @ Bit 2 BTF: Byte transfer finished
                                         @ 0: Data byte transfer not done
                                         @ 1: Data byte transfer succeeded
                                         @ – Set by hardware when NOSTRETCH=0 and:
                                         @ – In reception when a new byte is received (including ACK pulse) and DR has not been read
                                         @ yet (RxNE=1).
                                         @ – In transmission when a new byte should be sent and DR has not been written yet (TxE=1).
                                         @ – Cleared by software by either a read or write in the DR register or by hardware after a start or
                                         @ a stop condition in transmission or when PE=0.
                                         @ Note: The BTF bit is not set after a NACK reception
                                         @ The BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2
                                         @ register and PEC=1 in I2C_CR1 register)
.EQU  I2C_SR1_BTF_N      , 2
.EQU  I2C_SR1_ADD10      , 1<<3          @ Bit 3 ADD10: 10-bit header sent (Master mode)
                                         @ 0: No ADD10 event occurred.
                                         @ 1: Master has sent first address byte (header).
                                         @ – Set by hardware when the master has sent the first byte in 10-bit address mode.
                                         @ – Cleared by software reading the SR1 register followed by a write in the DR register of the
                                         @ second address byte, or by hardware when PE=0.
                                   @ Note: ADD10 bit is not set after a NACK reception
.EQU  I2C_SR1_STOPF      , 1<<4          @ Bit 4 STOPF: Stop detection (slave mode)
                                         @ 0: No Stop condition detected
                                         @ 1: Stop condition detected
                                         @ – Set by hardware when a Stop condition is detected on the bus by the slave after an
                                         @ acknowledge (if ACK=1).
                                         @ – Cleared by software reading the SR1 register followed by a write in the CR1 register, or by
                                         @ hardware when PE=0
                                   @ Note: The STOPF bit is not set after a NACK reception.
                                         @ It is recommended to perform the complete clearing sequence (READ SR1 then
                                         @ WRITE CR1) after the STOPF is set. Refer to Figure 211.
.EQU  I2C_SR1_RXNE       , 1<<6          @ Bit 6 RxNE: Data register not empty (receivers)
                                         @ 0: Data register empty
                                         @ 1: Data register not empty
                                         @ – Set when data register is not empty in receiver mode. RxNE is not set during address phase.
                                         @ – Cleared by software reading or writing the DR register or by hardware when PE=0.
                                         @ RxNE is not set in case of ARLO event.
                                         @ Note: RxNE is not cleared by reading data when BTF is set, as the data register is still full.
.EQU  I2C_SR1_TXE        , 1<<7          @ Bit 7 TxE: Data register empty (transmitters)
                                         @ 0: Data register not empty
                                         @ 1: Data register empty
                                         @ – Set when DR is empty in transmission. TxE is not set during address phase.
                                         @ – Cleared by software writing to the DR register or by hardware after a start or a stop condition
                                         @ or when PE=0.
                                         @ TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
                                   @ Note: TxE is not cleared by writing the first data being transmitted, or by writing data when
                                         @ BTF is set, as in both cases the data register is still empty.
.EQU  I2C_SR1_TXE_N      , 7
.EQU  I2C_SR1_BERR       , 1<<8          @ Bit 8 BERR: Bus error
                                         @ 0: No misplaced Start or Stop condition
                                         @ 1: Misplaced Start or Stop condition
                                         @ – Set by hardware when the interface detects an SDA rising or falling edge while SCL is high,
                                         @ occurring in a non-valid position during a byte transfer.
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
.EQU  I2C_SR1_ARLO       , 1<<9          @ Bit 9 ARLO: Arbitration lost (master mode)
                                         @ 0: No Arbitration Lost detected
                                         @ 1: Arbitration Lost detected
                                         @ Set by hardware when the interface loses the arbitration of the bus to another master
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
                                         @ After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
                                         @ Note: In SMBUS, the arbitration on the data in slave mode occurs only during the data phase,
                                         @ or the acknowledge transmission (not on the address acknowledge).
.EQU  I2C_SR1_AF         , 1<<10         @ Bit 10 AF: Acknowledge failure
                                         @ 0: No acknowledge failure
                                         @ 1: Acknowledge failure
                                         @ – Set by hardware when no acknowledge is returned.
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
.EQU  I2C_SR1_AF_N       , 10
.EQU  I2C_SR1_OVR        , 1<<11         @ Bit 11 OVR: Overrun/Underrun
                                         @ 0: No overrun/underrun
                                         @ 1: Overrun or underrun
                                         @ – Set by hardware in slave mode when NOSTRETCH=1 and:
                                         @ – In reception when a new byte is received (including ACK pulse) and the DR register has not
                                         @ been read yet. New received byte is lost.
                                         @ – In transmission when a new byte should be sent and the DR register has not been written
                                         @ yet. The same byte is sent twice.
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
                                   @ Note: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a
                                         @ hold timing error occurs
.EQU  I2C_SR1_PECERR     , 1<<12         @ Bit 12 PECERR: PEC Error in reception
                                         @ 0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
                                         @ 1: PEC error: receiver returns NACK after PEC reception (whatever ACK)
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
                                         @ Note: When the received CRC is wrong, PECERR is not set in slave mode if the PEC control
                                         @ bit is not set before the end of the CRC reception. Nevertheless, reading the PEC value
                                         @ determines whether the received CRC is right or wrong.
.EQU  I2C_SR1_TIMEOUT    , 1<<14         @ Bit 14 TIMEOUT: Timeout or Tlow error
                                         @ 0: No timeout error
                                         @ 1: SCL remained LOW for 25 ms (Timeout)
                                         @ or
                                         @ Master cumulative clock low extend time more than 10 ms (Tlow:mext)
                                         @ or
                                         @ Slave cumulative clock low extend time more than 25 ms (Tlow:sext)
                                         @ – When set in slave mode: slave resets the communication and lines are released by
                                         @ hardware
                                         @ – When set in master mode: Stop condition sent by hardware
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
                                         @ Note: This functionality is available only in SMBus mode.
.EQU  I2C_SR1_SMBALERT   , 1<<15         @ Bit 15 SMBALERT: SMBus alert
                                         @ In SMBus host mode:
                                         @ 0: no SMBALERT
                                         @ 1: SMBALERT event occurred on pin
                                         @ In SMBus slave mode:
                                         @ 0: no SMBALERT response address header
                                         @ 1: SMBALERT response address header to SMBALERT LOW received
                                         @ – Cleared by software writing 0, or by hardware when PE=0.
@.end

@.item     I2C_SR2
.EQU  I2C_SR2_MSL        , 1             @ Bit 0 MSL: Master/slave
                                         @ 0: Slave Mode
                                         @ 1: Master Mode
                                         @ – Set by hardware as soon as the interface is in Master mode (SB=1).
                                         @ – Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
                                         @ (ARLO=1), or by hardware when PE=0.
.EQU  I2C_SR2_BUSY       , 1<<1          @ Bit 1 BUSY: Bus busy
                                         @ 0: No communication on the bus
                                         @ 1: Communication ongoing on the bus
                                         @ – Set by hardware on detection of SDA or SCL low
                                         @ – cleared by hardware on detection of a Stop condition.
                                         @ It indicates a communication in progress on the bus. This information is still updated when
                                         @ the interface is disabled (PE=0).
.EQU  I2C_SR2_BUSY_N     , 1             @
.EQU  I2C_SR2_TRA        , 1<<2          @ Bit 2 TRA: Transmitter/receiver
                                         @ 0: Data bytes received
                                         @ 1: Data bytes transmitted
                                         @ This bit is set depending on the R/W bit of the address byte, at the end of total address
                                         @ phase.
                                         @ It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start
                                         @ condition, loss of bus arbitration (ARLO=1), or when PE=0.
.EQU  I2C_SR2_GENCALL    , 1<<4          @ Bit 4 GENCALL: General call address (Slave mode)
                                         @ 0: No General Call
                                         @ 1: General Call Address received when ENGC=1
                                         @ – Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
.EQU  I2C_SR2_SMBDEFAULT , 1<<5          @ Bit 5 SMBDEFAULT: SMBus device default address (Slave mode)
                                         @ 0: No SMBus Device Default address
                                         @ 1: SMBus Device Default address received when ENARP=1
                                         @ – Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
.EQU  I2C_SR2_SMBHOST    , 1<<6          @ Bit 6 SMBHOST: SMBus host header (Slave mode)
                                         @ 0: No SMBus Host address
                                         @ 1: SMBus Host address received when SMBTYPE=1 and ENARP=1.
                                         @ – Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
.EQU  I2C_SR2_DUALF      , 1<<7          @ Bit 7 DUALF: Dual flag (Slave mode)
                                         @ 0: Received address matched with OAR1
                                         @ 1: Received address matched with OAR2
                                         @ – Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
.EQU  I2C_SR2_PEC_N      , 8             @ Bits 15:8 PEC[7:0] Packet error checking register
                                         @ This register contains the internal PEC when ENPEC=1.
@.end

@.item     I2C_CCR
.EQU  I2C_CCR_CCR_N      , 0             @ Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
                                         @ Controls the SCL clock in master mode.
                                         @ Sm mode or SMBus:
                                         @ Thigh = CCR * TPCLK1
                                         @ Tlow = CCR * TPCLK1
                                         @ Fm mode:
                                         @ If DUTY = 0:
                                         @ Thigh = CCR * TPCLK1
                                         @ Tlow = 2 * CCR * TPCLK1
                                         @ If DUTY = 1:
                                         @ Thigh = 9 * CCR * TPCLK1
                                         @ Tlow = 16 * CCR * TPCLK1
                                         @ For instance: in Sm mode, to generate a 100 kHz SCL frequency:
                                         @ If FREQ = 08, TPCLK1 = 125 ns so CCR must be programmed with 0x28
                                         @ (0x28 <=> 40d x 125 ns = 5000 ns.)
                                   @ Note: The minimum allowed value is 0x04, except in FAST DUTY mode where the minimum
                                         @ allowed value is 0x01
                                         @ thigh = tr(SCL) + tw(SCLH). See device datasheet for the definitions of parameters.
                                         @ tlow = tf(SCL) + tw(SCLL). See device datasheet for the definitions of parameters.
                                         @ I2C communication speed, fSCL ~ 1/(thigh + tlow). The real frequency may differ due to
                                         @ the analog noise filter input delay.
                                         @ The CCR register must be configured only when the I2C is disabled (PE = 0).
.EQU  I2C_CCR_DUTY       , 1<<14         @ Bit 14 DUTY: Fm mode duty cycle
                                         @ 0: Fm mode tlow/thigh = 2
                                         @ 1: Fm mode tlow/thigh = 16/9 (see CCR)
.EQU  I2C_CCR_FS         , 1<<15         @ Bit 15 F/S: I2C master mode selection
                                         @ 0: Sm mode I2C
                                         @ 1: Fm mode I2C
@.end

@.item     I2C_TRISE
.EQU  I2C_TRISE_TRISE_M  , 0x3F          @ Maximum Rise Time in Fast/Standard mode (Master mode)
@.end


