@GNU AS
@.CHARSET =CP1251 ( Cyrillic )

@.DESC     type=module
@ +------------------------------------------------------------------+
@ |               Константы SCB (System control block)               |
@ |                           Cortex-M3 Core                         |
@ +------------------------------------------------------------------+
@.ENDDESC

.INCLUDE    "/src/inc/base.inc"

@.ITEM     SCB_BASE
.EQU  SCB_CPUID     , 0x00      @ (R) CPUID base register (SCB_CPUID)
.EQU  SCB_ICSR      , 0x04      @ (R/W) Interrupt Control and State Register
.EQU  SCB_VTOR      , 0x08      @ (R/W) Vector Table Offset Register
.EQU  SCB_AIRCR     , 0x0C      @ (R/W) Application Interrupt and Reset Control Register
.EQU  SCB_SCR       , 0x10      @ (R/W) System Control Register
.EQU  SCB_CCR       , 0x14      @ (R/W) Configuration Control Register
.EQU  SCB_SHPR1     , 0x18      @ (R/W) System Handlers Priority Registers (4-7)
.EQU  SCB_SHPR2     , 0x1C      @ (R/W)                                    (8-11)
.EQU  SCB_SHPR3     , 0x20      @ (R/W)                                    (12-15)
.EQU  SCB_SHCSR     , 0x24      @ (R/W) System Handler Control and State Register
.EQU  SCB_CFSR      , 0x28      @ (R/W) Configurable Fault Status Register
.EQU  SCB_HFSR      , 0x2C      @ (R/W) HardFault Status Register
.EQU  SCB_DFSR      , 0x30      @ (R/W) Debug Fault Status Register
.EQU  SCB_MMAR      , 0x34      @ (R/W) MemManage Fault Address Register
.EQU  SCB_BFAR      , 0x38      @ (R/W) BusFault Address Register
.EQU  SCB_AFSR      , 0x03C     @ (R/W) Auxiliary Fault Status Register
.EQU  SCB_PFR0      , 0x040     @ (R)  Processor Feature Register
.EQU  SCB_PFR1      , 0x044     @ (R)  Processor Feature Register
.EQU  SCB_DFR       , 0x048     @ (R)  Debug Feature Register
.EQU  SCB_ADR       , 0x04C     @ (R)  Auxiliary Feature Register
.EQU  SCB_MMFR0     , 0x050     @ (R)  Memory Model Feature Register
.EQU  SCB_MMFR1     , 0x054     @ (R)  Memory Model Feature Register
.EQU  SCB_MMFR2     , 0x058     @ (R)  Memory Model Feature Register
.EQU  SCB_MMFR3     , 0x05C     @ (R)  Memory Model Feature Register
.EQU  SCB_ISAR0     , 0x060     @ (R)  Instruction Set Attributes Register
.EQU  SCB_ISAR1     , 0x060     @ (R)  Instruction Set Attributes Register
.EQU  SCB_ISAR2     , 0x060     @ (R)  Instruction Set Attributes Register
.EQU  SCB_ISAR3     , 0x060     @ (R)  Instruction Set Attributes Register
.EQU  SCB_ISAR4     , 0x060     @ (R)  Instruction Set Attributes Register
                                @ reserved
.EQU  SCB_CPACR     , 0x088     @ (R/W)  Coprocessor Access Control Register
@.END

@.ITEM     SCB_CPUID
.EQU  SCB_CPUID_IMPLEMENTER_N, 24                  @ Bits 31:24 Implementer: Implementer code
.EQU  SCB_CPUID_IMPLEMENTER, 0X41 << 24            @ 0x41: Arm
.EQU  SCB_CPUID_VARIANT_N, 20                      @ Bits 23:20 Variant: Variant number: The r value in the rnpn product revision identifier
.EQU  SCB_CPUID_VARIANT1, 0X1 << 20                @ 0x1: r1
.EQU  SCB_CPUID_VARIANT2, 0X2 << 20                @ 0x2: r2
.EQU  SCB_CPUID_CONSANT_N, 16                      @ Bits 19:16 Constant: Reads as 0xF
.EQU  SCB_CPUID_CONSTANT, 0xF << 16                @ 0xF
.EQU  SCB_CPUID_PARTNO_N, 4                        @ Bits 15:4 PartNo: Part number of the processor
.EQU  SCB_CPUID_CONSTANT, 0xC23 << 4               @ 0xC23 = Cortex-M3
.EQU  SCB_CPUID_REVISION_N, 0                      @ Bits 3:0 Revision: Revision number The        p value in the rnpn product revision identifier, indicates patch release
.EQU  SCB_CPUID_REVISION0, 0                       @ 0x0: = p0
.EQU  SCB_CPUID_REVISION1, 1                       @ 0x1: = p1
@.END

@.ITEM     SCB_ICSR
.EQU  SCB_ICSR_NMIPENDSET, 1 << 31                 @ Bit 31 NMIPENDSET: NMI set-pending bit.
.EQU  SCB_ICSR_PENDSVSET, 1 << 28                  @ Bit 28 PENDSVSET: PendSV set-pending bit
.EQU  SCB_ICSR_PENDSVCLR, 1 << 27                  @ Bit 27 PENDSVCLR: PendSV clear-pending bit.
.EQU  SCB_ICSR_PENDSTSET, 1 << 26                  @ Bit 26 PENDSTSET: SysTick exception set-pending bit
.EQU  SCB_ICSR_PENDSTCLR, 1 << 25                  @ Bit 25 PENDSTCLR: SysTick exception clear-pending bit.
.EQU  SCB_ICSR_ISRPENDING, 1 << 22                 @ Bit 22 ISRPENDING: Interrupt pending flag, excluding NMI and Faults
.EQU  SCB_ICSR_VECTPENDING_N, 12                   @ Bits 21:12 VECTPENDING[9:0] Pending vector
.EQU  SCB_ICSR_RETOBASE, 1 << 11                   @ Bit 11 RETOBASE: Return to base level
.EQU  SCB_ICSR_VECTACTIVE_N, 0                     @ Bits 8:0 VECTACTIVE[8:0] Active vector
@.END

@.ITEM     SCB_VTOR
.EQU  SCB_VTOR_TBLOFF_N, 9
.EQU  SCB_VTOR_TBLOFF, 1 << 29                     @ Bits 29:9 TBLOFF[29:9]: Vector table base offset field.
@.END

@.ITEM     SCB_AIRCR
.EQU  SCB_AIRCR_VECTKEYSTAT_N, 16                  @ Bits 31:16 VECTKEYSTAT[15:0]/ VECTKEY[15:0] Register key
.EQU  SCB_AIRCR_ENDIANESS, 15                      @ Bit 15 ENDIANESS Data endianness bit
.EQU  SCB_AIRCR_PRIGROUP, 8                        @ Bits 10:8 PRIGROUP[2:0]: Interrupt priority grouping field
.EQU  SCB_AIRCR_SYSRESETREQ, 1 << 2                @ Bit 2 SYSRESETREQ System reset request
.EQU  SCB_AIRCR_VECTCLRACTIVE, 1 << 1              @ Bit 1 VECTCLRACTIVE  Reserved   for Debug use. This bit reads as 0. When writing to the register you must write 0 to  this       bit, otherwise behavior is unpredictable
.EQU  SCB_AIRCR_VECTRESET, 1                       @ Bit 0 VECTRESET Reserved   for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is unpredictable.
@.END

@.ITEM     SCB_SCR
.EQU  SCB_SCR_SEVEONPEND, 1 << 4                   @ Bit 4 SEVEONPEND Send Event on Pending bit
.EQU  SCB_SCR_SLEEPDEEP, 1 << 2                    @ Bit 2 SLEEPDEEP Controls   whether the processor uses sleep or deep sleep as its low power mode
.EQU  SCB_SCR_SLEEPONEXIT, 1 << 1                  @ Bit 1 SLEEPONEXIT  Configures  sleep - on - exit when returning from Handler mode to Thread mode. Setting this bit to  1  enables an interrupt - driven application to avoid returning to an empty main application.
@.END

@.ITEM     SCB_CCR
.EQU  SCB_CCR_STKALIGN, 1 << 9                     @ Bit 9 STKALIGN  Configures  stack alignment on exception entry. On exception entry, the processor uses bit 9 of  the        stacked PSR to indicate the stack alignment. On return from the exception it uses this  stacked    bit to restore the correct stack alignment
.EQU  SCB_CCR_BFHFNMIGN, 1 << 8                    @ Bit 8 BFHFNMIGN  Enables    handlers with priority - 1 or - 2 to ignore data bus faults caused by load and store instructions
.EQU  SCB_CCR_DIV_0_TRP, 1 << 4                    @ Bit 4 DIV_0_TRP  Enables    faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
.EQU  SCB_CCR_UNALIGN_TRP, 1 << 3                  @ Bit 3 UNALIGN_TRP  Enables    unaligned access traps
.EQU  SCB_CCR_USERSETMPEND, 1 << 1                 @ Bit 1 USERSETMPEND Enables    unprivileged software access to the STIR
.EQU  SCB_CCR_NONBASETHRDENA, 1                    @ Bit 0 NONBASETHRDENA  Configures  how the processor enters Thread mode
@.END

@.ITEM     SCB_SHPR1
.EQU  SCB_SHPR1_PRI_4_N, 0                         @ Bits 7:0 PRI_4[7:0]: Priority of system handler 4, memory management fault
.EQU  SCB_SHPR1_PRI_5_N, 8                         @ Bits 15:8 PRI_5[7:0]: Priority of system handler 5, bus fault
.EQU  SCB_SHPR1_PRI_6_N, 16                        @ Bits 23:16 PRI_6[7:0]: Priority of system handler 6, usage fault
@.END

@.ITEM     SCB_SHPR2
.EQU  SCB_SHPR1_PRI_11_N, 24                       @ Bits 31:24 PRI_11[7:0]: Priority of system handler 11, SVCall
@.END

@.ITEM     SCB_SHPR3
.EQU  SCB_SHPR3_PRI_15_N, 24                       @ Bits 31:24 PRI_15[7:0]: Priority of system handler 15, SysTick exception
.EQU  SCB_SHPR3_PRI_14_N, 16                       @ Bits 23:16 PRI_14[7:0]: Priority of system handler 14, PendSV
@.END

@.ITEM     SCB_SHCSR
.EQU  SCB_SCB_SHCSR_USGFAULTENA, 1 << 18           @ Bit 18 USGFAULTENA: Usage fault enable bit, set to 1 to enable
.EQU  SCB_SCB_SHCSR_BUSFAULTENA, 1 << 17           @ Bit 17 BUSFAULTENA: Bus fault enable bit, set to 1 to enable
.EQU  SCB_SCB_SHCSR_MEMFAULTENA, 1 << 16           @ Bit 16 MEMFAULTENA: Memory management fault enable bit, set to 1 to enable
.EQU  SCB_SCB_SHCSR_SVCALLPENDED, 1 << 15          @ Bit 15 SVCALLPENDED: SVC call pending bit, reads as 1 if exception is pending
.EQU  SCB_SCB_SHCSR_BUSFAULTPENDED, 1 << 14        @ Bit 14 BUSFAULTPENDED: Bus fault exception pending bit, reads as 1 if exception is pending
.EQU  SCB_SCB_SHCSR_MEMFAULTPENDED, 1 << 13        @ Bit 13 MEMFAULTPENDED: Memory management fault exception pending bit, reads as 1 if exception  is pending
.EQU  SCB_SCB_SHCSR_USGFAULTPENDED, 1 << 12        @ Bit 12 USGFAULTPENDED: Usage fault exception pending bit, reads as 1 if exception is pending
.EQU  SCB_SCB_SHCSR_SYSTICKACT, 1 << 11            @ Bit 11 SYSTICKACT: SysTick exception active bit, reads as 1 if exception is active
.EQU  SCB_SCB_SHCSR_PENDSVACT, 1 << 10             @ Bit 10 PENDSVACT: PendSV exception active bit, reads as 1 if exception is active
.EQU  SCB_SCB_SHCSR_MONITORACT, 1 << 8             @ Bit 8 MONITORACT: Debug monitor active bit, reads as 1 if Debug monitor is active
.EQU  SCB_SCB_SHCSR_SVCALLACT, 1 << 7              @ Bit 7 SVCALLACT: SVC call active bit, reads as 1 if SVC call is active
.EQU  SCB_SCB_SHCSR_USGFAULTACT, 1 << 3            @ Bit 3 USGFAULTACT: Usage fault exception active bit, reads as 1 if exception is active
.EQU  SCB_SCB_SHCSR_BUSFAULTACT, 1 << 1            @ Bit 1 BUSFAULTACT: Bus fault exception active bit, reads as 1 if exception is active
.EQU  SCB_SCB_SHCSR_MEMFAULTACT, 1                 @ Bit 0 MEMFAULTACT: Memory management fault exception active bit, reads as 1 if exception is active
@.END


@.ITEM     SCB_CFSR
.EQU  SCB_CFSR_BFSR_ADR, 0xE000ED29                @ Access the BFSR with a byte access to 0xE000ED29
.EQU  SCB_CFSR_UFSR_ADR, 0xE000ED2A                @ Access the UFSR with a halfword access to 0xE000ED2A
.EQU  SCB_CFSR_DIVBYZERO, 1 << 25                  @ Bit 25 DIVBYZERO: Divide by zero usage fault
.EQU  SCB_CFSR_UNALIGNED, 1 << 24                  @ Bit 24 UNALIGNED: Unaligned access usage fault
.EQU  SCB_CFSR_NOCP , 1 << 19                      @ Bit 19 NOCP: No coprocessor usage fault. The processor does not support coprocessor instructions
.EQU  SCB_CFSR_INVPC, 1 << 18                      @ Bit 18 INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN
.EQU  SCB_CFSR_INVSTATE, 1 << 17                   @ Bit 17 INVSTATE: Invalid state usage fault
.EQU  SCB_CFSR_UNDEFINSTR, 1 << 16                 @ Bit 16 UNDEFINSTR: Undefined instruction usage fault
.EQU  SCB_CFSR_BFARVALID, 1 << 15                  @ Bit 15 BFARVALID: Bus Fault Address Register (BFAR) valid flag
.EQU  SCB_CFSR_STKERR, 1 << 12                     @ Bit 12 STKERR: Bus fault on stacking for exception entry
.EQU  SCB_CFSR_UNSTKERR, 1 << 11                   @ Bit 11 UNSTKERR: Bus fault on unstacking for a return from exception
.EQU  SCB_CFSR_IMPRECISERR, 1 << 10                @ Bit 10 IMPRECISERR: Imprecise data bus error
.EQU  SCB_CFSR_PRECISERR, 1 << 9                   @ Bit 9 PRECISERR: Precise data bus error
.EQU  SCB_CFSR_IBUSERR, 1 << 8                     @ Bit 8 IBUSERR: Instruction bus error
.EQU  SCB_CFSR_MMARVALID, 1 << 7                   @ Bit 7 MMARVALID: Memory Management Fault Address Register (MMAR) valid flag
.EQU  SCB_CFSR_MSTKERR, 1 << 4                     @ Bit 4 MSTKERR: Memory manager fault on stacking for exception entry
.EQU  SCB_CFSR_MUNSTKERR, 1 << 3                   @ Bit 3 MUNSTKERR: Memory manager fault on unstacking for a return from exception
.EQU  SCB_CFSR_DACCVIOL, 1 << 1                    @ Bit 1 DACCVIOL: Data access violation flag
.EQU  SCB_CFSR_IACCVIOL, 1                         @ Bit 1 IACCVIOL: Instruction access violation flag
@.END

@.ITEM     SCB_HFSR
.EQU  SCB_HFSR_DEBUG_VT, 1 << 31                   @ Bit 31 DEBUG_VT: Reserved   for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is unpredictable
.EQU  SCB_HFSR_FORCED, 1 << 30                     @ Bit 30 FORCED: Forced hard fault
.EQU  SCB_HFSR_VECTTBL, 1 << 1                     @ Bit 1 VECTTBL: Vector table hard fault
@.END



