@GNU AS
@.CharSet =CP1251 ( Cyrillic )
@.desc     type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы DBG                    |
@ +------------------------------------------------------------------+
@.enddesc

.include   "/src/inc/base.inc"

@.item     CORE
.equ  DBG_BASE           , CORE + 0x42000
.equ  DBG                , CORE_BASE + DBG_BASE    @Address: 0xE004 2000

@ Debug MCU registers base address

@.item     DBG_BASE DBG
.equ  DBGMCU_IDCODE      , 0x00    @ MCU device ID code
.equ  DBGMCU_CR          , 0x04    @ Debug MCU configuration register
.equ  DBGMCU_APB1_FZ     , 0x08    @ Debug MCU APB1 freeze regist
.equ  DBGMCU_APB2_FZ     , 0x0C    @ Debug MCU APB2 Freeze register
.EQU  DBGMCU_TPIU_CPS    , 0xE0040004 @ current port size
.EQU  DBGMCU_TPIU_SPP    , 0xE00400F0    @ Selected pin protocol
.EQU  DBGMCU_TPIU_FFC    , 0xE0040304    @ Formated and flush control
.EQU  DBGMCU_TPIU_FFS    , 0xE0040300    @ Formated and flush status

@.item     DBGMCU_IDCODE
.equ  DBGMCU_IDCODE_DEV_ID, 0x00000FFF    @ Bits 11:0 DEV_ID[11:0]: Device identifier (STM32F405xx/07xx and STM32F415xx/17xx)
.equ  DBGMCU_IDCODE_REV_ID, 0xFFFF0000    @Bits 31:16 REV_ID[15:0] Revision identifier                                          @This field indicates the revision of the device.                                          @STM32F405xx/07xx and STM32F415xx/17xx devices:

@.item     DBGMCU_CR
.equ  DBGMCU_CR_TRACE_MODE, 0x000000C0    @Bits 7:5 TRACE_MODE[1:0]
.equ  DBGMCU_CR_TRACE_MODE_N, 5
.equ  DBGMCU_CR_TRACE_MODE_1, 4 << 5    @TRACE_MODE=xx: TRACE pins not assigned (default state)
.equ  DBGMCU_CR_TRACE_MODE_0, 2 << 5    @ TRACE_MODE=00: TRACE_MODE=01: TRACE_MODE=10:  TRACE_MODE=11:
.equ  DBGMCU_CR_TRACE_IOEN, 1 << 5    @Bits 5 TRACE_IOEN: Trace pin assigment control
.equ  DBGMCU_CR_DBG_STANDBY, 0x00000004    @ Bit 2 DBG_STANDBY: Debug Standby mode
.equ  DBGMCU_CR_DBG_STOP , 0x00000002    @Bit 1 DBG_STOP: Debug Stop mode
.equ  DBGMCU_CR_DBG_SLEEP, 0x00000001    @Bit 0 DBG_SLEEP: Debug Sleep mode

@.item     DBGMCU_APB1_FZ
.equ  DBGMCU_APB1_FZ_DBG_CAN2_STOP, 1 << 26    @Bit 26 DBG_CAN2_STOP: Debug CAN2 stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_CAN1_STOP, 1 << 25    @Bit 25 DBG_CAN1_STOP: Debug CAN2 stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT, 1 << 23    @Bit 23 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT, 1 << 22    @ Bit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT, 1 << 21    @ Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_IWDG_STOP, 1 << 12    @Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
.equ  DBGMCU_APB1_FZ_DBG_WWDG_STOP, 1 << 11    @Bit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_RTC_STOP, 1 << 10    @Bit 10 DBG_RTC_STOP: RTC stopped when Core is halted
.equ  DBGMCU_APB1_FZ_DBG_TIM14_STOP, 1 << 8    @Bits 8:0 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=2..7, 12..14)
.equ  DBGMCU_APB1_FZ_DBG_TIM13_STOP, 1 << 7
.equ  DBGMCU_APB1_FZ_DBG_TIM12_STOP, 1 << 6
.equ  DBGMCU_APB1_FZ_DBG_TIM7_STOP, 1 << 5
.equ  DBGMCU_APB1_FZ_DBG_TIM6_STOP, 1 << 4
.equ  DBGMCU_APB1_FZ_DBG_TIM5_STOP, 1 << 3
.equ  DBGMCU_APB1_FZ_DBG_TIM4_STOP, 1 << 2
.equ  DBGMCU_APB1_FZ_DBG_TIM3_STOP, 1 << 1
.equ  DBGMCU_APB1_FZ_DBG_TIM2_STOP, 1 << 0

@.item     DBGMCU_APB2_FZ
.equ  DBGMCU_APB2_FZ_DBG_TIM11_STOP, 1 << 18    @Bits 18:16 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..11)
.equ  DBGMCU_APB2_FZ_DBG_TIM10_STOP, 1 << 17
.equ  DBGMCU_APB2_FZ_DBG_TIM9_STOP, 1 << 16
.equ  DBGMCU_APB2_FZ_DBG_TIM8_STOP, 1 << 1    @Bit 1 DBG_TIM8_STOP: TIM8 counter stopped when core is halted
.equ  DBGMCU_APB2_FZ_DBG_TIM1_STOP, 1 << 0    @Bit 0 DBG_TIM1_STOP: TIM1 counter stopped when core is halted














