@.CharSet CP1251
@GNU AS

.include "/src/inc/base.inc"

@.item APB2PERIPH_BASE
.equ SPI                           , 0

@.item SPI
.EQU  SPI1_BASE          , ( APB2PERIPH_BASE + 0x3000 )
.EQU  SPI2_BASE          , ( APB1PERIPH_BASE + 0x3800 )
.EQU  SPI3_BASE          , ( APB1PERIPH_BASE + 0x3C00 )
.EQU  SPI4_BASE          , ( APB2PERIPH_BASE + 0x3400 )
.EQU  SPI1               , PERIPH_BASE + SPI1_BASE
.EQU  SPI2               , PERIPH_BASE + SPI2_BASE
.EQU  SPI3               , PERIPH_BASE + SPI3_BASE
.EQU  SPI4               , PERIPH_BASE + SPI4_BASE
@.end

@.item SPI1_BASE SPI2_BASE SPI3_BASE SPI4_BASE SPI1 SPI2 SPI3 SPI4
.EQU  SPI_CR1            , 0x00          @ SPI control register 1 (SPI_CR1)
.EQU  SPI_CR2            , 0x04          @ SPI control register 2 (SPI_CR2)
.EQU  SPI_SR             , 0x08          @ SPI status register (SPI_SR)
.EQU  SPI_DR             , 0x0C          @ SPI data register (SPI_DR)
.EQU  SPI_CRCPR          , 0x10          @ SPI CRC polynomial register (SPI_CRCPR)
.EQU  SPI_SPI_RXCRCR     , 0x14          @ SPI RX CRC register (SPI_RXCRCR)
.EQU  SPI_SPI_TXCRCR     , 0x18          @ SPI TX CRC register (SPI_TXCRCR)
.EQU  SPI_I2SCFGR        , 0x1C
.EQU  SPI_I2SPR          , 0x20
@.end

@.item SPI_CR1
.EQU  SPI_CR1_CPHA       , 0x0001        @ Bit 0 CPHA: Clock phase
.EQU  SPI_CR1_CPOL       , 0x0002        @ Bit1 CPOL: Clock polarity
.EQU  SPI_CR1_MSTR       , 0x0004        @ Bit 2 MSTR: Master selection
.EQU  SPI_CR1_BR_DIV_2   , 0x00 << 3     @ Bits 5:3 BR[2:0]: Baud rate control
.EQU  SPI_CR1_BR_DIV_4   , 0x01 << 3
.EQU  SPI_CR1_BR_DIV_8   , 0x02 << 3
.EQU  SPI_CR1_BR_DIV_16  , 0x03 << 3
.EQU  SPI_CR1_BR_DIV_32  , 0x04 << 3
.EQU  SPI_CR1_BR_DIV_64  , 0x05 << 3
.EQU  SPI_CR1_BR_DIV_128 , 0x06 << 3
.EQU  SPI_CR1_BR_DIV_256 , 0x07 << 3
.EQU  SPI_CR1_SPE        , 0x0040        @ Bit 6 SPE: SPI enable
.EQU  SPI_CR1_LSBFIRST_LSB, 0x0080       @ Bit 7 LSBFIRST: Frame format
.EQU  SPI_CR1_SSI        , 0x0100        @ Bit 8 SSI: Internal slave select
.EQU  SPI_CR1_SSM        , 0x0200        @ Bit 9 SSM: Software slave management
.EQU  SPI_CR1_RXONLY     , 0x0400        @ Bit 10 RXONLY: Receive only
.EQU  SPI_CR1_DFF_16BIT  , 0x0800        @ Bit 11 DFF: Data frame format
.EQU  SPI_CR1_CRCNEXT    , 0x1000        @ Bit 12 CRCNEXT: CRC transfer next
.EQU  SPI_CR1_CRCEN      , 0x2000        @ Bit 13 CRCEN: Hardware CRC calculation enable
.EQU  SPI_CR1_BIDIOE     , 0x4000        @ Bit 14 BIDIOE: Output enable in bidirectional mode
.EQU  SPI_CR1_BIDIMODE   , 0x8000        @ Bit 15 BIDIMODE: Bidirectional data mode enable
@.end

@.item SPI_CR2
.EQU  SPI_CR2_RXDMAEN    , 0x01          @ Bit 0 RXDMAEN: Rx buffer DMA enable
.EQU  SPI_CR2_TXDMAEN_N  , 1             @ Bit 1 TXDMAEN: Tx buffer DMA enable
.EQU  SPI_CR2_TXDMAEN    , 0x02          @ Bit 1 TXDMAEN: Tx buffer DMA enable
.EQU  SPI_CR2_SSOE       , 0x04          @ Bit 2 SSOE: SS output enable
.EQU  SPI_CR2_FRF        , 0x10          @ Bit 4 FRF: Frame format
.EQU  SPI_CR2_ERRIE      , 0x20          @ Bit 5 ERRIE: Error interrupt enabled
.EQU  SPI_CR2_RXNEIE     , 0x40          @ Bit 6 RXNEIE: RX buffer not empty interrupt enable
.EQU  SPI_CR2_TXEIE      , 0x80          @ Bit 7 TXEIE: Tx buffer empty interrupt enable
@.end

@.item SPI_SR
.EQU  SPI_SR_RXNE        , 0x01          @ Bit 0 RXNE: Receive buffer not empty
.EQU  SPI_SR_TXE         , 0x02          @ Bit 1 TXE: Transmit buffer empty
.EQU  SPI_SR_CHSIDE      , 0x04          @ Bit 2 CHSIDE: Channel side
.EQU  SPI_SR_UDR         , 0x08          @ Bit 3 UDR: Underrun flag
.EQU  SPI_SR_CRCERR      , 0x10          @ Bit 4 CRCERR: CRC error flag
.EQU  SPI_SR_MODF        , 0x20          @ Bit 5 MODF: Mode fault
.EQU  SPI_SR_OVR         , 0x40          @ Bit 6 OVR: Overrun flag
.EQU  SPI_SR_BSY         , 0x80          @ Bit 7 BSY: Busy flag
.EQU  SPI_SR_FRE         , 0x0100        @ Bit 8 FRE: Frame format error
@.end

@ маппинг SPI 1
@+------+--------+-------+-------+--------+--------+
@|          AF5  |  NSS  |  SCK  |  MISO  |  MOSI  |
@+---------------+-------+-------+--------+--------+
@| GPIOA         |  PA4  |  PA5  |  PA6   |  PA7   |
@|               |  PA15 |       |        |        |
@+---------------+-------+-------+--------+--------+
@| GPIOB         |       |  PB3  |  PB4   |  PB5   |
@+---------------+-------+-------+--------+--------+

@ маппинг SPI 2
@+------+--------+-------+-------+--------+--------+
@|          AF5  |  NSS  |  SCK  |  MISO  |  MOSI  |
@+---------------+-------+-------+--------+--------+
@| GPIOB         |  PB9  |  PB10 |  PB14  |  PB15  |
@|               |  PB12 |  PB13 |        |        |
@+---------------+-------+-------+--------+--------+
@| GPIOC         |       |       |  PC2   |  PC3   |
@+---------------+-------+-------+--------+--------+
@| GPIOI         |  PI0  |  PI1  |  PI2   |  PI3   |
@+---------------+-------+-------+--------+--------+

@.item SPI_I2SCFGR
.EQU  SPI_I2SCFGR_CHLEN_N , 0             @ Bit 0 CHLEN: Channel length (number of bits per audio channel)
.EQU  SPI_I2SCFGR_CHLEN_16B, 0            @ 16-bit wide
.EQU  SPI_I2SCFGR_CHLEN_32B, 1            @ 32-bit wide
.EQU  SPI_I2SCFGR_DATLEN_N, 1             @ Bits 2:1 DATLEN: Data length to be transferred
.EQU  SPI_I2SCFGR_DATLEN_16B, 0 << 1      @ 16-bit wide
.EQU  SPI_I2SCFGR_DATLEN_24B, 1 << 1      @ 24-bit wide
.EQU  SPI_I2SCFGR_DATLEN_32B, 2 << 1      @ 32-bit wide
.EQU  SPI_I2SCFGR_CKPOL_N , 3             @ Bit 3 CKPOL: Steady state clock polarity
.EQU  SPI_I2SCFGR_I2SSTD_N, 4             @ Bits 5:4 I2SSTD: I2S standard selection
.EQU  SPI_I2SCFGR_I2SSTD_I2S, 0 << 4      @ I2S Philips standard
.EQU  SPI_I2SCFGR_I2SSTD_MSB, 1 << 4      @ MSB justified standard (left justified)
.EQU  SPI_I2SCFGR_I2SSTD_LSB, 2 << 4      @ LSB justified standard (right justified)
.EQU  SPI_I2SCFGR_I2SSTD_PCM, 3 << 4      @ PCM standard
.EQU  SPI_I2SCFGR_PCMSYNC_N, 7            @ Bit 7 PCMSYNC: PCM frame synchronization
.EQU  SPI_I2SCFGR_I2SCFG_N, 8             @ Bits 9:8 I2SCFG: I2S configuration mode
.EQU  SPI_I2SCFGR_I2SCFG_SLTR, 0 << 8     @ Slave - transmit
.EQU  SPI_I2SCFGR_I2SCFG_SLREC, 1 << 8    @ Slave - receive
.EQU  SPI_I2SCFGR_I2SCFG_MSTR, 2 << 8     @ Master - transmit
.EQU  SPI_I2SCFGR_I2SCFG_MSREC, 3 << 8    @ Master - receive
.EQU  SPI_I2SCFGR_I2SE_N  , 10            @ Bit 10 I2SE: I2S Enable
.EQU  SPI_I2SCFGR_I2SMOD_N, 11            @ Bit 11 I2SMOD: I2S mode selection
.EQU  SPI_I2SCFGR_I2SMOD_SPI, 0 << 11     @ SPI mode is selected
.EQU  SPI_I2SCFGR_I2SMOD_I2S, 1 << 11     @ I2S mode is selected
@.end

@.item SPI_I2SPR
.EQU  SPI_I2SPR_I2SDIV_N , 0             @ Bits 7:0 I2SDIV: I2S Linear prescaler
.EQU  SPI_I2SPR_ODD_N    , 8             @ Bit 8 ODD: Odd factor for the prescaler
.EQU  SPI_I2SPR_MCKOE_N  , 9             @ Bit 9 MCKOE: Master clock output enable
@.END

