@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы RCC                        |
@ |                         STM32L100xxx                             |
@ +------------------------------------------------------------------+
@.ENDDESC


.INCLUDE   "/src/inc/base.inc"

@.ITEM     AHBPERIPH_BASE
.EQU  RCC_BASE      , ( AHBPERIPH_BASE + 0x3800 )    @ Базовый адрес RCC
@.END

@.ITEM     RCC_BASE
.EQU  RCC_CR        , 0x00       @ Clock control register (RCC_CR)
.EQU  RCC_ICSCR     , 0x04       @ Internal clock sources calibration register (RCC_ICSCR)
.EQU  RCC_CFGR      , 0x08       @ Clock configuration register (RCC_CFGR)
.EQU  RCC_CIR       , 0x0C       @ RCC clock interrupt register
.EQU  RCC_AHBRSTR   , 0x10       @ RCC AHB1 peripheral reset register
.EQU  RCC_APB2RSTR  , 0x14       @ RCC APB2 peripheral reset register
.EQU  RCC_APB1RSTR  , 0x18       @ RCC APB1 peripheral reset register
.EQU  RCC_AHBENR    , 0x1C       @ RCC AHB1 peripheral clock register
.EQU  RCC_APB2ENR   , 0x20       @ RCC APB2 peripheral clock enable register
.EQU  RCC_APB1ENR   , 0x24       @ RCC APB1 peripheral clock enable register
.EQU  RCC_AHBLPENR  , 0x28       @ RCC AHB peripheral clock enable in low power mode register
.EQU  RCC_APB2LPENR , 0x2C       @ RCC APB2 peripheral clock enable in low power mode register
.EQU  RCC_APB1LPENR , 0x30       @ RCC APB1 peripheral clock enabled in low power mode register
.EQU  RCC_CSR       , 0x34       @ RCC clock control & status register
@.END

@.ITEM     RCC_CR
.EQU  RCC_CR_HSION_N, 0          @ Bit 0 HSION: Internal high-speed clock enable
                                 @ This bit is set and cleared by software.
                                 @ This bit cannot be cleared if the HSI is used directly or indirectly as the system clock.
                                 @ 0: HSI oscillator OFF
.EQU  RCC_CR_HSION  , 1          @ 1: HSI oscillator ON
.EQU  RCC_CR_HSIRDY_N, 1         @ Bit 1 HSIRDY: Internal high-speed clock ready flag
                                 @ This bit is set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is
                                 @ cleared, HSIRDY goes low after 6 HSI clock cycles.
                                 @ 0: HSI oscillator not ready
.EQU  RCC_CR_HSIRDY , 1 << 1     @ 1: HSI oscillator ready
.EQU  RCC_CR_MSION_N, 8          @ Bit 8 MSION: MSI clock enable
                                 @ This bit is set and cleared by software.
                                 @ Set by hardware to force the MSI oscillator ON when exiting from Stop or Standby mode, or
                                 @ in case of a failure of the HSE oscillator used directly or indirectly as system clock. This bit
                                 @ cannot be cleared if the MSI is used as system clock.
                                 @ 0: MSI oscillator OFF
.EQU  RCC_CR_MSION  , 1 << 8     @ 1: MSI oscillator ON
.EQU  RCC_CR_MSIRDY_N, 9         @ Bit 9 MSIRDY: MSI clock ready flag
                                 @ This bit is set by hardware to indicate that the MSI oscillator is stable.
                                 @ 0: MSI oscillator not ready
.EQU  RCC_CR_MSIRDY , 1 << 9     @ 1: MSI oscillator ready
                           @ Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
.EQU  RCC_CR_HSEON_N, 16         @ Bit 16 HSEON: HSE clock enable
                                 @ This bit is set and cleared by software.
                                 @ Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
                                 @ bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
                                 @ 0: HSE oscillator OFF
.EQU  RCC_CR_HSEON  , 1 << 16    @ 1: HSE oscillator ON
.EQU  RCC_CR_HSERDY_N, 17        @ Bit 17 HSERDY: HSE clock ready flag
                                 @ This bit is set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is
                                 @ cleared, HSERDY goes low after 6 HSE oscillator clock cycles.
                                 @ 0: HSE oscillator not ready
.EQU  RCC_CR_HSERDY , 1 << 17    @ 1: HSE oscillator ready
.EQU  RCC_CR_HSEBYP_N, 18        @ Bit 18 HSEBYP: HSE clock bypass
                                 @ This bit is set and cleared by software to bypass the oscillator with an external clock. The
                                 @ external clock must be enabled with the HSEON bit, to be used by the device.
                                 @ The HSEBYP bit can be written only if the HSE oscillator is disabled.
                                 @ This bit is reset by power on reset, it keeps its value after system reset.
                                 @ 0: HSE oscillator not bypassed
.EQU  RCC_CR_HSEBYP , 1 << 18    @ 1: HSE oscillator bypassed with an external clock
.EQU  RCC_CR_PLLON_N, 24         @ Bit 24 PLLON: PLL enable
                                 @ This bit is set and cleared by software to enable PLL.
                                 @ Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
                                 @ PLL clock is used as system clock or is selected to become the system clock.
                                 @ 0: PLL OFF
.EQU  RCC_CR_PLLON  , 1 << 24    @ 1: PLL ON
.EQU  RCC_CR_PLLRDY_N, 25        @ Bit 25 PLLRDY: PLL clock ready flag
                                 @ This bit is set by hardware to indicate that the PLL is locked.
                                 @ 0: PLL unlocked
.EQU  RCC_CR_PLLRDY , 1 << 25    @ 1: PLL locked
.EQU  RCC_CR_CSSON_N, 28         @ Bit 28 CSSON: Clock security system enable
                                 @ This bit is set and cleared by software to enable the clock security system (CSS). When
                                 @ CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready,
                                 @ and disabled by hardware if an oscillator failure is detected.
                                 @ 0: Clock security system OFF (clock detector OFF)
.EQU  RCC_CR_CSSON  , 1 << 28    @ 1: Clock security system ON (clock detector ON if HSE oscillator is stable, OFF otherwise)
.EQU  RCC_CR_RTCPRE_N, 29        @ Bits 30:29 RTCPRE[1:0] RTC/LCD prescaler
                                 @ These bits are set and reset by software to obtain a 1 MHz clock from HSE. This prescaler
                                 @ cannot be modified if HSE is enabled (HSEON = 1).
                                 @ These bits are reset by power on reset, they keep their value after system reset.
.EQU  RCC_CR_RTCPRE_DIV2, 0          @ 00: HSE is divided by 2 for RTC/LCD clock
.EQU  RCC_CR_RTCPRE_DIV4, 1 << 29    @ 01: HSE is divided by 4 for RTC/LCD clock
.EQU  RCC_CR_RTCPRE_DIV8, 2 << 29    @ 10: HSE is divided by 8 for RTC/LCD clock
.EQU  RCC_CR_RTCPRE_DIV16, 3 << 29   @ 11: HSE is divided by 16 for RTC/LCD clock
@.END

@.ITEM     RCC_ICSCR
.EQU  RCC_ICSCR_MSITRIM_N, 24    @ Bits 31:24 MSITRIM[7:0]: MSI clock trimming
                                 @ These bits are set by software to adjust MSI calibration.
                                 @ These bits provide an additional user-programmable trimming value that is added to the
                                 @ MSICAL[7:0] bits. They can be programmed to compensate for the variations in voltage and
                                 @ temperature that influence the frequency of the internal MSI RC.
.EQU  RCC_ICSCR_MSICAL_N, 16     @ Bits 23:16 MSICAL[7:0]: MSI clock calibration
                                 @ These bits are initialized at startup with the factory-programmed MSI calibration trim value.
                                 @ When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
                                 @ value
.EQU  RCC_ICSCR_MSIRANGE_N, 13   @ Bits 15:13 MSIRANGE[2:0]: MSI clock ranges
                                 @ These bits are set by software to choose the frequency range of MSI.7 frequency ranges are
                                 @ available:
.EQU  RCC_ICSCR_MSIRANGE_65536K, 0  @ 000: range 0 around 65.536 kHz
.EQU  RCC_ICSCR_MSIRANGE_131072K, 1 << 13    @ 001: range 1 around 131.072 kHz
.EQU  RCC_ICSCR_MSIRANGE_262144K, 2 << 13    @ 010: range 2 around 262.144 kHz
.EQU  RCC_ICSCR_MSIRANGE_524288K, 3 << 13    @ 011: range 3 around 524.288 kHz
.EQU  RCC_ICSCR_MSIRANGE_1048M, 4 << 13    @ 100: range 4 around 1.048 MHz
.EQU  RCC_ICSCR_MSIRANGE_2097M, 5 << 13    @ 101: range 5 around 2.097 MHz (reset value)
.EQU  RCC_ICSCR_MSIRANGE_4194M, 6 << 13    @ 110: range 6 around 4.194 MHz
                                           @ 111: not allowed
.EQU  RCC_ICSCR_HSITRIM_N, 8     @ Bits 12:8 HSITRIM[4:0]: High speed internal clock trimming
                                 @ These bits provide an additional user-programmable trimming value that is added to the
                                 @ HSICAL[7:0] bits. They can be programmed to compensated for the variations in voltage and
                                 @ temperature that influence the frequency of the internal HSI RC.
.EQU  RCC_ICSCR_HSICAL_N, 0      @ Bits 7:0 HSICAL[7:0] Internal high speed clock calibration
                                 @ These bits are initialized at startup with the factory-programmed HSI calibration trim value.
                                 @ When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
                                 @  value.
@.END

@.ITEM     RCC_CFGR
.EQU  RCC_CFGR_SW_N , 0          @ Bits 1:0 SW[1:0]: System clock switch
                                 @ These bits are set and cleared by software to select SYSCLK source.
                                 @ Set by hardware to force MSI selection when leaving Stop and Standby mode or in case of
                                 @ failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
                                 @ System is enabled).
.EQU  RCC_CFGR_SW_MSI, 0         @ 00: MSI oscillator used as system clock
.EQU  RCC_CFGR_SW_HSI, 1         @ 01: HSI oscillator used as system clock
.EQU  RCC_CFGR_SW_HSE, 2         @ 10: HSE oscillator used as system clock
.EQU  RCC_CFGR_SW_PLL, 3         @ 11: PLL used as system clock
.EQU  RCC_CFGR_SWS_N, 2          @ Bits 3:2 SWS[1:0]: System clock switch status
                                 @ These bits are set and cleared by hardware to indicate which clock source is used as
                                 @ system clock.
.EQU  RCC_CFGR_SWS_MSI, 0         @ 00: MSI oscillator used as system clock
.EQU  RCC_CFGR_SWS_HSI, 1 << 2    @ 01: HSI oscillator used as system clock
.EQU  RCC_CFGR_SWS_HSE, 2 << 2    @ 10: HSE oscillator used as system clock
.EQU  RCC_CFGR_SWS_PLL, 3 << 2    @ 11: PLL used as system clock
.EQU  RCC_CFGR_HPRE_N, 4         @ Bits 7:4 HPRE[3:0]: AHB prescaler
                                 @ These bits are set and cleared by software to control the division factor of the AHB clock.
                        @ Caution: Depending on the device voltage range, the software has to set correctly these bits
                                 @ to ensure that the system frequency does not exceed the maximum allowed
                                 @ frequency (for more details refer to the Dynamic voltage scaling management
                                 @ section in the PWR chapter.) After a write operation to these bits and before
                                 @ decreasing the voltage range, this register must be read to be sure that the new
                                 @ value has been taken into account.
.EQU  RCC_CFGR_HPRE_DIV1,0       @ 0xxx: SYSCLK not divided
.EQU  RCC_CFGR_HPRE_DIV2, 8 << 4    @ 1000: SYSCLK divided by 2
.EQU  RCC_CFGR_HPRE_DIV4, 9 << 4    @ 1001: SYSCLK divided by 4
.EQU  RCC_CFGR_HPRE_DIV8, 10 << 4   @ 1010: SYSCLK divided by 8
.EQU  RCC_CFGR_HPRE_DIV16, 11 << 4  @ 1011: SYSCLK divided by 16
.EQU  RCC_CFGR_HPRE_DIV64, 12 << 4  @ 1100: SYSCLK divided by 64
.EQU  RCC_CFGR_HPRE_DIV128, 13 << 4    @ 1101: SYSCLK divided by 128
.EQU  RCC_CFGR_HPRE_DIV256, 14 << 4    @ 1110: SYSCLK divided by 256
.EQU  RCC_CFGR_HPRE_DIV512, 15 << 4    @ 1111: SYSCLK divided by 512
.EQU  RCC_CFGR_PPRE1_N, 8        @ Bits 10:8 PPRE1[2:0]: APB low-speed prescaler (APB1)
                                 @ These bits are set and cleared by software to control the division factor of the APB low-
                                 @ speed clock (PCLK1).
.EQU  RCC_CFGR_PPRE1_DIV1, 0     @ 0xx: HCLK not divided
.EQU  RCC_CFGR_PPRE1_DIV2, 4<<8  @ 100: HCLK divided by 2
.EQU  RCC_CFGR_PPRE1_DIV4, 5<<8  @ 101: HCLK divided by 4
.EQU  RCC_CFGR_PPRE1_DIV8, 6<<8  @ 110: HCLK divided by 8
.EQU  RCC_CFGR_PPRE1_DIV16, 7<<8 @ 111: HCLK divided by 16
.EQU  RCC_CFGR_PPRE2_N, 11       @ Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)
                                 @ These bits are set and cleared by software to control the division factor of the APB high-
                                 @ speed clock (PCLK2).
.EQU  RCC_CFGR_PPRE2_DIV1, 0     @ 0xx: HCLK not divided
.EQU  RCC_CFGR_PPRE2_DIV1, 4<<11 @ 100: HCLK divided by 2
.EQU  RCC_CFGR_PPRE2_DIV4, 5<<11 @ 101: HCLK divided by 4
.EQU  RCC_CFGR_PPRE2_DIV8, 6<<11 @ 110: HCLK divided by 8
.EQU  RCC_CFGR_PPRE2_DIV16, 7<<11 @ 111: HCLK divided by 16
.EQU  RCC_CFGR_PLLSRC_N, 16      @ Bit 16 PLLSRC: PLL entry clock source
                                 @ This bit is set and cleared by software to select PLL clock source. This bit can be written
                                 @ only when PLL is disabled.
                                 @ 0: HSI oscillator clock selected as PLL input clock
.EQU  RCC_CFGR_PLLSRC_HSE, 1<<16 @ 1: HSE oscillator clock selected as PLL input clock
                           @ Note: The PLL minimum input clock frequency is 2 MHz.
.EQU  RCC_CFGR_PLLMUL_N, 18      @ Bits 21:18 PLLMUL[3:0]: PLL multiplication factor
                                 @ These bits are written by software to define the PLL multiplication factor to generate the PLL
                                 @ VCO clock. These bits can be written only when the PLL is disabled.
.EQU  RCC_CFGR_PLLMUL_3, 0       @ 0000: PLLVCO = PLL clock entry x 3
.EQU  RCC_CFGR_PLLMUL_4, 1<<18   @ 0001: PLLVCO = PLL clock entry x 4
.EQU  RCC_CFGR_PLLMUL_6, 2<<18   @ 0010: PLLVCO = PLL clock entry x 6
.EQU  RCC_CFGR_PLLMUL_8, 3<<18   @ 0011: PLLVCO = PLL clock entry x 8
.EQU  RCC_CFGR_PLLMUL_12, 4<<18  @ 0100: PLLVCO = PLL clock entry x 12
.EQU  RCC_CFGR_PLLMUL_16, 5<<18  @ 0101: PLLVCO = PLL clock entry x 16
.EQU  RCC_CFGR_PLLMUL_24, 6<<18  @ 0110: PLLVCO = PLL clock entry x 24
.EQU  RCC_CFGR_PLLMUL_32, 7<<18  @ 0111: PLLVCO = PLL clock entry x 32
.EQU  RCC_CFGR_PLLMUL_48, 8<<18  @ 1000: PLLVCO = PLL clock entry x 48
                                 @ others: not allowed
                                 @ Caution: The PLL VCO clock frequency must not exceed 96 MHz when the product is in
                                 @ Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
                                 @ in Range 3.
.EQU  RCC_CFGR_PLLDIV_N, 22      @ Bits 23:22 PLLDIV[1:0]: PLL output division
                                 @ These bits are set and cleared by software to control PLL output clock division from PLL
                                 @ VCO clock. These bits can be written only when the PLL is disabled.
                                 @ 00: not allowed
.EQU  RCC_CFGR_PLLDIV_2, 1<<22   @ 01: PLL clock output = PLLVCO / 2
.EQU  RCC_CFGR_PLLDIV_3, 2<<22   @ 10: PLL clock output = PLLVCO / 3
.EQU  RCC_CFGR_PLLDIV_4, 3<<22   @ 11: PLL clock output = PLLVCO / 4
.EQU  RCC_CFGR_MCOSEL_N, 24      @ Bits 26:24 MCOSEL[2:0]: Microcontroller clock output selection
                                 @ These bits are set and cleared by software.
.EQU  RCC_CFGR_MCOSEL_DIS, 0     @ 000: MCO output disabled, no clock on MCO
.EQU  RCC_CFGR_MCOSEL_SYSCLK, 1 << 24    @ 001: SYSCLK clock selected
.EQU  RCC_CFGR_MCOSEL_HSI, 2 << 24    @ 010: HSI oscillator clock selected
.EQU  RCC_CFGR_MCOSEL_MSI, 3 << 24    @ 011: MSI oscillator clock selected
.EQU  RCC_CFGR_MCOSEL_HSE, 4 << 24    @ 100: HSE oscillator clock selected
.EQU  RCC_CFGR_MCOSEL_PLL, 5 << 24    @ 101: PLL clock selected
.EQU  RCC_CFGR_MCOSEL_LSI, 6 << 24    @ 110: LSI oscillator clock selected
.EQU  RCC_CFGR_MCOSEL_LSE, 7 << 24    @ 111:LSE oscillator clock selected
                           @ Note: This clock output may have some truncated cycles at startup or during MCO clock
                                 @ source switching.
.EQU  RCC_CFGR_MCOPRE_N, 28      @ Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
                                 @ These bits are set and cleared by software.
                                 @ It is highly recommended to change this prescaler before MCO output is enabled.
.EQU  RCC_CFGR_MCOPRE_DIV1, 0    @ 000: MCO is divided by 1
.EQU  RCC_CFGR_MCOPRE_DIV2, 1 << 28    @ 001: MCO is divided by 2
.EQU  RCC_CFGR_MCOPRE_DIV4, 2 << 28    @ 010: MCO is divided by 4
.EQU  RCC_CFGR_MCOPRE_DIV8, 3 << 28    @ 011: MCO is divided by 8
.EQU  RCC_CFGR_MCOPRE_DIV16, 4 << 28   @ 100: MCO is divided by 16
                          @ Others: not allowed
@.END

@.ITEM     RCC_CIR
.EQU  RCC_CIR_LSIRDYF_N, 0       @ Bit 0 LSIRDYF: LSI ready interrupt flag
                                 @ This bit is set by hardware when the LSI becomes stable and LSIRDYDIE is set.
                                 @ It is cleared by software setting the LSIRDYC bit.
                                 @ 0: No clock ready interrupt caused by the LSI
.EQU  RCC_CIR_LSIRDYF, 1         @ 1: Clock ready interrupt caused by the LSI
.EQU  RCC_CIR_LSERDYF_N, 1       @ Bit 1 LSERDYF: LSE ready interrupt flag
                                 @ This bit is set by hardware when the LSE becomes stable and LSERDYDIE is set.
                                 @ It is cleared by software setting the LSERDYC bit.
                                 @ 0: No clock ready interrupt caused by the LSE
.EQU  RCC_CIR_LSERDYF, 1 << 1    @ 1: Clock ready interrupt caused by the LSE
.EQU  RCC_CIR_HSIRDYF_N, 2       @ Bit 2 HSIRDYF: HSI ready interrupt flag
                                 @ This bit is set by hardware when the HSI becomes stable and HSIRDYDIE is set.
                                 @ It is cleared by software setting the HSIRDYC bit.
                                 @ 0: No clock ready interrupt caused by the HSI
.EQU  RCC_CIR_HSIRDYF, 1 << 2    @ 1: Clock ready interrupt caused by the HSI
.EQU  RCC_CIR_HSERDYF_N, 3       @ Bit3 HSERDYF: HSE ready interrupt flag
                                 @ This bit is set by hardware when HSE becomes stable and HSERDYDIE is set.
                                 @ It is cleared by software setting the HSERDYC bit.
                                 @ 0: No clock ready interrupt caused by the HSE
.EQU  RCC_CIR_HSERDYF, 1<<3      @ 1: Clock ready interrupt caused by the HSE
.EQU  RCC_CIR_PLLRDYF_N, 4       @ Bit 4 PLLRDYF: PLL ready interrupt flag
                                 @ This bit is set by hardware when the PLL locks and PLLRDYDIE is set.
                                 @ It is cleared by software setting the PLLRDYC bit.
                                 @ 0: No clock ready interrupt caused by PLL lock
.EQU  RCC_CIR_PLLRDYF, 1<<4      @ 1: Clock ready interrupt caused by PLL lock
.EQU  RCC_CIR_MSIRDYF_N, 5       @ Bit 5 MSIRDYF: MSI ready interrupt flag
                                 @ This bit is set by hardware when the MSI becomes stable and MSIRDYDIE is set.
                                 @ It is cleared by software setting the MSIRDYC bit.
                                 @ 0: No clock ready interrupt caused by the MSI
.EQU  RCC_CIR_MSIRDYF, 1 << 5    @ 1: Clock ready interrupt caused by the MSI
.EQU  RCC_CIR_LSECSSF_N, 6       @ Bit 6 LSECSSF LSE CSS Interrupt flag
                                 @ Reset by software by writing to the LSECSSC bit. Set by hardware when a failure is detected
                                 @ on the external 32 KHz oscillator and the LSECSSIE bit is set.
                                 @ 0: No failure detected on the external 32 KHz oscillator (LSE)
.EQU  RCC_CIR_LSECSSF, 1 << 6    @ 1: A failure is detected on the external 32 kHz oscillator (LSE)
                           @ Note: This bit is available in Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_CIR_CSSF_N, 7          @ Bit 7 CSSF: Clock security system interrupt flag
                                 @ This bit is set by hardware when a failure is detected in the HSE oscillator.
                                 @ It is cleared by software by setting the CSSC bit.
                                 @ 0: No clock security interrupt caused by HSE clock failure
.EQU  RCC_CIR_CSSF  , 1 << 7     @ 1: Clock security interrupt caused by HSE clock failure
.EQU  RCC_CIR_LSIRDYIE_N, 8      @ Bit 8 LSIRDYIE: LSI ready interrupt enable
                                 @ This bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator
                                 @ stabilization.
                                 @ 0: LSI ready interrupt disabled
.EQU  RCC_CIR_LSIRDYIE, 1 << 8   @ 1: LSI ready interrupt enabled
.EQU  RCC_CIR_LSERDYIE_N, 9      @ Bit 9 LSERDYIE: LSE ready interrupt enable
                                 @ This bit is set and cleared by software to enable/disable interrupt caused by the LSE
                                 @ oscillator stabilization.
                                 @ 0: LSE ready interrupt disabled
.EQU  RCC_CIR_LSERDYIE, 1 << 9   @ 1: LSE ready interrupt enabled
.EQU  RCC_CIR_HSIRDYIE_N, 10     @ Bit 10 HSIRDYIE: HSI ready interrupt enable
                                 @ This bit is set and cleared by software to enable/disable interrupt caused by the HSI
                                 @ oscillator stabilization.
                                 @ 0: HSI ready interrupt disabled
.EQU  RCC_CIR_HSIRDYIE, 1 << 10  @ 1: HSI ready interrupt enabled
.EQU  RCC_CIR_HSERDYIE_N, 11     @ Bit 11 HSERDYIE: HSE ready interrupt enable
                                 @ This bit is set and cleared by software to enable/disable interrupt caused by the HSE
                                 @ oscillator stabilization.
                                 @ 0: HSE ready interrupt disabled
.EQU  RCC_CIR_HSERDYIE, 1 << 11  @ 1: HSE ready interrupt enabled
.EQU  RCC_CIR_PLLRDYIE_N, 12     @ Bit 12 PLLRDYIE: PLL ready interrupt enable
                                 @ This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.
                                 @ 0: PLL lock interrupt disabled
.EQU  RCC_CIR_PLLRDYIE, 1<<12    @ 1: PLL lock interrupt enabled
.EQU  RCC_CIR_MSIRDYIE_N, 13     @ Bit 13 MSIRDYIE: MSI ready interrupt enable
                                 @ This bit is set and cleared by software to enable/disable interrupt caused by the MSI
                                 @ oscillator stabilization.
                                 @ 0: MSI ready interrupt disabled
.EQU  RCC_CIR_MSIRDYIE, 1 << 13  @ 1: MSI ready interrupt enabled
.EQU  RCC_CIR_LSECSSIE_N, 14     @ Bit 14 LSECSSIE: LSE CSS interrupt enable
                                 @ Set and reset by software to enable/disable interrupts from the Clock Security System on
                                 @ external 32 kHz oscillator (LSE).
                                 @ 0: LSE CSS interrupt disabled
.EQU  RCC_CIR_LSECSSIE, 1 << 14  @ 1: LSE CSS interrupt enabled
                           @ Note: This bit is available in Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_CIR_LSIRDYC_N, 16      @ Bit 16 LSIRDYC: LSI ready interrupt clear
                                 @ This bit is set by software to clear the LSIRDYF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_LSIRDYC, 1 << 16   @ 1: LSIRDYF cleared
.EQU  RCC_CIR_LSERDYC_N, 17      @ Bit 17 LSERDYC: LSE ready interrupt clear
                                 @ This bit is set by software to clear the LSERDYF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_LSERDYC, 1 << 17   @ 1: LSERDYF cleared
.EQU  RCC_CIR_HSIRDYC_N, 18      @ Bit 18 HSIRDYC: HSI ready interrupt clear
                                 @ This bit is set software to clear the HSIRDYF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_HSIRDYC, 1 << 18   @ 1: HSIRDYF cleared
.EQU  RCC_CIR_HSERDYC_N, 19      @ Bit 19 HSERDYC: HSE ready interrupt clear
                                 @ This bit is set by software to clear the HSERDYF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_HSERDYC, 1<<19     @ 1: HSERDYF cleared
.EQU  RCC_CIR_PLLRDYC_N, 20      @ Bit 20 PLLRDYC: PLL ready interrupt clear
                                 @ This bit is set by software to clear the PLLRDYF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_PLLRDYC, 1<<20     @ 1: PLLRDYF cleared
.EQU  RCC_CIR_MSIRDYC_N, 21      @ Bit 21 MSIRDYC: MSI ready interrupt clear
                                 @ This bit is set by software to clear the MSIRDYF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_MSIRDYC, 1 << 21   @ 1: MSIRDYF cleared
.EQU  RCC_CIR_LSECSSC_N, 22      @ Bit 22 LSECSSC: LSE CSS interrupt clear
                                 @ Set by software to clear LSECSSF. Reset by hardware when clear done.
                                 @ 0: LSECSSF not cleared
.EQU  RCC_CIR_LSECSSC, 1 << 22   @ 1: LSECSSF cleared
                           @ Note: This bit is available in Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_CIR_CSSC_N, 23         @ Bit 2 3 CSSC: Clock security system interrupt clear
                                 @ This bit is set by software to clear the CSSF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_CSSC  , 1 << 23    @ 1: Clear CSSF flag
@.END

@.ITEM     RCC_AHBRSTR
.EQU  RCC_AHBRSTR_GPIOARST_N, 0  @ Bit 0 GPIOARST: IO port A reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOARST, 1    @ 1: Reset IO port A
.EQU  RCC_AHBRSTR_GPIOBRST_N, 1  @ Bit 1 GPIOBRST: IO port B reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOBRST, 1<<1 @ 1: Reset IO port B
.EQU  RCC_AHBRSTR_GPIOCRST_N, 2  @ Bit 2 GPIOCRST: IO port C reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOCRST, 1 << 2    @ 1: Reset IO port C
.EQU  RCC_AHBRSTR_GPIODRST_N, 3  @ Bit 3 GPIODRST: IO port D reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIODRST, 1 << 3    @ 1: Reset IO port D
.EQU  RCC_AHBRSTR_GPIOERST_N, 4  @ Bit 4 GPIOERST: IO port E reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOERST, 1 << 4    @ 1: Reset IO port E
.EQU  RCC_AHBRSTR_GPIOHRST_N, 5  @ Bit 5 GPIOHRST: IO port H reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOHRST, 1 << 5    @ 1: Reset
.EQU  RCC_AHBRSTR_GPIOFRST_N, 6  @ Bit 6 GPIOFRST: IO port F reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOFRST, 1 << 6    @ 1: Reset IO port F
                                  @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBRSTR_GPIOGRST_N, 7  @ Bit 7 GPIOGRST: IO port G reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_GPIOGRST, 1 << 7    @ 1: Reset IO port G
                            @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBRSTR_CRCRST_N, 12   @  Bit 12 CRCRST: CRC reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_CRCRST, 1 << 12    @ 1: Reset CRC
.EQU  RCC_AHBRSTR_FLITFRST_N, 15 @ Bit 15 FLITFRST: FLITF reset
                                  @ This bit is set and cleared by software. The FLITF reset can be enabled only when the Flash
                                  @ memory is in power down mode.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_FLITFRST, 1 << 15    @ 1: Reset FLITF
.EQU  RCC_AHBRSTR_DMA1RST_N, 24  @ Bit 24 DMA1RST: DMA1 reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_DMA1RST, 1 << 24    @ 1: Reset DMA1
.EQU  RCC_AHBRSTR_DMA2RST_N, 25  @ Bit 25 DMA1RST: DMA2 reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_DMA2RST, 1 << 25    @ 1: Reset DMA2
.EQU  RCC_AHBRSTR_AESRST_N, 27   @ Bit 27 AESRST: AES reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
.EQU  RCC_AHBRSTR_AESRST, 1 << 27    @ 1: Reset AES
                            @ Note: This bit is available in STM32L16x devices only.
.EQU  RCC_AHBRSTR_FSMCRST_N, 30  @ Bit 30 FSMCRST: FSMC reset
                                  @ This bit is set and cleared by software.
                                  @ 0: No effect
                                  @ 1: Reset FSMC
                                  @ Note: This bit is available in Cat.4 devices only.
@.END

@.ITEM     RCC_APB2RSTR
.EQU  RCC_APB2RSTR_SYSCFGRST_N, 0    @ Bit 0 SYSCFGRST: System configuration controller reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_SYSCFGRST, 1      @ 1: Reset System configuration controller
.EQU  RCC_APB2RSTR_TIM9RST_N, 2      @ Bit 2 TIM9RST: TIM9 timer reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_TIM9RST, 1 << 2   @ 1: Reset TIM9 timer
.EQU  RCC_APB2RSTR_TIM10RST_N, 3     @ Bit 3 TIM10RST: TIM10 timer reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_TIM10RST, 1 << 3  @ 1: Reset TIM10 timer
.EQU  RCC_APB2RSTR_TIM11RST_N, 4     @ Bit 4 TIM11RST: TIM11 timer reset
                                     @ Set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_TIM11RST, 1 << 4  @ 1: Reset TIM11 timer
.EQU  RCC_APB2RSTR_ADC1RST_N, 9      @ Bit 9 ADC1RST: ADC1 interface reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_ADC1RST, 1 << 9   @ 1: Reset ADC1 interface
.EQU  RCC_APB2RSTR_SDIORST_N, 11     @ Bit 11 SDIORST: SDIO reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_SDIORST, 1 << 11  @ 1: Reset SDIO
                               @ Note: This bit is available in Cat.4 devices only.
.EQU  RCC_APB2RSTR_SPI1RST_N, 12     @ Bit 12 SPI1RST: SPI 1 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_SPI1RST, 1 << 12  @ 1: Reset SPI 1
.EQU  RCC_APB2RSTR_USART1RST_N, 14   @ Bit 14 USART1RST: USART1 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB2RSTR_USART1RST, 1<<14  @ 1: Reset USART1
@.END

@.ITEM     RCC_APB1RSTR
.EQU  RCC_APB1RSTR_TIM2RST_N, 0      @ Bit 0 TIM2RST: Timer 2 reset
                                     @ Set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_TIM2RST, 1        @ 1: Reset timer 2
.EQU  RCC_APB1RSTR_TIM3RST_N, 1      @ Bit 1 TIM3RST: Timer 3 reset
                                     @ Set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_TIM3RST, 1 << 1   @ 1: Reset timer 3
.EQU  RCC_APB1RSTR_TIM4RST_N, 2      @ Bit 2 TIM4RST: Timer 4 reset
                                     @ Set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_TIM4RST, 1 << 2   @ 1: Reset timer 4
.EQU  RCC_APB1RSTR_TIM5RST_N, 3      @ Bit 3 TIM5RST: Timer 5 reset
                                     @ Set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_TIM5RST, 1 << 3   @ 1: Reset timer 5
                               @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1RSTR_TIM6RST_N, 4      @ Bit 4 TIM6RST: Timer 6reset
                                     @ Set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_TIM6RST, 1<<4     @ 1: Reset timer 6
.EQU  RCC_APB1RSTR_TIM7RST_N, 5      @ Bit 5 TIM7RST: Timer 7 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_TIM7RST, 1 << 5   @ 1: Reset timer 7
.EQU  RCC_APB1RSTR_LCDRST_N, 9       @ Bit 9 LCDRST: LCD reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_LCDRST, 1<<9      @ 1: Reset LCD
.EQU  RCC_APB1RSTR_WWDGRST_N, 11     @ Bit 11 WWDGRST: Window watchdog reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_WWDGRST, 1 << 11  @ 1: Reset window watchdog
.EQU  RCC_APB1RSTR_SPI2RST_N, 14     @ Bit 14 SPI2RST: SPI 2 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_SPI2RST, 1<<14    @ 1: Reset SPI 2
.EQU  RCC_APB1RSTR_SPI3RST_N, 15     @ Bit 15 SPI3RST: SPI 3 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_SPI3RST, 1<<15    @ 1: Reset SPI 3
                               @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only
.EQU  RCC_APB1RSTR_USART2RST_N, 17   @ Bit 17 USART2RST: USART 2 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_USART2RST, 1<<17  @ 1: Reset USART 2
.EQU  RCC_APB1RSTR_USART3RST_N, 18   @ Bit 18 USART3RST: USART 3 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_USART3RST, 1<<18  @ 1: Reset USART 3
.EQU  RCC_APB1RSTR_UART4RST_N, 19    @ Bit 19 UART4RST: UART 4 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_UART4RST, 1<<19   @ 1: Reset UART 4
                               @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1RSTR_UART5RST_N, 20    @ Bit 20 UART5RST: UART 5 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_UART5RST, 1<<20   @ 1: Reset UART 5
                               @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1RSTR_I2C1RST_N, 21     @ Bit 21 I2C1RST: I2C 1 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_I2C1RST, 1<<21    @ 1: Reset I2C 1
.EQU  RCC_APB1RSTR_I2C2RST_N, 22     @ Bit 22  I2C2RST: I2C 2 reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_I2C2RST, 1 << 22  @ 1: Reset I2C 2
.EQU  RCC_APB1RSTR_USBRST_N, 23      @ Bit 23 USBRST: USB reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_USBRST, 1 << 23   @ 1: Reset USB
.EQU  RCC_APB1RSTR_PWRRST_N, 28      @ Bit 28 PWRRST: Power interface reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_PWRRST, 1<<28     @ 1: Reset power interface
.EQU  RCC_APB1RSTR_DACRST_N, 29      @ Bit 29 DACRST: DAC interface reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_DACRST, 1<<29     @ 1: Reset DAC interface
.EQU  RCC_APB1RSTR_COMPRST_N, 31     @ Bit 31 COMPRST: COMP interface reset
                                     @ This bit is set and cleared by software.
                                     @ 0: No effect
.EQU  RCC_APB1RSTR_COMPRST, 1 << 31  @ 1: Reset COMP interface
@.END



@.ITEM     RCC_AHBENR
.EQU  RCC_AHBENR_GPIOAEN_N, 0     @ Bit 0 GPIOAEN: IO port A clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port A clock disabled
.EQU  RCC_AHBENR_GPIOAEN, 1       @ 1: IO port A clock enabled
.EQU  RCC_AHBENR_GPIOBEN_N, 1     @ Bit 1 GPIOBEN: IO port B clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port B clock disabled
.EQU  RCC_AHBENR_GPIOBEN, 1<<1    @ 1: IO port B clock enabled
.EQU  RCC_AHBENR_GPIOCEN_N, 2     @ Bit 2 GPIOCEN: IO port C clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port C clock disabled
.EQU  RCC_AHBENR_GPIOCEN, 1 << 2  @ 1: IO port C clock enabled
.EQU  RCC_AHBENR_GPIODEN_N, 3     @ Bit 3 GPIODEN: IO port D clock enable
                                  @ Set and cleared by software.
                                  @ 0: IO port D clock disabled
.EQU  RCC_AHBENR_GPIODEN, 1 << 3  @ 1: IO port D clock enabled
.EQU  RCC_AHBENR_GPIOEEN_N, 4     @ Bit 4 GPIOEEN: IO port E clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port E clock disabled
.EQU  RCC_AHBENR_GPIOEEN, 1 << 4  @ 1: IO port E clock enabled
.EQU  RCC_AHBENR_GPIOHEN_N, 5     @ Bit 5 GPIOHEN: IO port H clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port H clock disabled
.EQU  RCC_AHBENR_GPIOHEN, 1 << 5  @ 1: IO port H clock enabled
.EQU  RCC_AHBENR_GPIOFEN_N, 6     @ Bit 6 GPIOFEN: IO port F clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port F clock disabled
.EQU  RCC_AHBENR_GPIOFEN, 1 << 6  @ 1: IO port F clock enabled
                            @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBENR_GPIOGEN_N, 7     @ Bit 7 GPIOGEN: IO port G clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: IO port G clock disabled
.EQU  RCC_AHBENR_GPIOGEN, 1 << 7  @ 1: IO port G clock enabled
                            @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBENR_CRCEN_N, 12      @ Bit 12 CRCEN: CRC clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: CRC clock disabled
.EQU  RCC_AHBENR_CRCEN, 1 << 12   @ 1: CRC clock enabled
.EQU  RCC_AHBENR_FLITFEN_N, 15    @ Bit 15 FLITFEN: FLITF clock enable
                                  @ This bit can be written only when the Flash memory is in power down mode.
                                  @ 0: FLITF clock disabled
.EQU  RCC_AHBENR_FLITFEN, 1 << 15 @ 1: FLITF clock enabled
.EQU  RCC_AHBENR_DMA1EN_N, 24     @ Bit 24 DMA1EN: DMA1 clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: DMA1 clock disabled
.EQU  RCC_AHBENR_DMA1EN, 1 << 24  @ 1: DMA1 clock enabled
.EQU  RCC_AHBENR_DMA2EN_N, 25     @ Bit 25 DMA2EN: DMA2 clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: DMA2 clock disabled
.EQU  RCC_AHBENR_DMA2EN, 1 << 25  @ 1: DMA2 clock enabled
                            @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBENR_AESEN_N, 27      @ Bit 27 AESEN: AES clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: AES clock disabled
.EQU  RCC_AHBENR_AESEN, 1 << 27   @ 1: AES clock enabled
                            @ Note: This bit is available in STM32L16x devices only.
.EQU  RCC_AHBENR_FSMCEN_N, 30     @ Bit 30 FSMCEN: FSMC clock enable
                                  @ This bit is set and cleared by software.
                                  @ 0: FSMC clock disabled
.EQU  RCC_AHBENR_FSMCEN, 1<<30    @ 1: FSMC clock enabled
                            @ Note: This bit is available in Cat.4 devices only.
@.END

@.ITEM     RCC_APB2ENR
.EQU  RCC_APB2ENR_SYSCFGEN_N, 0    @ Bit 0 SYSCFGEN: System configuration controller clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: System configuration controller clock disabled
.EQU  RCC_APB2ENR_SYSCFGEN, 1      @ 1: System configuration controller clock enabled
.EQU  RCC_APB2ENR_TIM9EN_N, 2      @ Bit 2 TIM9EN: TIM9 timer clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: TIM9 timer clock disabled
.EQU  RCC_APB2ENR_TIM9EN, 1 << 2   @ 1: TIM9 timer clock enabled
.EQU  RCC_APB2ENR_TIM10EN_N, 3     @ Bit 3 TIM10EN: TIM10 timer clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: TIM10 timer clock disabled
.EQU  RCC_APB2ENR_TIM10EN, 1 << 3  @ 1: TIM10 timer clock enabled
.EQU  RCC_APB2ENR_TIM11EN_N, 4     @ Bit 4 TIM11EN: TIM11 timer clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: TIM11 timer clock disabled
.EQU  RCC_APB2ENR_TIM11EN, 1 << 4  @ 1: TIM11 timer clock enabled
.EQU  RCC_APB2ENR_ADC1EN_N, 9      @ Bit 9 ADC1EN: ADC1 interface clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: ADC1 interface disabled
.EQU  RCC_APB2ENR_ADC1EN, 1 << 9   @ 1: ADC1 interface clock enabled
.EQU  RCC_APB2ENR_SDIOEN_N, 11     @ Bit 11 SDIOEN: SDIO clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: SDIO clock disabled
.EQU  RCC_APB2ENR_SDIOEN, 1 << 11  @ 1: SDIO clock enabled
                             @ Note: This bit is available in Cat.4 devices only.
.EQU  RCC_APB2ENR_SPI1EN_N, 12     @ Bit 12 SPI1EN: SPI 1 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: SPI 1 clock disabled
.EQU  RCC_APB2ENR_SPI1EN, 1 << 12  @ 1: SPI 1 clock enabled
.EQU  RCC_APB2ENR_USART1EN_N, 14   @ Bit 14 USART1EN: USART1 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: USART1 clock disabled
.EQU  RCC_APB2ENR_USART1EN, 1<<14  @ 1: USART1 clock enabled
@.END


@.ITEM     RCC_APB1ENR
.EQU  RCC_APB1ENR_TIM2EN_N, 0      @ Bit 0 TIM2EN: Timer 2 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 2 clock disabled
.EQU  RCC_APB1ENR_TIM2EN, 1        @ 1: Timer 2 clock enabled
.EQU  RCC_APB1ENR_TIM3EN_N, 1      @ Bit 1 TIM3EN: Timer 3 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 3 clock disabled
.EQU  RCC_APB1ENR_TIM3EN, 1 << 1   @ 1: Timer 3 clock enabled
.EQU  RCC_APB1ENR_TIM4EN_N, 2      @ Bit 2 TIM4EN: Timer 4 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 4 clock disabled
.EQU  RCC_APB1ENR_TIM4EN, 1 << 2   @ 1: Timer 4 clock enabled
.EQU  RCC_APB1ENR_TIM5EN_N, 3      @ Bit 3 TIM5EN: Timer 5 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 5 clock disabled
.EQU  RCC_APB1ENR_TIM5EN, 1 << 3   @ 1: Timer 5 clock enabled
                             @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1ENR_TIM6EN_N, 4      @ Bit 4 TIM6EN: Timer 6 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 6 clock disabled
.EQU  RCC_APB1ENR_TIM6EN, 1<<4     @ 1: Timer 6 clock enabled
.EQU  RCC_APB1ENR_TIM7EN_N, 5      @ Bit 5 TIM7EN: Timer 7 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 7 clock disabled
.EQU  RCC_APB1ENR_TIM7EN, 1 << 5   @ 1: Timer 7 clock enabled
.EQU  RCC_APB1ENR_LCDEN_N, 9       @ Bit 9 LCDEN: LCD clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: LCD clock disabled
.EQU  RCC_APB1ENR_LCDEN, 1<<9      @ 1: LCD clock enabled
.EQU  RCC_APB1ENR_WWDGEN_N, 11     @ Bit 11 WWDGEN: Window watchdog clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Window watchdog clock disabled
.EQU  RCC_APB1ENR_WWDGEN, 1 << 11  @ 1: Window watchdog clock enabled
.EQU  RCC_APB1ENR_SPI2EN_N, 14     @ Bit 14 SPI2EN: SPI 2 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: SPI 2 clock disabled
.EQU  RCC_APB1ENR_SPI2EN, 1<<14    @ 1: SPI 2 clock enabled
.EQU  RCC_APB1ENR_SPI3EN_N, 15     @ Bit 15 SPI3EN: SPI 3 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: SPI 3 clock disabled
.EQU  RCC_APB1ENR_SPI3EN, 1<<15    @ 1: SPI 3 clock enabled
                             @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only
.EQU  RCC_APB1ENR_USART2EN_N, 17   @ Bit 17 USART2EN: USART 2 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: USART 2 clock disabled
.EQU  RCC_APB1ENR_USART2EN, 1<<17  @ 1: USART 2 clock enabled
.EQU  RCC_APB1ENR_USART3EN_N, 18   @ Bit 18 USART3EN: USART 3 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: USART 3 clock disabled
.EQU  RCC_APB1ENR_USART3EN, 1<<18  @ 1: USART 3 clock enabled
.EQU  RCC_APB1ENR_UART4EN_N, 19    @ Bit 19 UART4EN: UART 4 clock enable
                                   @ This bit is set and cleared by software.
                             @ Note: 0: UART 4 clock disabled
.EQU  RCC_APB1ENR_UART4EN, 1<<19   @ 1: UART 4 clock enabled
                                   @ This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1ENR_UART5EN_N, 20    @ Bit 20 UART5EN: UART 5 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: UART 5 clock disabled
.EQU  RCC_APB1ENR_UART5EN, 1<<20   @ 1: UART 5 clock enabled
                                   @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1ENR_I2C1EN_N, 21     @ Bit 21 I2C1EN: I2C 1 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: I2C 1 clock disabled
.EQU  RCC_APB1ENR_I2C1EN, 1<<21    @ 1: I2C 1 clock enabled
.EQU  RCC_APB1ENR_I2C2EN_N, 22     @ Bit 22 I2C2EN: I2C 2 clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: I2C 2 clock disabled
.EQU  RCC_APB1ENR_I2C2EN, 1 << 22  @ 1: I2C 2 clock enabled
.EQU  RCC_APB1ENR_USBEN_N, 23      @ Bit 23 USBEN: USB clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: USB clock disabled
.EQU  RCC_APB1ENR_USBEN, 1 << 23   @ 1: USB clock enabled
.EQU  RCC_APB1ENR_PWREN_N, 28      @ Bit 28 PWREN: Power interface clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: Power interface clock disabled
.EQU  RCC_APB1ENR_PWREN, 1<<28     @ 1: Power interface clock enable
.EQU  RCC_APB1ENR_DACEN_N, 29      @ Bit 29 DACEN: DAC interface clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: DAC interface clock disabled
.EQU  RCC_APB1ENR_DACEN, 1<<29     @ 1: DAC interface clock enable
.EQU  RCC_APB1ENR_COMPEN_N, 31     @ Bit 31 COMPEN: COMP interface clock enable
                                   @ This bit is set and cleared by software.
                                   @ 0: COMP interface clock disabled
.EQU  RCC_APB1ENR_COMPEN, 1 << 31  @ 1: COMP interface clock enable
@.END


@.ITEM     RCC_AHBLPENR
.EQU  RCC_AHBLPENR_GPIOALPEN_N, 0   @ Bit 0 GPIOALPEN: IO port A clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port A clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOALPEN, 1     @ 1: IO port A clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOBLPEN_N, 1   @ Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port B clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOBLPEN, 1<<1  @ 1: IO port B clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOCLPEN_N, 2   @ Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port C clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOCLPEN, 1 << 2  @ 1: IO port C clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIODLPEN_N, 3   @ Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port D clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIODLPEN, 1 << 3 @ 1: IO port D clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOELPEN_N, 4   @ Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port E clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOELPEN, 1 << 4 @ 1: IO port E clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOHLPEN_N, 5   @ Bit 5 GPIOHLPEN: IO port H clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port H clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOHLPEN, 1 << 5 @ 1: IO port H clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOFLPEN_N, 6   @ Bit 6 GPIOFLPEN: IO port F clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port F clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOFLPEN, 1 << 6 @ 1: IO port F clock enabled during Sleep mode
                              @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only
.EQU  RCC_AHBLPENR_GPIOGLPEN_N, 7   @ Bit 7 GPIOGLPEN: IO port G clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: IO port G clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_GPIOGLPEN, 1 << 7 @ 1: IO port G clock enabled during Sleep mode
                              @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBLPENR_CRCLPEN_N, 12    @ Bit 12 CRCLPEN: CRC clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: CRC clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_CRCLPEN, 1 << 12 @ 1: CRC clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_FLITFLPEN_N, 15  @ Bit 15 FLITFLPEN: FLITF clock enable during Sleep mode
                                    @ This bit can be written only when the Flash memory is in power down mode.
                                    @ 0: FLITF clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_FLITFLPEN, 1 << 15 @ 1: FLITF clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_SRAMLPEN_N, 16   @ Bit 16 SRAMLPEN: SRAM clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: SRAM clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_SRAMLPEN, 1<<16  @ 1: SRAM clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_DMA1LPEN_N, 24   @ Bit 24 DMA1LPEN: DMA1 clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: DMA1 clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_DMA1LPEN, 1 << 24 @ 1: DMA1 clock enabled during Sleep mode
.EQU  RCC_AHBLPENR_DMA2LPEN_N, 25   @ Bit 25 DMA2LPEN: DMA2 clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: DMA2 clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_DMA2LPEN, 1 << 25 @ 1: DMA2 clock enabled during Sleep mode
                              @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_AHBLPENR_AESLPEN_N, 27    @ Bit 27 AESLPEN: AES clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: AES clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_AESLPEN, 1 << 27 @ 1: AES clock enabled during Sleep mode
                              @ Note: This bit is available in STM32L16x devices only.
.EQU  RCC_AHBLPENR_FSMCLPEN_N, 30   @ Bit 30 FSMCLPEN: FSMC clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: FSMC clock disabled during Sleep mode
.EQU  RCC_AHBLPENR_FSMCLPEN, 1<<30  @ 1: FSMC clock enabled during Sleep mode
                              @ Note: This bit is available in Cat.4 devices only.
@.END

@.ITEM     RCC_APB2LPENR
.EQU  RCC_APB2LPENR_SYSCFGLPEN_N, 0 @ Bit 0 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: System configuration controller clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SYSCFGLPEN, 1   @ 1: System configuration controller clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM9LPEN_N, 2   @ Bit 2 TIM9LPEN: TIM9 timer clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: TIM9 timer clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM9LPEN, 1 << 2 @ 1: TIM9 timer clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM10LPEN_N, 3  @ Bit 3 TIM10LPEN: TIM10 timer clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: TIM10 timer clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM10LPEN, 1 << 3 @ 1: TIM10 timer clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM11LPEN_N, 4  @ Bit 4 TIM11LPEN: TIM11 timer clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: TIM11 timer clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM11LPEN, 1 << 4 @ 1: TIM11 timer clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_ADC1LPEN_N, 9   @ Bit 9 ADC1LPEN: ADC1 interface clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: ADC1 interface disabled during Sleep mode
.EQU  RCC_APB2LPENR_ADC1LPEN, 1 << 9 @ 1: ADC1 interface clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_SDIOLPEN_N, 11  @ Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: SDIO clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SDIOLPEN, 1 << 11 @ 1: SDIO clock enabled during Sleep mode
                              @ Note: This bit is available in Cat.4 devices only.
.EQU  RCC_APB2LPENR_SPI1LPEN_N, 12  @ Bit 12 SPI1LPEN: SPI 1 clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: SPI 1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SPI1LPEN, 1 << 12 @ 1: SPI 1 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_USART1LPEN_N, 14  @ Bit 14 USART1LPEN: USART1 clock enable during Sleep mode
                                    @ This bit is set and cleared by software.
                                    @ 0: USART1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_USART1LPEN, 1<<14 @ 1: USART1 clock enabled during Sleep mode
@.END


@.ITEM     RCC_APB1LPENR
.EQU  RCC_APB1LPENR_TIM2LPEN_N, 0  @ Bit 0 TIM2LPEN: Timer 2 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM2LPEN, 1    @ 1: Timer 2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM3LPEN_N, 1  @ Bit 1 TIM3LPEN: Timer 3 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 3 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM3LPEN, 1 << 1 @ 1: Timer 3 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM4LPEN_N, 2  @ Bit 2 TIM4LPEN: Timer 4 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 4 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM4LPEN, 1 << 2 @ 1: Timer 4 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM5LPEN_N, 3  @ Bit 3 TIM5LPEN: Timer 5 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 5 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM5LPEN, 1 << 3 @ 1: Timer 5 clock enabled during Sleep mode
                             @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1LPENR_TIM6LPEN_N, 4  @ Bit 4 TIM6LPEN: Timer 6 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 6 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM6LPEN, 1<<4 @ 1: Timer 6 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM7LPEN_N, 5  @ Bit 5 TIM7LPEN: Timer 7 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: Timer 7 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM7LPEN, 1 << 5  @ 1: Timer 7 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_LCDLPEN_N, 9   @ Bit 9 LCDLPEN: LCD clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: LCD clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_LCDLPEN, 1<<9  @ 1: LCD clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_WWDGLPEN_N, 11 @ Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode
@ This bit is set and cleared by software.
@ 0: Window watchdog clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_WWDGLPEN, 1 << 11 @ 1: Window watchdog clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI2LPEN_N, 14 @ Bit 14 SPI2LPEN: SPI 2 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: SPI 2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI2LPEN, 1<<14 @ 1: SPI 2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI3LPEN_N, 15 @ Bit 15 SPI3LPEN: SPI 3 clock enable during Sleep mode
                                   @ This bit is set and cleared by software.
                                   @ 0: SPI 3 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI3LPEN, 1<<15 @ 1: SPI 3 clock enabled during Sleep mode
                             @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1LPENR_USART2LPEN_N, 17 @ Bit 17 USART2LPEN: USART 2 clock enable during Sleep mode
                                     @ This bit is set and cleared by software.
                                     @ 0: USART 2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_USART2LPEN, 1<<17 @ 1: USART 2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_USART3LPEN_N, 18  @ Bit 18 USART3LPEN: USART 3 clock enable during Sleep mode
                                     @ This bit is set and cleared by software.
                                     @ 0: USART 3 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_USART3LPEN, 1<<18 @ 1: USART 3 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_UART4LPEN_N, 19   @ Bit 19 UART4LPEN: USART 4 clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: UART 4 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_UART4LPEN, 1<<19  @ 1: UART 4 clock enabled during Sleep mode
                                @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only
.EQU  RCC_APB1LPENR_UART5LPEN_N, 20   @ Bit 20 UART5LPEN: USART 5 clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: UART 5 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_UART5LPEN, 1<<20  @ 1: UART 5 clock enabled during Sleep mode
                                @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_APB1LPENR_I2C1LPEN_N, 21    @ Bit 21 I2C1LPEN: I2C 1 clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: I2C 1 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C1LPEN, 1<<21   @ 1: I2C 1 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C2LPEN_N, 22    @ Bit 22 I2C2LPEN: I2C 2 clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: I2C 2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C2LPEN, 1 << 22 @ 1: I2C 2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_USBLPEN_N, 23     @ Bit 23 USBLPEN: USB clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: USB clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_USBLPEN, 1 << 23  @ 1: USB clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_PWRLPEN_N, 28     @ Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: Power interface clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_PWRLPEN, 1<<28    @ 1: Power interface clock enable during Sleep mode
.EQU  RCC_APB1LPENR_DACLPEN_N, 29     @ Bit 29 DACLPEN: DAC interface clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: DAC interface clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_DACLPEN, 1<<29    @ 1: DAC interface clock enable during Sleep mode
.EQU  RCC_APB1LPENR_COMPLPEN_N, 31    @ Bit 31 COMPLPEN: COMP interface clock enable during Sleep mode
                                      @ This bit is set and cleared by software.
                                      @ 0: COMP interface clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_COMPLPEN, 1 << 31 @ 1: COMP interface clock enable during Sleep mode
@.END




@.ITEM     RCC_CSR
@ Power-on reset value: 0x0C00 0000,
@ Access: 0   wait state   3, word, half-word and byte access
@ Wait states are inserted in case of successive accesses to this register.
@ Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC control and status register
@ (RCC_CSR) are in the RTC domain. As these bits are write protected after reset, the DBP
@ bit in the Power control register (PWR_CR) has to be set to be able to modify them. Refer to
@ Section RTC and RTC backup registers for further information. These bits are only reset
@ after a RTC domain reset (see RTC and backup registers reset). Any internal or external
@ reset does not have any effect on them.
.EQU  RCC_CSR_LSION_N, 0         @ Bit 0 LSION: Internal low-speed oscillator enable
                                 @ This bit is set and cleared by software.
                                 @ It is reset by system reset.
                                 @ 0: LSI oscillator OFF
.EQU  RCC_CSR_LSION , 1          @ 1: LSI oscillator ON
.EQU  RCC_CSR_LSIRDY_N, 1        @ Bit 1 LSIRDY: Internal low-speed oscillator ready
                                 @ This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the
                                 @ LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit is kept set
                                 @ if IWDG is activated.
                                 @ This bit is reset by system reset.
                                 @ 0: LSI oscillator not ready
.EQU  RCC_CSR_LSIRDY, 1<<1       @ 1: LSI oscillator ready
.EQU  RCC_CSR_LSEON_N, 8         @ Bit 8 LSEON: External low-speed oscillator enable
                                 @ This bit is set and cleared by software.
                                 @ It is reset by setting the RTCRST bit or by a POR.
                                 @ 0: LSE oscillator OFF
.EQU  RCC_CSR_LSEON, 1<<8        @ 1:LSE oscillator ON
.EQU  RCC_CSR_LSERDY_N, 9        @ Bit 9 LSERDY: External low-speed oscillator ready
                                 @ This bit is set and cleared by hardware to indicate when the LSE oscillator is stable. After the
                                 @ LSEON bit is cleared, LSERDY goes low after 6 LSE oscillator clock cycles.
                                 @ It is reset by setting the RTCRST bit or by a POR.
                                 @ 0: External 32 kHz oscillator not ready
.EQU  RCC_CSR_LSERDY, 1<<9       @ 1: External 32 kHz oscillator ready
.EQU  RCC_CSR_LSEBYP_N, 10       @ Bit 10 LSEBYP: External low-speed oscillator bypass
                                 @ This bit is set and cleared by software to bypass oscillator in debug mode. This bit can be
                                 @ written only when the LSE oscillator is disabled.
                                 @ It is reset by setting the RTCRST bit or by a POR.
                                 @ 0: LSE oscillator not bypassed
.EQU  RCC_CSR_LSEBYP, 1<<10      @ 1: LSE oscillator bypassed
.EQU  RCC_CSR_LSECSSON_N, 11     @ Bit 11 LSECSSON CSS on LSE enable
                                 @ Set by software to enable the Clock Security System on LSE (32 kHz oscillator).
                                 @ LSECSSON must be enabled after the LSE and LSI oscillators are enabled (LSEON and
                                 @ LSION bits enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after the
                                 @ RTCSEL bit is selected.
                                 @ Once enabled this bit cannot be disabled, except after an LSE failure detection (LSECSSD
                                 @ =1). In that case the software MUST disable the LSECSSON bit.
                                 @ Reset by power on reset and RTC software reset (RTCRST bit).
                                 @ 0: CSS on LSE (32 kHz oscillator) OFF
.EQU  RCC_CSR_LSECSSON, 1<<11    @ 1: CSS on LSE (32 kHz oscillator) ON
                           @ Note: This bit is available in Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only
.EQU  RCC_CSR_LSECSSD_N, 12      @ Bit 12 LSECSSD: CSS on LSE failure Detection
                                 @ Set by hardware to indicate when a failure has been detected by the Clock Security System
                                 @ on the external 32 kHz oscillator (LSE).
                                 @ Reset by power on reset and RTC software reset (RTCRST bit).
                                 @ 0: No failure detected on LSE (32 kHz oscillator)
.EQU  RCC_CSR_LSECSSD, 1<<12     @ 1: Failure detected on LSE (32 kHz oscillator)
                           @ Note: This bit is available in Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  RCC_CSR_RTCSEL_N, 16       @ Bits 17:16 RTCSEL[1:0]: RTC and LCD clock source selection
                                 @ These bits are set by software to select the clock source for the RTC.
                                 @ Once the RTC and LCD clock source has been selected it cannot be switched until RTCRST
                                 @ is set or a Power On Reset occurred. The only exception is if the LSE oscillator clock was
                                 @ selected, if the LSE clock stops and it is detected by the CSS, in that case the clock can be
                                 @ switched.
.EQU  RCC_CSR_RTCSEL_NOCLOCK, 0  @ 00: No clock
.EQU  RCC_CSR_RTCSEL_LSE, 1<<16  @ 01: LSE oscillator clock used as RTC/LCD clock
.EQU  RCC_CSR_RTCSEL_LSI, 2<<16  @ 10: LSI oscillator clock used as RTC/LCD clock
.EQU  RCC_CSR_RTCSEL_HSE, 3<<16  @ 11: HSE oscillator clock divided by a programmable prescaler (selection through the
                                 @ RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC/LCD clock
                                 @ If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and
                                 @ Standby low-power modes, and can be used as wake-up source. However, when the HSE
                                 @ clock is used as RTC clock source, the RTC cannot be used in Stop and Standby low-power
                                 @ modes.
.EQU  RCC_CSR_RTCEN_N, 22        @ Bit 22 RTCEN: RTC clock enable
                                 @ This bit is set and cleared by software.
                                 @ It is reset by setting the RTCRST bit or by a POR.
                                 @ 0: RTC clock disabled
.EQU  RCC_CSR_RTCEN, 1<<22       @ 1: RTC clock enabled
.EQU  RCC_CSR_RTCRST_N, 23       @ Bit 23 RTCRST: RTC software reset
                                 @ This bit is set and cleared by software.
                                 @ 0: Reset not activated
.EQU  RCC_CSR_RTCRST, 1<<23      @ 1: Resets the RTC peripheral, its clock source selection and the backup registers.
.EQU  RCC_CSR_RMVF_N, 24         @ Bit 24 RMVF: Remove reset flag
                                 @ This bit is set by software to clear the reset flags.
                                 @ 0: No effect
.EQU  RCC_CSR_RMVF  , 1<<24      @ 1: Clear the reset flags
.EQU  RCC_CSR_OBLRRSTF_N, 25     @ Bit 25 OBLRSTF Options bytes loading reset flag
                                 @ This bit is set by hardware when an OBL reset occurs.
                                 @ It is cleared by writing to the RMVF bit, or by a POR.
                                 @ 0: No OBL reset occurred
.EQU  RCC_CSR_OBLRRSTF, 1<<25    @ 1: OBL reset occurred
.EQU  RCC_CSR_PINRSTF_N, 26      @ Bit 26 PINRSTF: PIN reset flag
                                 @ This bit is set by hardware when a reset from the NRST pin occurs.
                                 @ It is cleared by writing to the RMVF bit, or by a POR.
                                 @ 0: No reset from NRST pin occurred
.EQU  RCC_CSR_PINRSTF, 1<<26     @ 1: Reset from NRST pin occurred
.EQU  RCC_CSR_PORRSTF_N, 27      @ Bit 27 PORRSTF: POR/PDR reset flag
                                 @ This bit is set by hardware when a POR/PDR reset occurs.
                                 @ It is cleared by writing to the RMVF bit.
                                 @ 0: No POR/PDR reset occurred
.EQU  RCC_CSR_PORRSTF, 1<<27     @ 1: POR/PDR reset occurred
.EQU  RCC_CSR_SFTRSTF_N, 28      @ Bit 28 SFTRSTF: Software reset flag
                                 @ This bit is set by hardware when a software reset occurs.
                                 @ It is cleared by writing to the RMVF bit, or by a POR.
                                 @ 0: No software reset occurred
.EQU  RCC_CSR_SFTRSTF, 1<<28     @ 1: Software reset occurred
.EQU  RCC_CSR_IWDGRSTF_N, 29     @ Bit 29 IWDGRSTF: Independent watchdog reset flag
                                 @ This bit is set by hardware when an independent watchdog reset from VDD domain occurs.
                                 @ It is cleared by writing to the RMVF bit, or by a POR.
                                 @ 0: No watchdog reset occurred
.EQU  RCC_CSR_IWDGRSTF, 1<<29    @ 1: Watchdog reset occurred
.EQU  RCC_CSR_WWDGRSTF_N, 30     @ Bit 30 WWDGRSTF: Window watchdog reset flag
                                 @ This bit is set by hardware when a window watchdog reset occurs.
                                 @ It is cleared by writing to the RMVF bit, or by a POR.
                                 @ 0: No window watchdog reset occurred
.EQU  RCC_CSR_WWDGRSTF, 1<<30    @ 1: Window watchdog reset occurred
.EQU  RCC_CSR_LPWRRSTF_N, 31     @ Bit 31 LPWRRSTF: Low-power reset flag
                                 @ This bit is set by hardware when a Low-power management reset occurs.
                                 @ It is cleared by writing to the RMVF bit, or by a POR.
                                 @ 0: No Low-power management reset occurred
.EQU  RCC_CSR_LPWRRSTF, 1<<31    @ 1: Low-power management reset occurred
                                 @ For further information on Low-power management reset, refer to Low-power management
                                 @ reset.
@.END

