@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"

.EQU  FSMC             , 0xA0000000

@.ITEM     FSMC
.EQU  FSMC_BCR1          , 0x00                    @ chip-select control register 1
.EQU  FSMC_BTR1          , 0x04                    @ chip-select timing register 1
.EQU  FSMC_BWTR1         , 0x0104                  @ write timing registers


@.ITEM     FSMC_BCR1
.EQU  FSMC_BCR1_RSTVAL   , 0x000030DB              @ Reset value: 0x000030DB for Bank1
.EQU  FSMC_BCR_CBURSTRW  , 1 << 19                 @ Bit 19 CBURSTRW: Write burst enable
.EQU  FSMC_BCR_CPSIZE    , 7 << 16                 @ Bits 18: 16 CPSIZE[2:0]: CRAM page size
.EQU  FSMC_BCR_CPSIZE_N  , 16
.EQU  FSMC_BCR_ASYNCWAIT , 1 << 15                 @ Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
.EQU  FSMC_BCR_EXTMOD    , 1 << 14                 @ Bit 14 EXTMOD: Extended mode enable
.EQU  FSMC_BCR_WAITEN    , 1 << 13                 @ Bit 13 WAITEN: Wait enable bit
.EQU  FSMC_BCR_WREN      , 1 << 12                 @ Bit 12 WREN: Write enable bit
.EQU  FSMC_BCR_WAITCFG   , 1 << 11                 @ Bit 11 WAITCFG: Wait timing configuration
.EQU  FSMC_BCR_WRAPMOD   , 1 << 10                 @ Bit 10 WRAPMOD: Wrapped burst mode support
.EQU  FSMC_BCR_WAITPOL   , 1 << 9                  @ Bit 9 WAITPOL: Wait signal polarity bit.
.EQU  FSMC_BCR_BURSTEN   , 1 << 8                  @ Bit 8 BURSTEN: Burst enable bit
.EQU  FSMC_BCR_FACCEN    , 1 << 6                  @ Bit 6 FACCEN: Flash access enable
.EQU  FSMC_BCR_MWID      , 3 << 4                  @ Bits 5:4 MWID[1:0]: Memory databus width
.EQU  FSMC_BCR_MWID_N    , 4
.EQU  FSMC_BCR_MTYP      , 3 << 2                  @ Bits 3:2 MTYP[1:0]: Memory type.
.EQU  FSMC_BCR_MTYP_N    , 2
.EQU  FSMC_BCR_MUXEN     , 1 << 1                  @ Bit 1 MUXEN: Address/data multiplexing enable bit
.EQU  FSMC_BCR_MBKEN     , 1 << 0                  @ Bit 0 MBKEN: Memory bank enable bit


@.ITEM     FSMC_BTR1
.EQU  FSMC_BTR_RSTVAL    , 0x0FFFFFFF              @ Reset value: 0x0FFFFFFF for all Banks
.EQU  FSMC_BTR_ACCMOD    , 3 << 28                 @ Bits 29:28 ACCMOD[1:0]: Access mode
.EQU  FSMC_BTR_ACCMOD_N  , 28
.EQU  FSMC_BTR_DATLAT    , 0xF << 24               @ Bits 27:24 DATLAT[3:0]: Data latency for synchronous NOR Flash memory (see note below bit description table)
.EQU  FSMC_BTR_DATLAT_N  , 24
.EQU  FSMC_BTR_CLKDIV    , 0xF << 20               @ Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FSMC_CLK signal)
.EQU  FSMC_BTR_CLKDIV_N  , 20
.EQU  FSMC_BTR_BUSTURN   , 0xF << 16               @ Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
.EQU  FSMC_BTR_BUSTURN_N , 16
.EQU  FSMC_BTR_DATAST    , 0xFF << 8               @ Bits 15:8 DATAST[7:0]: Data-phase duration
.EQU  FSMC_BTR_DATAST_N  , 8
.EQU  FSMC_BTR_ADDHLD    , 0xF << 4                @ Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
.EQU  FSMC_BTR_ADDHLD_N  , 4
.EQU  FSMC_BTR_ADDSET    , 0xF << 0                @ Bits 3:0 ADDSET[3:0]: Address setup phase duration
.EQU  FSMC_BTR_ADDSET_N  , 0


@.ITEM     FSMC_BWTR1
.EQU  FSMC_BWTR_RSTVAL    , 0x0FFFFFFF              @ Reset value: 0x0FFFFFFF for all Banks
.EQU  FSMC_BWTR_ACCMOD    , 3 << 28                 @ Bits 29:28 ACCMOD[1:0]: Access mode
.EQU  FSMC_BWTR_ACCMOD_N  , 28
.EQU  FSMC_BWTR_BUSTURN   , 0xF << 16               @ Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
.EQU  FSMC_BWTR_BUSTURN_N , 16
.EQU  FSMC_BWTR_DATAST    , 0xFF << 8               @ Bits 15:8 DATAST[7:0]: Data-phase duration
.EQU  FSMC_BWTR_DATAST_N  , 8
.EQU  FSMC_BWTR_ADDHLD    , 0xF << 4                @ Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
.EQU  FSMC_BWTR_ADDHLD_N  , 4
.EQU  FSMC_BWTR_ADDSET    , 0xF << 0                @ Bits 3:0 ADDSET[3:0]: Address setup phase duration
.EQU  FSMC_BWTR_ADDSET_N  , 0

