@.CHARSET CP1251

@ +---------------------------------------------------------------+
@ |              Определения Embedded Flash memory                |
@ |                           STM32F0x0xxx                        |
@ +---------------------------------------------------------------+

.include "/src/inc/base.inc"

@.ITEM     AHB1PERIPH_BASE
.EQU  FLASH_BASE    , AHB1PERIPH_BASE + 0x2000
.EQU  FLASH         , PERIPH_BASE + FLASH_BASE
@.END

@.ITEM     FLASH_BASE
.EQU  FLASH_ACR     , 0x00    @ Flash access control register
.EQU  FLASH_KEYR    , 0x04    @ Flash key register
.EQU  FLASH_OPTKEYR , 0x08    @ Flash option key register
.EQU  FLASH_SR      , 0x0C    @ Flash status register
.EQU  FLASH_CR      , 0x10    @ Flash control register
.EQU  FLASH_AR      , 0x14    @ Flash address register
.EQU  FLASH_OBR     , 0x1C    @ Flash Option byte register
.EQU  FLASH_WRPR    , 0x20    @ Write protection register
@.END

@.item FLASH_ACR
.equ FLASH_ACR_LATENCY_N, 0   @These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
                              @ 000: Zero wait state, if SYSCLK  24 MHz
                              @ 001: One wait state, if 24 MHz < SYSCLK  48 MHz
.equ FLASH_ACR_PRFTBE, 1<<4   @Prefetch buffer enable
                              @ 0: Prefetch is disabled
                              @ 1: Prefetch is enabled
.equ FLASH_ACR_PRFTBS, 1<<5   @ Prefetch buffer status
                              @ This bit provides the status of the prefetch buffer.
                              @ 0: Prefetch buffer is disabled
                              @ 1: Prefetch buffer is enabled
                              @ Note: The prefetch status is set to 1 as soon a first fetch request is done
@.end

@.item FLASH_KEYR
.equ FLASH_KEYR_FKEY_M, 0xFFFFFFFF           @ Flash key
                                             @These bits represent the keys to unlock the Flash.
@.end

@.item FLASH_OPTKEYR
.equ FLASH_OPTKEYR_OPTKEY_M, 0xFFFFFFFF      @Option byte key
                                             @ These bits represent the keys to unlock the OPTWRE..
@.end

@.item FLASH_SR
.equ FLASH_SR_BSY, 1<<0       @ Busy
                              @ This indicates that a Flash operation is in progress. This is set on the beginning of a Flash
                              @ operation and reset when the operation finishes or when an error occurs.
.equ FLASH_SR_PGERR, 1<<2     @ Programming error
                              @ Set by hardware when an address to be programmed contains a value different from '0xFFFF'
                              @ before programming.
                              @ Reset by writing 1.
                              @ Note: The STRT bit in the FLASH_CR register should be reset before starting a programming
                              @ operation.
.equ FLASH_SR_WRPRTERR, 1<<4  @ Write protection error
                              @ Set by hardware when programming a write-protected address of the Flash memory.
                              @ Reset by writing 1.
.equ FLASH_SR_EOP, 1<<5       @ End of operation
                              @ Set by hardware when a Flash operation (programming / erase) is completed.
                              @ Reset by writing 1.
                              @ Note: EOP is asserted at the end of each successful program or erase operation
@.end

@.item FLASH_CR
.equ FLASH_CR_PG, 1<<0        @ Flash programming chosen.
.equ FLASH_CR_PER, 1<<1       @ Page Erase chosen.
.equ FLASH_CR_MER, 1<<2       @ Mass erase. Erase of all user pages chosen.
.equ FLASH_CR_OPTPG, 1<<4     @ Option byte programming. Option byte programming chosen.
.equ FLASH_CR_OPTER, 1<<5     @ Option byte erase. Option byte erase chosen.
.equ FLASH_CR_STRT, 1<<6      @ Start This bit triggers an ERASE operation when set. This bit is set only by software and reset when
                              @ the BSY bit is reset.
.equ FLASH_CR_LOCK, 1<<7      @ Lock. Write to 1 only. When it is set, it indicates that the Flash is locked. This bit is reset by hardware
                              @ after detecting the unlock sequence.
                              @ In the event of unsuccessful unlock operation, this bit remains set until the next reset.
.equ FLASH_CR_OPTWRE, 1<<9    @ Option byte write enable. When set, the option byte can be programmed. This bit is set on writing the correct key
                              @ sequence to the FLASH_OPTKEYR register.
                              @ This bit can be reset by software
.equ FLASH_CR_ERRIE, 1<<10    @ Error interrupt enable. This bit enables the interrupt generation on an error when PGERR / WRPRTERR are set in the
                              @ FLASH_SR register.
                              @ 0: Interrupt generation disabled
                              @ 1: Interrupt generation enabled
.equ FLASH_CR_EOPIE, 1<<12    @ End of operation interrupt enable. This bit enables the interrupt generation when the EOP bit in the FLASH_SR register
                              @ goes to 1.
                              @ 0: Interrupt generation disabled
                              @ 1: Interrupt generation enabled
.equ FLASH_CR_OBL_LAUNCH, 1<<13    @ Force option byte loading. When set to 1, this bit forces the option byte reloading. This operation generates
                                   @ a system reset.
                                   @ 0: Inactive
                                   @ 1: Active
@.end

@.item FLASH_AR
.equ FLASH_AR_FAR_M, 0xFFFFFFFF    @ Flash Address
                                   @ Chooses the address to program when programming is selected, or a page to erase when Page
                                   @ Erase is selected.
                                   @ Note: Write access to this register is blocked when the BSY bit in the FLASH_SR register is set.
@.end

@.item FLASH_OBR
.equ FLASH_OBR_OPTERR, 1<<0        @ Option byte error
                                   @ When set, this indicates that the loaded option byte and its complement do not match. The
                                   @ corresponding byte is set to 0xFF in respective FLASH_OBR or FLASH_WRPR register.
.equ FLASH_OBR_RDPRT_N, 1          @ Read protection level status
                                   @ 00: Read protection level 0 is enabled (ST production configuration)
                                   @ 01: Read protection level 1 is enabled
                                   @ 11: Read protection level 2 is enabled.
.equ FLASH_OBR_WDG_SW, 1<<8
.equ FLASH_OBR_NRST_STOP, 1<<9
.equ FLASH_OBR_NRST_STDBY, 1<<10
.equ FLASH_OBR_NBOOT1, 1<<12
.equ FLASH_OBR_VDDA_MONITOR, 1<<13
.equ FLASH_OBR_RAM_PARITY_CHECK, 1<<14
.equ FLASH_OBR_DATA0_M, 0x00FF0000
.equ FLASH_OBR_DATA1_M, 0xFF000000
@.end

@.item FLASH_WRPR
.equ FLASH_WRPR_WRP_M, 0xFFFFFFFF  @ Write protect
                                   @ This register contains the write-protection option byte loaded by the OBL.
@.end






