@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                        Базовые константы ADC                     |
@ |                              STM32L100                           |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APB2PERIPH_BASE
.equ ADC_BASE          , APB2PERIPH_BASE + 0x2400
.EQU ADC               , PERIPH_BASE + ADC_BASE
@.END

@.item  ADC ADC_BASE
.equ ADC_SR             , 0x00 @ ADC status register
.equ ADC_CR1            , 0x04 @ ADC control register 1
.equ ADC_CR2            , 0x08 @ ADC control register 2
.equ ADC_SMPR1          , 0x0C @ ADC sample time register 1
.equ ADC_SMPR2          , 0x10 @ ADC sample time register 2
.equ ADC_SMPR3          , 0x14 @ ADC sample time register 3
.equ ADC_JOFR1          , 0x18 @ ADC injected channel data offset register 1
.equ ADC_JOFR2          , 0x1C @ ADC injected channel data offset register 2
.equ ADC_JOFR3          , 0x20 @ ADC injected channel data offset register 3
.equ ADC_JOFR4          , 0x24 @ ADC injected channel data offset register 4
.equ ADC_HTR            , 0x28 @ ADC watchdog higher threshold register
.equ ADC_LTR            , 0x2C @ ADC watchdog lower threshold register
.equ ADC_SQR1           , 0x30 @ ADC regular sequence register 1
.equ ADC_SQR2           , 0x34 @ ADC regular sequence register 2
.equ ADC_SQR3           , 0x38 @ ADC regular sequence register 3
.equ ADC_SQR4           , 0x3C @ ADC regular sequence register 4
.equ ADC_SQR5           , 0x40 @ ADC regular sequence register 5
.equ ADC_JSQR           , 0x44 @ ADC injected sequence register
.equ ADC_JDR1           , 0x48 @ ADC injected data register 1
.equ ADC_JDR2           , 0x4C @ ADC injected data register 2
.equ ADC_JDR3           , 0x50 @ ADC injected data register 3
.equ ADC_JDR4           , 0x54 @ ADC injected data register 4
.equ ADC_DR             , 0x58 @ ADC regular data register
.equ ADC_SMPR0          , 0x5C @ ADC sample time register 0 (ADC_SMPR0)
.equ ADC_CSR            , 0x00+0x300 @ ADC common status register (ADC_CSR)
.equ ADC_CCR            , 0x04+0x300 @ ADC common control register (ADC_CCR)
@.END

@.ITEM     ADC_SR
.EQU  ADC_SR_AWD_N       , 0     @ Bit 0 AWD: Analog watchdog flag
                                 @ This bit is set by hardware when the converted voltage crosses the values programmed in
                                 @ the ADC_LTR and ADC_HTR registers. It is cleared by software.
                                 @ 0: No analog watchdog event occurred
.EQU  ADC_SR_AWD         , 1     @ 1: Analog watchdog event occurred
.EQU  ADC_SR_EOC_N       , 1     @ Bit 1 EOC: Regular channel end of conversion
                                 @ This bit is set by hardware at the end of the conversion of a regular group of channels. It is
                                 @ cleared by software or by reading the ADC_DR register.
                                 @ 0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)
.EQU  ADC_SR_EOC         , 1<<1  @ 1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)
.EQU  ADC_SR_JEOC_N      , 2     @ Bit 2 JEOC: Injected channel end of conversion
                                 @ This bit is set by hardware at the end of the conversion of all injected channels in the group.
                                 @ It is cleared by software.
                                 @ 0: Conversion is not complete
.EQU  ADC_SR_JEOC        , 1<<2  @ 1: Conversion complete
.EQU  ADC_SR_JSTRT_N     , 3     @ Bit 3 JSTRT: Injected channel start flag
                                 @ This bit is set by hardware when injected group conversion starts. It is cleared by software.
                                 @ 0: No injected group conversion started
.EQU  ADC_SR_JSTRT       , 1<<3  @ 1: Injected group conversion has started
.EQU  ADC_SR_STRT_N      , 4     @ Bit 4 STRT: Regular channel start flag
                                 @ This bit is set by hardware when regular channel conversion starts. It is cleared by software.
                                 @ 0: No regular channel conversion started
.EQU  ADC_SR_STRT        , 1<<4  @ 1: Regular channel conversion has started
.EQU  ADC_SR_OVR_N       , 5     @ Bit 5 OVR: Overrun
                                 @ This bit is set by hardware when regular conversion data are lost. It is cleared by software.
                                 @ Overrun detection is enabled only when DMA = 1 or EOCS = 1.
                                 @ 0: No overrun occurredF
.EQU  ADC_SR_OVR         , 1<<5  @ 1: Overrun has occurred
.EQU  ADC_SR_ADDONS_N    , 6     @ Bit 6 ADONS: ADC ON status
                                 @ This bit is set and cleared by hardware to indicate if the ADC is ready to convert.
                                 @ 0: The ADC is not ready
.EQU  ADC_SR_ADDONS      , 1<<6  @ 1: The ADC is ready to convert. External triggers can be enabled, the SWSTART and
                                 @ JSWSTART bits can be set.
.EQU  ADC_SR_RCNR_N      , 8     @ Bit 8 RCNR: Regular channel not ready
                                 @ This bit is set and cleared by hardware after one of the SQRx register is written or after the
                                 @ OVR bit is cleared. It indicates if a new regular conversion can be launched (by setting the
                                 @ SWSTART bit).
                                 @ 0: Regular channel ready
.EQU  ADC_SR_RCNR        , 1<<8  @ 1: Regular channel not ready, SWSTART must not be set
.EQU  ADC_SR_JCNR_N      , 9     @ Bit 9 JCNR: Injected channel not ready
                                 @ This bit is set and cleared by hardware after the JSQR register is written. It indicates if a new
                                 @ injected conversion can be launched (by setting the JSWSTART bit).
                                 @ 0: Injected channel ready
.EQU  ADC_SR_JCNR        , 1<<9  @ 1: Injected channel not ready, JSWSTART must not be set
@.END

@.ITEM     ADC_CR1
.EQU  ADC_CR1_AWDCH_N    , 0     @ Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
                                 @ These bits are set and cleared by software. They select the input channel to be guarded by
                                 @ the analog watchdog.
                                 @ 00000: ADC analog input ADC_IN0
                                 @ 00001: ADC analog input ADC_IN1
                                 @ ...
                                 @ 11000: ADC analog input ADC_IN24
                                 @ 11001: ADC analog input ADC_IN25
                                 @ 11010: ADC analog input ADC_IN26
                                 @ Other values reserved.
                           @ Note: ADC analog inputs ADC_IN16, ADC_IN17 and ADC_IN26 are internally connected to
                                 @ the temperature sensor, to VREFINT and to VCOMP, respectively.
.EQU  ADC_CR1_EOCIE      , 1<<5  @ Bit 5 EOCIE: Interrupt enable for EOC
                                 @ This bit is set and cleared by software to enable/disable the end of conversion interrupt.
                                 @ 0: EOC interrupt disabled
                                 @ 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
.EQU  ADC_CR1_AWDIE      , 1<<6  @ Bit 6 AWDIE: Analog watchdog interrupt enable
                                 @ This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
                                 @ 0: Analog watchdog interrupt disabled
                                 @ 1: Analog watchdog interrupt enabled
.EQU  ADC_CR1_JEOCIE     , 1<<7  @ Bit 7 JEOCIE: Interrupt enable for injected channels
                                 @ This bit is set and cleared by software to enable/disable the end of conversion interrupt for
                                 @ injected channels.
                                 @ 0: JEOC interrupt disabled
                                 @ 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
.EQU  ADC_CR1_SCAN       , 1<<8  @ Bit 8 SCAN: Scan mode
                                 @ This bit is set and cleared by software to enable/disable the Scan mode. In the Scan mode,
                                 @ the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
                                 @ 0: Scan mode disabled
                                 @ 1: Scan mode enabled
                           @ Note: This bit must be written only when ADON=0.
.EQU  ADC_CR1_AWDSGL     , 1<<9  @ Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
                                 @ This bit is set and cleared by software to enable/disable the analog watchdog on the channel
                                 @ identified by the AWDCH[4:0] bits.
                                 @ 0: Analog watchdog enabled on all channels
                                 @ 1: Analog watchdog enabled on a single channel
.EQU  ADC_CR1_JAUTO      , 1<<10 @ Bit 10 JAUTO: Automatic injected group conversion
                                 @ This bit is set and cleared by software to enable/disable automatic injected group conversion
                                 @ after regular group conversion.
                                 @ 0: Automatic injected group conversion disabled
                                 @ 1: Automatic injected group conversion enabled
                           @ Note: This bit must be written only when ADON=0.
.EQU  ADC_CR1_DISCEN     , 1<<11 @ Bit 11 DISCEN: Discontinuous mode on regular channels
                                 @ This bit is set and cleared by software to enable/disable Discontinuous mode on regular
                                 @ channels.
                                 @ 0: Discontinuous mode on regular channels disabled
                                 @ 1: Discontinuous mode on regular channels enabled
                           @ Note: This bit must be written only when ADON=0.
.EQU  ADC_CR1_JDISCEN    , 1<<12 @ Bit 12 JDISCEN: Discontinuous mode on injected channels
                                 @ This bit is set and cleared by software to enable/disable discontinuous mode on the injected
                                 @ channels of a group.
                                 @ 0: Discontinuous mode on injected channels disabled
                                 @ 1: Discontinuous mode on injected channels enabled
                           @ Note: This bit must be written only when ADON=0.
.EQU  ADC_CR1_DISCNUM_N  , 13          @ 15:13  DISCNUM[2:0]: Discontinuous mode channel count
                                       @ These bits are written by software to define the number of regular channels to be converted
                                       @ in discontinuous mode, after receiving an external trigger.
.EQU  ADC_CR1_DISCNUM_1  , 0           @ 000: 1 channel
.EQU  ADC_CR1_DISCNUM_2  , 1<<13       @ 001: 2 channels
.EQU  ADC_CR1_DISCNUM_3  , 2<<13       @ 002: 3 channels
.EQU  ADC_CR1_DISCNUM_4  , 3<<13       @ 003: 4 channels
.EQU  ADC_CR1_DISCNUM_5  , 4<<13       @ 004: 5 channels
.EQU  ADC_CR1_DISCNUM_6  , 5<<13       @ 005: 6 channels
.EQU  ADC_CR1_DISCNUM_7  , 6<<13       @ 006: 7 channels
.EQU  ADC_CR1_DISCNUM_8  , 7<<13       @ 007: 8 channels
                           @ Note: This bit must be written only when ADON=0.
.EQU  ADC_CR1_PDD        , 1<<16       @ Bit 16  PDD: Power down during the delay phase
                                       @ This bit is written and cleared by software. When ADON=1, it determines whether the ADC is
                                       @ powered up or down between 2 conversions (or sequences of conversions) when a delay is
                                       @ inserted (DELS bits).
                                       @ 0: The ADC is powered up during the delay
                                       @ 1: The ADC is powered down during the delay
                                 @ Note: This bit must be written only when ADON=0.
.EQU  ADC_CR1_PDI        , 1<<17       @ Bit 17  PDI: Power down during the idle phase
                                       @ This bit is written and cleared by software. When ADON=1, it determines whether the ADC is
                                       @ powered up or down when not converting (waiting for a hardware or software trigger event).
                                       @ 0: The ADC is powered up when waiting for a start event
                                       @ 1: The ADC is powered down when waiting for a start event
                                 @ Note: This bit must be written only when ADON=0
.EQU  ADC_CR1_JAWDEN     , 1<<22       @ Bit 22 JAWDEN: Analog watchdog enable on injected channels
                                       @ This bit is set and cleared by software.
                                       @ 0: Analog watchdog disabled on injected channels
                                       @ 1: Analog watchdog enabled on injected channels
.EQU  ADC_CR1_AWDEN      , 1<<23       @ Bit 23 AWDEN: Analog watchdog enable on regular channels
                                       @ This bit is set and cleared by software.
                                       @ 0: Analog watchdog disabled on regular channels
                                       @ 1: Analog watchdog enabled on regular channels
.EQU  ADC_CR1_RES_N      , 24          @ Bits 25:24 RES[1:0]: Resolution
                                       @ These bits are written by software to select the resolution of the conversion.
.EQU  ADC_CR1_RES_12BIT  , 0           @ 00: 12-bit (12 ADCCLK cycles)
.EQU  ADC_CR1_RES_10BIT  , 1<<24       @ 01: 10-bit (11 ADCCLK cycles)
.EQU  ADC_CR1_RES_8BIT   , 2<<24       @ 10: 8-bit (9 ADCCLK cycles)
.EQU  ADC_CR1_RES_6BIT   , 3<<24       @ 11: 6-bit (7 ADCCLK cycles)
.EQU  ADC_CR1_OVRIE_N    , 26          @ Bit 26 OVRIE: Overrun interrupt enable
                                       @ This bit is set and cleared by software to enable/disable the Overrun interrupt.
.EQU  ADC_CR1_OVRIE_DISABLE, 0         @ 0: Overrun interrupt disabled
.EQU  ADC_CR1_OVRIE_ENABLED, 1<<26     @ 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
@.end

@.ITEM     ADC_CR2
.EQU  ADC_CR2_ADON_N     , 0           @ Bit 0 ADON: A/D Converter ON / OFF
                                       @ This bit is set and cleared by software.
                                       @ 0: Disable ADC conversion and go to power down mode
.EQU  ADC_CR2_ADON       , 1           @ 1: Enable ADC: conversions can start as soon as a start event (hardware or software) is
                                       @ received. When not converting, the ADC goes to the power up or power down mode
                                       @ depending on the PDI and PDD bits.
                                 @ Note: This bit must be set only when ADONS=0 and cleared only when ADONS=1.
.EQU  ADC_CR2_CONT       , 1<<1        @ Bit 1 CONT: Continuous conversion
                                       @ This bit is set and cleared by software. If it is set, conversion takes place continuously until it
                                       @ is cleared.
                                       @ 0: Single conversion mode
                                       @ 1: Continuous conversion mode
.EQU  ADC_CR2_ADC_CFG    , 1<<2        @ Bit 2 ADC_CFG: ADC configuration
                                       @ This bit is set and cleared by software. It selects the bank of channels to be converted.
                                       @ 0: Bank A selected for channels ADC_IN0..31
                                       @ 1: Bank B selected for channels ADC_IN0..31b
                                 @ Note: This bit must be modified only when no conversion is on going.
                                       @ This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only
.EQU  ADC_CR2_DELS_N     , 4           @ Bit 6:4 DELS: Delay selection
                                       @ These bits are set and cleared by software. They define the length of the delay which is
                                       @ applied after a conversion or a sequence of conversions.
.EQU  ADC_CR2_DELS_NODELAY , 0         @ 000: No delay
.EQU  ADC_CR2_DELS_UHC     , 1<<4      @ 001: Until the converted data have been read (DR read or EOC=0 for regular conversions,
                                       @ JEOC=0 for injected conversions)
.EQU  ADC_CR2_DELS_7C     , 2<<4       @ 010: 7 APB clock cycles after the end of conversion
.EQU  ADC_CR2_DELS_15C    , 3<<4       @ 011: 15 APB clock cycles after the end of conversion
.EQU  ADC_CR2_DELS_31C    , 4<<4       @ 100: 31 APB clock cycles after the end of conversion
.EQU  ADC_CR2_DELS_63     , 5<<4       @ 101: 63 APB clock cycles after the end of conversion
.EQU  ADC_CR2_DELS_127C   , 6<<4       @ 110: 127 APB clock cycles after the end of conversion
.EQU  ADC_CR2_DELS_255C   , 7<<4       @ 111: 255 APB clock cycles after the end of conversion
                                 @ Note: 1- This bit must be written only when ADON=0.
                                       @ 2- Due to clock domain crossing, a latency of 2 or 3 ADC clock cycles is added to the
                                       @ delay before a new conversion can start.
                                       @ 3- The delay required for a given frequency ratio between the APB clock and the ADC
                                       @ clock depends on the activity on the AHB and APB busses. If the ADC is the only
                                       @ peripheral that needs to transfer data, then a minimum delay should be configured:
                                       @ 15 APB clock cycles if fAPB < fADCCLK/2 or else 7 APB clock cycles if fAPB < fADCCLK,
                                       @ otherwise no delay is needed.
.EQU  ADC_CR2_DMA        , 1<<8        @ Bit 8  DMA: Direct memory access mode (for single ADC mode)
                                       @ This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
                                       @ 0: DMA mode disabled
                                       @ 1: DMA mode enabled
.EQU  ADC_CR2_DDS        , 1<<9        @ Bit 9  DDS: DMA disable selection (for single ADC mode)
                                       @ This bit is set and cleared by software.
                                       @ 0: No new DMA request is issued after the last transfer (as configured in the DMA controller)
                                       @ 1: DMA requests are issued as long as data are converted and DMA=1
.EQU  ADC_CR2_EOCS       , 1<<10       @ Bit 10  EOCS: End of conversion selection
                                       @ This bit is set and cleared by software.
                                       @ 0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
                                       @ is enabled only if DMA=1.
                                       @ 1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
.EQU  ADC_CR2_ALIGN      , 1<<11       @ Bit 11 ALIGN: Data alignment
                                       @ This bit is set and cleared by software. Refer to Figure 35 and Figure 36.
                                       @ 0: Right alignment
                                       @ 1: Left alignment
.EQU  ADC_CR2_JEXTSEL_N  , 16          @ Bits 19:16 JEXTSEL[3:0]: External event select for injected group
                                       @ These bits select the external event used to trigger the start of conversion of an injected
                                       @ group.
.EQU  ADC_CR2_JEXTSEL_T9CC1 , 0        @ 0000: TIM9_CC1 event
.EQU  ADC_CR2_JEXTSEL_T9TRGO , 1<<16   @ 0001: TIM9_TRGO event
.EQU  ADC_CR2_JEXTSEL_T2TRGO , 2<<16   @ 0010: TIM2_TRGO event
.EQU  ADC_CR2_JEXTSEL_T2CC1 , 3<<16    @ 0011: TIM2_CC1 event
.EQU  ADC_CR2_JEXTSEL_T4CC4 , 4<<16    @ 0100: TIM3_CC4 event
.EQU  ADC_CR2_JEXTSEL_T4TRGO , 5<<16   @ 0101: TIM4_TRGO event
.EQU  ADC_CR2_JEXTSEL_T4CC1 , 6<<16    @ 0110: TIM4_CC1 event
.EQU  ADC_CR2_JEXTSEL_T4CC2 , 7<<16    @ 0111: TIM4_CC2 event
.EQU  ADC_CR2_JEXTSEL_T4CC3 , 8<<16    @ 1000: TIM4_CC3 event
.EQU  ADC_CR2_JEXTSEL_T10CC1 , 9<<16   @ 1001: TIM10_CC1 event
.EQU  ADC_CR2_JEXTSEL_T7TRGO , 10<<16  @ 1010: TIM7_TRGO event
                                       @ 1011: Reserved
                                       @ 1100: Reserved
                                       @ 1101: Reserved
                                       @ 1110: Reserved
.EQU  ADC_CR2_JEXTSEL_EXTI15 , 15<<16  @ 1111: EXTI line15
.EQU  ADC_CR2_JEXTEN_20  , 20          @ Bits 21:20 JEXTEN: External trigger enable for injected channels
                                       @ These bits are set and cleared by software to select the external trigger polarity and enable
                                       @ the trigger of an injected group.
.EQU  ADC_CR2_JEXTEN_DIS   ,  0        @ 00: Trigger detection disabled
.EQU  ADC_CR2_JEXTEN_RISING,  1<<20    @ 01: Trigger detection on the rising edge
.EQU  ADC_CR2_JEXTEN_FALLING, 2<<20    @ 10: Trigger detection on the falling edge
.EQU  ADC_CR2_JEXTEN_BOTH  ,  3<<20    @ 11: Trigger detection on both the rising and falling edges
                                 @ Note: The external trigger must be enabled only when ADONS=1.
.EQU  ADC_CR2_JSWSTART   , 1<<22       @ Bit 22 JSWSTART: Start conversion of injected channels
                                       @ This bit is set by software and cleared by hardware as soon as the conversion starts.
                                       @ 0: Reset state
                                       @ 1: Starts conversion of injected channels
                                 @ Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
.EQU  ADC_CR2_EXTSEL_N   , 24          @ Bits 27:24 EXTSEL[3:0]: External event select for regular group
                                       @ These bits select the external event used to trigger the start of conversion of a regular group:
.EQU  ADC_CR2_EXTSEL_T9CC2, 0          @ 0000: TIM9_CC2 event
.EQU  ADC_CR2_EXTSEL_T9TRGO, 1<<24     @ 0001: TIM9_TRGO event
.EQU  ADC_CR2_EXTSEL_T2CC3, 2<<24      @ 0010: TIM2_CC3 event
.EQU  ADC_CR2_EXTSEL_T2CC2, 3<<24      @ 0011: TIM2_CC2 event
.EQU  ADC_CR2_EXTSEL_T3TRGO, 4<<24     @ 0100: TIM3_TRGO event
.EQU  ADC_CR2_EXTSEL_T4CC4, 5<<24      @ 0101: TIM4_CC4 event
.EQU  ADC_CR2_EXTSEL_T2TRGO, 6<<24     @ 0110: TIM2_TRGO event
.EQU  ADC_CR2_EXTSEL_T3CC1, 7<<24      @ 0111: TIM3_CC1 event
.EQU  ADC_CR2_EXTSEL_T3CC3, 8<<24      @ 1000: TIM3_CC3 event
.EQU  ADC_CR2_EXTSEL_T4TRGO, 9<<24     @ 1001: TIM4_TRGO event
.EQU  ADC_CR2_EXTSEL_T6TRGO, 10<<24    @ 1010: TIM6_TRGO event
                                       @ 1011: Reserved
                                       @ 1100: Reserved
                                       @ 1101: Reserved
                                       @ 1110: Reserved
.EQU  ADC_CR2_EXTSEL_EXTI11, 15<<24    @ 1111: EXTI line11
.EQU  ADC_CR2_EXTEN_N    , 28          @ Bits 29:28 EXTEN: External trigger enable for regular channels
                                       @ These bits are set and cleared by software to select the external trigger polarity and enable
                                       @ the trigger of a regular group.
.EQU  ADC_CR2_EXTEN_DIS  , 0           @ 00: Trigger detection disabled
.EQU  ADC_CR2_EXTEN_RISING , 1<<28     @ 01: Trigger detection on the rising edge
.EQU  ADC_CR2_EXTEN_FALLING, 2<<28     @ 10: Trigger detection on the falling edge
.EQU  ADC_CR2_EXTEN_BOTH   , 3<<28     @ 11: Trigger detection on both the rising and falling edges
.EQU  ADC_CR2_SWSTART      , 1<<30     @ Bit 30 SWSTART: Start conversion of regular channels
.EQU  ADC_CR2_SWSTART_N    , 30        @ This bit is set by software to start conversion and cleared by hardware as soon as the
                                       @ conversion starts.
                                       @ 0: Reset state
                                       @ 1: Starts conversion of regular channels
                                 @ Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
@.end

@.ITEM     ADC_SMPR1
.EQU  ADC_SMPR1_SMP20_N    , 0         @ Bits 2:0   SMP20[2:0]: Channel 20 sampling time selection
                                       @ These bits are written by software to select the sampling time individually for each channel.
                                       @ During sampling cycles, the channel selection bits must remain unchanged.
.EQU  ADC_SMPR1_SMP21_N    , 3         @ Bits 5:3   SMP21[2:0] bits (Channel 21 Sample time selection)
.EQU  ADC_SMPR1_SMP22_N    , 6         @ Bits 8:6   SMP22[2:0] bits (Channel 22 Sample time selection)
.EQU  ADC_SMPR1_SMP23_N    , 9         @ Bits 11:9  SMP23[2:0] bits (Channel 23 Sample time selection)
.EQU  ADC_SMPR1_SMP24_N    , 12        @ Bits 14:12 SMP24[2:0] bits (Channel 24 Sample time selection)
.EQU  ADC_SMPR1_SMP25_N    , 15        @ Bits 17:15 SMP25[2:0] bits (Channel 25 Sample time selection)
.EQU  ADC_SMPR1_SMP26_N    , 18        @ Bits 20:18 SMP26[2:0] bits (Channel 26 Sample time selection)
.EQU  ADC_SMPR1_SMP27_N    , 21        @ Bits 23:21 SMP27[2:0] bits (Channel 27 Sample time selection)
.EQU  ADC_SMPR1_SMP28_N    , 24        @ Bits 26:24 SMP28[2:0] bits (Channel 28 Sample time selection)
.EQU  ADC_SMPR1_SMP29_N    , 27        @ Bits 29:27 SMP29[2:0] bits (Channel 29 Sample time selection)
@.END


@.ITEM     ADC_SMPR2
.EQU  ADC_SMPR2_SMP10_N     , 0       @ Bits 2:0   SMP10[2:0]: Channel 10 sampling time selection
                                      @ These bits are written by software to select the sampling time individually for each channel.
                                      @ During sample cycles, the channel selection bits must remain unchanged.
.EQU  ADC_SMPR2_SMP11_N     , 3       @ Bits 5:3   SMP11[2:0] bits (Channel 11 Sample time selection)
.EQU  ADC_SMPR2_SMP12_N     , 6       @ Bits 8:6   SMP12[2:0] bits (Channel 12 Sample time selection)
.EQU  ADC_SMPR2_SMP13_N     , 9       @ Bits 11:9  SMP13[2:0] bits (Channel 13 Sample time selection)
.EQU  ADC_SMPR2_SMP14_N     , 12      @ Bits 14:12 SMP14[2:0] bits (Channel 14 Sample time selection)
.EQU  ADC_SMPR2_SMP15_N     , 15      @ Bits 17:15 SMP15[2:0] bits (Channel 15 Sample time selection)
.EQU  ADC_SMPR2_SMP16_N     , 18      @ Bits 20:18 SMP16[2:0] bits (Channel 16 Sample time selection)
.EQU  ADC_SMPR2_SMP17_N     , 21      @ Bits 23:21 SMP17[2:0] bits (Channel 17 Sample time selection)
.EQU  ADC_SMPR2_SMP18_N     , 24      @ Bits 26:24 SMP18[2:0] bits (Channel 18 Sample time selection)
.EQU  ADC_SMPR2_SMP19_N     , 27      @ Bits 29:27 SMP19[2:0] bits (Channel 19 Sample time selection)
@.end

@.ITEM     ADC_SMPR3
.EQU  ADC_SMPR3_SMP0_N     , 0       @ Bits 2:0   SMP0[2:0]: Channel 0 sampling time selection
                                      @ These bits are written by software to select the sampling time individually for each channel.
                                      @ During sample cycles, the channel selection bits must remain unchanged.
.EQU  ADC_SMPR3_SMP1_N     , 3       @ Bits 5:3   SMP1[2:0] bits (Channel 1 Sample time selection)
.EQU  ADC_SMPR3_SMP2_N     , 6       @ Bits 8:6   SMP2[2:0] bits (Channel 2 Sample time selection)
.EQU  ADC_SMPR3_SMP3_N     , 9       @ Bits 11:9  SMP3[2:0] bits (Channel 3 Sample time selection)
.EQU  ADC_SMPR3_SMP4_N     , 12      @ Bits 14:12 SMP4[2:0] bits (Channel 4 Sample time selection)
.EQU  ADC_SMPR3_SMP5_N     , 15      @ Bits 17:15 SMP5[2:0] bits (Channel 5 Sample time selection)
.EQU  ADC_SMPR3_SMP6_N     , 18      @ Bits 20:18 SMP6[2:0] bits (Channel 6 Sample time selection)
.EQU  ADC_SMPR3_SMP7_N     , 21      @ Bits 23:21 SMP7[2:0] bits (Channel 7 Sample time selection)
.EQU  ADC_SMPR3_SMP8_N     , 24      @ Bits 26:24 SMP8[2:0] bits (Channel 8 Sample time selection)
.EQU  ADC_SMPR3_SMP9_N     , 27      @ Bits 29:27 SMP9[2:0] bits (Channel 9 Sample time selection)
@.end

@.ITEN ADC SMPR1 ADC SMPR2 ADC SMPR3
                                     @ значение времени преобразования без сдвига !!!
                                     @ применение в виде:  ADC_SMPRx_SMPx_16C<<ADC_SMPR1_SMP20_N
                                     @ для 20го преобразования 16 циклов преобразования
.EQU  ADC_SMPRx_SMPx_4C  , 0         @ 000: 4 cycles
.EQU  ADC_SMPRx_SMPx_9C , 1          @ 001: 9 cycles
.EQU  ADC_SMPRx_SMPx_16C , 2         @ 010: 16 cycles
.EQU  ADC_SMPRx_SMPx_24C , 3         @ 011: 24 cycles
.EQU  ADC_SMPRx_SMPx_48C , 4         @ 100: 48 cycles
.EQU  ADC_SMPRx_SMPx_96C, 5          @ 101: 96 cycles
.EQU  ADC_SMPRx_SMPx_192C, 6         @ 110: 192 cycles
.EQU  ADC_SMPRx_SMPx_384C, 7         @ 111: 384 cycles
@.end

@.ITEM     ADC_JOFR1
.EQU  ADC_JOFR1_JOFFSET1 , 0x0FFF        @Data offset for injected channel 1
@.end

@.ITEM     ADC_JOFR2
.EQU  ADC_JOFR2_JOFFSET2 , 0x0FFF        @Data offset for injected channel 2
@.end

@.ITEM     ADC_JOFR3
.EQU  ADC_JOFR3_JOFFSET3 , 0x0FFF        @Data offset for injected channel 3
@.end

@.ITEM     ADC_JOFR4
.EQU  ADC_JOFR4_JOFFSET4 , 0x0FFF        @Data offset for injected channel 4
@.end

@.ITEM     ADC_HTR
.EQU  ADC_HTR_HT         , 0x0FFF        @Analog watchdog high threshold
@.end

@.ITEM     ADC_LTR
.EQU  ADC_LTR_LT         , 0x0FFF        @Analog watchdog low threshold
@.end

@.ITEM     ADC_SQR1
.EQU  ADC_SQR1_SQ25_N    , 0             @ Bits 4:0 SQ25[4:0]: 25th conversion in regular sequence
.EQU  ADC_SQR1_SQ26_N    , 5             @ Bits 9:5 SQ26[4:0]: 26th conversion in regular sequence
.EQU  ADC_SQR1_SQ27_N    , 10            @ Bits 14:10 SQ27[4:0]: 27th conversion in regular sequence
.EQU  ADC_SQR1_SQ28_N    , 15            @ Bits 19:15 SQ28[4:0]: 28th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 16th in
                                         @ the conversion sequence.
.EQU  ADC_SQR1_L         , 20            @ Bits 23:20 L[3:0]: Regular channel sequence length
                                         @ These bits are written by software to define the total number of conversions in the regular
                                         @ channel conversion sequence.
                                         @ 0000: 1 conversion
                                         @ 0001: 2 conversions
                                         @ ...
                                         @ 1111: 16 conversions
                                         @ ...
                                         @ 11010: 27 conversions
                                         @ 11011: 28 conversions (applicable in Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
@.end

@.ITEM     ADC_SQR2
.EQU  ADC_SQR2_SQ19_N     , 0            @ Bits 4:0 SQ19[4:0]: 19th conversion in regular sequence
.EQU  ADC_SQR2_SQ20_N     , 5            @ Bits 9:5 SQ20[4:0]: 20th conversion in regular sequence
.EQU  ADC_SQR2_SQ21_N     , 10           @ Bits 14:10 SQ21[4:0]: 21th conversion in regular sequence
.EQU  ADC_SQR2_SQ22_N    , 15            @ Bits 19:15 SQ22[4:0]: 22th conversion in regular sequence
.EQU  ADC_SQR2_SQ23_N    , 20            @ Bits 24:20 SQ23[4:0]: 23th conversion in regular sequence
.EQU  ADC_SQR2_SQ24_N    , 25            @ Bits 29:26 SQ24[4:0]: 24th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 12th in
                                         @ the sequence to be converted.
@.end

@.ITEM     ADC_SQR3
.EQU  ADC_SQR3_SQ13_N     , 0             @ Bits 4:0 SQ13[4:0]: 13st conversion in regular sequence
.EQU  ADC_SQR3_SQ14_N     , 5             @ Bits 9:5 SQ14[4:0]: 14nd conversion in regular sequence
.EQU  ADC_SQR3_SQ15_N     , 10            @ Bits 14:10 SQ15[4:0]: 15rd conversion in regular sequence
.EQU  ADC_SQR3_SQ16_N     , 15            @ Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
.EQU  ADC_SQR3_SQ17_N     , 20            @ Bits 24:20 SQ17[4:0]: 17th conversion in regular sequence
.EQU  ADC_SQR3_SQ18_N     , 25            @ Bits 29:25 SQ18[4:0]: 18th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 6th in the
                                         @ sequence to be converted.
@.end

@.ITEM     ADC_SQR4
.EQU  ADC_SQR4_SQ7_N     , 0             @ Bits 4:0 SQ7[4:0]: 7st conversion in regular sequence
.EQU  ADC_SQR4_SQ8_N     , 5             @ Bits 9:5 SQ8[4:0]: 8nd conversion in regular sequence
.EQU  ADC_SQR4_SQ9_N     , 10            @ Bits 14:10 SQ9[4:0]: 9rd conversion in regular sequence
.EQU  ADC_SQR4_SQ10_N     , 15            @ Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
.EQU  ADC_SQR4_SQ11_N     , 20            @ Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
.EQU  ADC_SQR4_SQ12_N     , 25            @ Bits 29:25 SQ12[4:0]: 12th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 6th in the
                                         @ sequence to be converted.
@.end

@.ITEM     ADC_SQR5
.EQU  ADC_SQR5_SQ1_N     , 0             @ Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
.EQU  ADC_SQR5_SQ2_N     , 5             @ Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
.EQU  ADC_SQR5_SQ3_N     , 10            @ Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
.EQU  ADC_SQR5_SQ4_N     , 15            @ Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
.EQU  ADC_SQR5_SQ5_N     , 20            @ Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
.EQU  ADC_SQR5_SQ6_N     , 25            @ Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 6th in the
                                         @ sequence to be converted.
@.end

@.ITEM     ADC_JSQR
.EQU  ADC_JSQR_JSQ1_N    , 0             @ Bits 4:0 JSQ1[4:0]: 1th conversion in injected sequence (when JL[1:0]=3, see note below)
                                         @ These bits are written by software with the channel number (0..31) assigned as the 4th in the
                                         @ sequence to be converted. The channel is selected in bank A or bank B depending on the
                                         @ ADC_CFG bit in the ADC_CR2 register.
.EQU  ADC_JSQR_JSQ2_N    , 5             @ Bits 9:5 JSQ2[4:0]: 2th conversion in injected sequence
.EQU  ADC_JSQR_JSQ3_N    , 10            @ Bits 14:10 JSQ3[4:0]: 3th conversion in injected sequence
.EQU  ADC_JSQR_JSQ4_N    , 15            @ Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence
.EQU  ADC_JSQR_JL_N      , 20            @ Bits 21:20 JL[1:0]: Injected sequence length
                                         @ These bits are written by software to define the total number of conversions in the injected
                                         @ channel conversion sequence.
                                         @ 00: 1 conversion
                                         @ 01: 2 conversions
                                         @ 10: 3 conversions
                                         @ 11: 4 conversions
@.end

@.ITEM     ADC_JDR1
.EQU  ADC_JDR1_JDATA     , 0xFFFF        @Injected data
@.end

@.ITEM     ADC_JDR2
.EQU  ADC_JDR2_JDATA     , 0xFFFF        @Injected data
@.end

@.ITEM     ADC_JDR3
.EQU  ADC_JDR3_JDATA     , 0xFFFF        @Injected data
@.end

@.ITEM     ADC_JDR4
.EQU  ADC_JDR4_JDATA     , 0xFFFF        @Injected data
@.end

@.ITEM     ADC_DR
.EQU  ADC_DR_DATA        , 0x0000FFFF    @Regular data
@.end

@.ITEM     ADC_SMPR0
.EQU ADC_SMPR0_SMP31_N, 3   @ Bits 5:3 SMPx[2:0]: Channel 31 Sample time selection
                            @ @ These bits are written by software to select the sampling time individually for each channel.
                            @ During the sampling cycles, the channel selection bits must remain unchanged.
.EQU ADC_SMPR0_SMP30_N, 0   @ Bits 2:0 SMPx[2:0]: Channel 30 Sample time selection
@.END

@.ITEM     ADC_CSR
.EQU  ADC_CSR_AWD1       , 1             @ Bit 0 AWD1: Analog watchdog flag of the ADC
                                         @ This bit is a copy of the AWD bit in the ADC_SR register.
.EQU  ADC_CSR_EOC1       , 1<<1          @ Bit 1 EOC1: End of conversion of the ADC
                                         @ This bit is a copy of the EOC bit in the ADC_SR register.
.EQU  ADC_CSR_JEOC1      , 1<<2          @ Bit 2 JEOC1: Injected channel end of conversion of the ADC
                                         @ This bit is a copy of the JEOC bit in the ADC_SR register.
.EQU  ADC_CSR_JSTRT1     , 1<<3          @ Bit 3 JSTRT1: Injected channel Start flag of the ADC
                                         @ This bit is a copy of the JSTRT bit in the ADC_SR register.
.EQU  ADC_CSR_STRT1      , 1<<4          @ Bit 4 STRT1: Regular channel Start flag of the ADC
                                         @ This bit is a copy of the STRT bit in the ADC_SR register.
.EQU  ADC_CSR_OVR1       , 1<<5          @ Bit 5 OVR1: Overrun flag of the ADC
                                         @ This bit is a copy of the OVR bit in the ADC_SR register.
.EQU  ADC_CSR_ADONS1     , 1<<6          @ Bit 6 ADONS1: ADON Status of ADC1
                                         @ This bit is a copy of the ADONS bit in the ADC_SR register.
@.end

@.ITEM     ADC_CCR
.EQU  ADC_CCR_TSVREFE_N  , 23            @ Bit 23 TSVREFE: Temperature sensor and VREFINT enable
                                         @ This bit is set and cleared by software to enable/disable the temperature sensor and the
                                         @ VREFINT channel.
                                         @ 0: Temperature sensor and VREFINT channel disabled
.EQU  ADC_CCR_TSVREFE    , 1<<23         @ 1: Temperature sensor and VREFINT channel enabled
.EQU  ADC_CCR_ADCPRE_N   , 16            @ Bits 17:16  ADCPRE: ADC prescaler
                                         @ Set and cleared by software to select the frequency of the clock to the ADC. .
.EQU  ADC_CCR_ADCPRE_DIV1, 0             @  00: HSI divided by 1
.EQU  ADC_CCR_ADCPRE_DIV2, 1<<16         @  01: HSI divided by 2
.EQU  ADC_CCR_ADCPRE_DIV4, 2<<16         @  10: HSI divided by 4
                                         @  11: Reserved
.EQU  ADC_CCR_ADCPRE_0   , 0x00010000    @Bit 0
.EQU  ADC_CCR_ADCPRE_1   , 0x00020000    @Bit 1
@.end


