@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы PWR                        |
@ |                           STM32F42x                              |
@ +------------------------------------------------------------------+
@.enddesc


.include       "/src/inc/base.inc"

@.item     APB1PERIPH_BASE
.equ  PWR_BASE                , ( APB1PERIPH_BASE + 0x7000 )
@.end

@.item     PWR_BASE
.EQU  PWR_CR1       , 0x00
.EQU  PWR_CR2       , 0x04
.EQU  PWR_CR3       , 0x08
.EQU  PWR_CR4       , 0x0C
.EQU  PWR_SR1       , 0x10
.EQU  PWR_SR2       , 0x14
.EQU  PWR_SCR       , 0x18
.EQU  PWR_PUCRA     , 0x20
.EQU  PWR_PDCRA     , 0x24
.EQU  PWR_PUCRB     , 0x28
.EQU  PWR_PDCRB     , 0x2C
.EQU  PWR_PUCRC     , 0x30
.EQU  PWR_PDCRC     , 0x34
.EQU  PWR_PUCRD     , 0x38
.EQU  PWR_PDCRD     , 0x3C
.EQU  PWR_PUCRE     , 0x40
.EQU  PWR_PDCRE     , 0x44
.EQU  PWR_PUCRF     , 0x48
.EQU  PWR_PDCRF     , 0x4C
.EQU  PWR_PUCRG     , 0x50
.EQU  PWR_PDCRG     , 0x54
.EQU  PWR_PUCRH     , 0x58
.EQU  PWR_PDCRH     , 0x5C
.EQU  PWR_PUCRI     , 0x60
.EQU  PWR_PDCRI     , 0x64
.EQU  PWR_CR5       , 0x80
@.END

@.item PWR_CR1
.EQU  PWR_CR1_LPR   , 1 << 14    @ Bit 14 LPR: Low-power run
                                 @ When this bit is set, the regulator is switched from main mode (MR) to low-power mode
                                 @ (LPR).
                                 @ Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
.EQU  PWR_CR1_VOS_N , 9          @ Bits 10:9 VOS: Voltage scaling range selection
                                 @ 00: Cannot be written (forbidden by hardware)
.EQU  PWR_CR1_VOS_1 , 1 << 9     @ 01: Range 1
.EQU  PWR_CR1_VOS_2 , 2 << 9     @ 10: Range 2
                                 @ 11: Cannot be written (forbidden by hardware)
.EQU  PWR_CR1_DBR_N , 8          @ Bit 8 DBP: Disable backup domain write protection
                                 @ In reset state, the RTC and backup registers are protected against parasitic write access.
                                 @ This bit must be set to enable write access to these registers.
.EQU  PWR_CR1_DBR_DISABLE , 0 << 8 @ 0: Access to RTC and Backup registers disabled
.EQU  PWR_CR1_DBR_DISABLE , 1 << 8 @ 1: Access to RTC and Backup registers enabled
.EQU  PWR_CR1_RRSTP_N, 4         @ Bit 4 RRSTP: SRAM3 retention in Stop 2 mode
.EQU  PWR_CR1_RRSTP_OFF, 0 << 4  @ 0: SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost)
.EQU  PWR_CR1_RRSTP_ON,  0 << 4  @ 1: SRAM3 is powered in Stop 2 mode (RAM3 content is kept).
.EQU  PWR_CR1_LPMS_N, 0          @ Bits 2:0 LPMS[2:0]: Low-power mode selection
                                 @ These bits select the low-power mode entered when CPU enters the Deepsleep mode.
.EQU  PWR_CR1_LPMS_STOP0, 0      @ 000: Stop 0 mode
.EQU  PWR_CR1_LPMS_STOP1, 1      @ 001: Stop 1 mode
.EQU  PWR_CR1_LPMS_STOP2, 2      @ 010: Stop 2 mode
.EQU  PWR_CR1_LPMS_STANDBY, 3    @ 011: Standby mode
.EQU  PWR_CR1_LPMS_SHUTDOWN, 4   @ 1xx: Shutdown mode
                           @ Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered
                                 @ instead of Stop 2.
                                 @ In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration
                                 @ in PWR_CR3.
@.END

@.item     PWR_CR2
.EQU  PWR_CR2_USV_N , 10         @ Bit 10 USV: VDDUSB USB supply valid
                                 @ This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose.
                                 @ Setting this bit is mandatory to use the USB OTG_FS peripheral. If VDDUSB is not always
                                 @ present in the application, the PVM can be used to determine whether this supply is ready or
                                 @ not.
                                 @ 0: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply.
.EQU  PWR_CR2_USV   , 1 << 10    @ 1: VDDUSB is valid.
.EQU  PWR_CR2_IOSV_N, 9          @ Bit 9 IOSV: VDDIO2 Independent I/Os supply valid
                                 @ This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.
                                 @ Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the
                                 @ application, the PVM can be used to determine whether this supply is ready or not.
                                 @ 0: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply.
.EQU  PWR_CR2_IOSV  , 1 << 9     @ 1: VDDIO2 is valid.
.EQU  PWR_CR2_PVME4_N, 7         @ Bit 7 PVME4: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V
                                 @ 0: PVM4 (VDDA monitoring vs. 2.2V threshold) disable.
.EQU  PWR_CR2_PVME4 , 1 << 7     @ 1: PVM4 (VDDA monitoring vs. 2.2V threshold) enable.
.EQU  PWR_CR2_PVME3_N, 6         @ Bit 6 PVME3: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
                                 @ 0: PVM3 (VDDA monitoring vs. 1.62V threshold) disable.
.EQU  PWR_CR2_PVME3 , 1 << 6     @ 1: PVM3 (VDDA monitoring vs. 1.62V threshold) enable.
.EQU  PWR_CR2_PVME2_N, 5         @ Bit 5 PVME2: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V
                                 @ 0: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable.
.EQU  PWR_CR2_PVME2 , 1 << 5     @ 1: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable.
.EQU  PWR_CR2_PVME1_N, 4         @ Bit 4 PVME1: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
                                 @ 0: PVM1 (VDDUSB monitoring vs. 1.2V threshold) disable.
.EQU  PWR_CR2_PVME1 , 1 << 4     @ 1: PVM1 (VDDUSB monitoring vs. 1.2V threshold) enable.
.EQU  PWR_CR2_PLS_N , 1          @ Bits 3:1 PLS[2:0]: Power voltage detector level selection.
                                 @ These bits select the voltage threshold detected by the power voltage detector:
.EQU  PWR_CR2_PLS_2V0, 0         @ 000: VPVD0 around 2.0 V
.EQU  PWR_CR2_PLS_2V2, 1         @ 001: VPVD1 around 2.2 V
.EQU  PWR_CR2_PLS_2V4, 2         @ 010: VPVD2 around 2.4 V
.EQU  PWR_CR2_PLS_2V5, 3         @ 011: VPVD3 around 2.5 V
.EQU  PWR_CR2_PLS_2V6, 4         @ 100: VPVD4 around 2.6 V
.EQU  PWR_CR2_PLS_2V8, 5         @ 101: VPVD5 around 2.8 V
.EQU  PWR_CR2_PLS_2V9, 6         @ 110: VPVD6 around 2.9 V
.EQU  PWR_CR2_PLS_IN,  7         @ 111: External input analog voltage PVD_IN (compared internally to VREFINT)
                           @ Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
                                 @ SYSCFG_CBR register.
                                 @ These bits are reset only by a system reset.
.EQU  PWR_CR2_PVDE_N, 0          @ Bit 0 PVDE: Power voltage detector enable
                                 @ 0: Power voltage detector disable.
.EQU  PWR_CR2_PVDE  , 1          @ 1: Power voltage detector enable.
                           @ Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
                                 @ register.
                                 @ This bit is reset only by a system reset.
@.end







@.item     PWR_CR
.equ  PWR_CR_RST_VAL          , 0x00004000    @ значение по умолчанию
.equ  PWR_CR_LPDS             , 0x01     @  Bit 0 LPDS: Low-power deepsleep
.equ  PWR_CR_PDDS             , 0x02     @  Bit 1 PDDS: Power-down deepsleep
.equ  PWR_CR_CWUF             , 0x04     @  Bit 2 CWUF: Clear wakeup flag
.equ  PWR_CR_CSBF             , 0x08     @  Bit 3 CSBF: Clear standby flag
.equ  PWR_CR_PVDE             , 0x10     @  Bit 4 PVDE: Power voltage detector enable
.equ  PWR_CR_VOS_N            , 14       @  Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
.EQU  PWR_CR_FPDS_N           , 9        @  Bits 9 FPDS: Flash power-down in Stop mode
.equ  PWR_CR_DBP_N            , 8        @  Bits 8 DBP: Disable backup domain write protection
.equ  PWR_CR_PLS_N            , 5        @  Bits 7:5 PLS[2:0]: PVD level selection
.equ  PWR_CR_PVDE_N           , 4        @  Bits PVDE: Power voltage detector enable
.equ  PWR_CR_CSBF_N           , 3        @  Bits CSBF: Clear standby flag
.equ  PWR_CR_CWUF_N           , 2        @  Bits CWUF: Clear wakeup flag
.equ  PWR_CR_PDDS_N           , 1        @  Bits PDDS: Power-down deepsleep
.equ  PWR_CR_LPDS_N           , 0        @  Bits LPDS: Low-power deepsleep
.equ  PWR_CR_PLS_2D0V         , 0 << 5
.equ  PWR_CR_PLS_2D1V         , 1 << 5
.equ  PWR_CR_PLS_2D3V         , 2 << 5
.equ  PWR_CR_PLS_2D5V         , 3 << 5
.equ  PWR_CR_PLS_2D6V         , 4 << 5
.equ  PWR_CR_PLS_2D7V         , 5 << 5
.equ  PWR_CR_PLS_2D8V         , 6 << 5
.equ  PWR_CR_PLS_2D9V         , 7 << 5
.equ  PWR_CR_DBP              , 1 << 8    @  Bit 8 DBP: Disable backup domain write protection
.equ  PWR_CR_FPDS             , 1 << 9    @  Bit 9 FPDS: Flash power-down in Stop mode
.equ  PWR_CR_LPUDS            , 1 << 10    @  Bit 10 LPUDS: Low-power regulator in deepsleep under-drive mode
.equ  PWR_CR_MRUDS            , 1 << 11    @  Bit 11 MRUDS: Main regulator in deepsleep under-drive mode
.equ  PWR_CR_ADCDC1           , 1 << 13    @  Bit 13 1: Refer to AN4073 for details on how to use this bit.
.equ  PWR_CR_VOS_0            , 1 << 14    @  01: Scale 3 mode
.equ  PWR_CR_VOS_1            , 2 << 14    @  10: Scale 2 mode
@.end

@.item     PWR_CSR
.equ  PWR_CSR_UDRDY_N         , 18       @ Bits 19:18 UDRDY[1:0]: Under-drive ready flag
.equ  PWR_CSR_UDRDY_0         , 1 << 18    @ 00: Under-drive is disabled
.equ  PWR_CSR_UDRDY_1         , 2 << 18    @ 11:Under-drive mode is activated in Stop mode.
.equ  PWR_CSR_ODSWRDY_N       , 17       @ Bit 17 ODSWRDY: Over-drive mode switching ready
.equ  PWR_CSR_ODSWRDY         , 1 << 17    @ Bit 17 ODSWRDY: Over-drive mode switching ready
.equ  PWR_CSR_ODRDY_N         , 16       @ Bit 16 ODRDY: Over-drive mode ready
.equ  PWR_CSR_ODRDY           , 1 << 16    @ 1: Over-drive mode ready
.equ  PWR_CSR_VOSRDY_N        , 14       @ Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
.equ  PWR_CSR_VOSRDY          , 1 << 14    @ 1: Ready
.equ  PWR_CSR_BRE_N           , 9        @ Bit 9 BRE: Backup regulator enable
.equ  PWR_CSR_BRE             , 1 << 9    @ 1: Backup regulator enabled
.equ  PWR_CSR_EWUP_N          , 8        @  Bit 8 EWUP: Enable WKUP pin
.equ  PWR_CSR_EWUP            , 1 << 8    @ 1: WKUP pin is used for wakeup from Standby mode
.equ  PWR_CSR_BRR_N           , 3        @  Bit 3 BRR: Backup regulator ready
.equ  PWR_CSR_BRR             , 1 << 3    @ 1: Backup Regulator ready
.equ  PWR_CSR_PVDO_N          , 2        @ Bit 2 PVDO: PVD output
.equ  PWR_CSR_PVDO            , 1 << 2    @ 1: VDD is lower than the PVD
.equ  PWR_CSR_SBF_N           , 1        @ Bit 1 SBF: Standby flag
.equ  PWR_CSR_SBF             , 1 << 1    @1: Device has been in Standby mode
.equ  PWR_CSR_WUF_N           , 0        @ Bit 0 WUF: Wakeup flag
.equ  PWR_CSR_WUF             , 1        @ 1: A wakeup event was received from the WKUP pin
@.end
