@.ITEM     I2C2 I2C2_BASE I2C1 I2C1_BASE
.EQU  I2C_CR1            , 0x00                    @ I2C Control register 1 (I2C_CR1)
.EQU  I2C_CR2            , 0x04                    @ I2C Control register 2 (I2C_CR2)
.EQU  I2C_OAR1           , 0X08                    @ I2C Own address register 1 (I2C_OAR1)
.EQU  I2C_OAR2           , 0X0C                    @ I2C Own address register 2 (I2C_OAR2)
.EQU  I2C_DR             , 0X10                    @ I2C Data register (I2C_DR)
.EQU  I2C_SR1            , 0X14                    @ I2C Status register 1 (I2C_SR1)
.EQU  I2C_SR2            , 0X18                    @ I2C Status register 2 (I2C_SR2)
.EQU  I2C_CCR            , 0X1C                    @ I2C Clock control register (I2C_CCR)
.EQU  I2C_TRISE          , 0X20                    @ I2C TRISE register (I2C_TRISE)
@.end

@.ITEM     I2C_CR1
.EQU  I2C_CR1_SWRST      , 1 << 15                 @ Bit 15 SWRST: Software reset
.EQU  I2C_CR1_ALERT      , 1 << 13                 @ Bit 13 ALERT: SMBus alert
.EQU  I2C_CR1_PEC        , 1 << 12                 @ Bit 12 PEC: Packet error checking
.EQU  I2C_CR1_POS        , 1 << 11                 @ Bit 11 POS: Acknowledge/PEC Position (for data reception)
.EQU  I2C_CR1_ACK        , 1 << 10                 @ Bit 10 ACK: Acknowledge enable
.EQU  I2C_CR1_STOP       , 1 << 9                  @ Bit 9 STOP: Stop generation
.EQU  I2C_CR1_START      , 1 << 8                  @ Bit 8 START: Start generation
.EQU  I2C_CR1_NOSTRETCH  , 1 << 7                  @ Bit 7 NOSTRETCH: Clock stretching disable (Slave mode)
.EQU  I2C_CR1_ENGC       , 1 << 6                  @ Bit 6 ENGC: General call enable
.EQU  I2C_CR1_ENPEC      , 1 << 5                  @ Bit 5 ENPEC: PEC enable
.EQU  I2C_CR1_ENARP      , 1 << 4                  @ Bit 4 ENARP: ARP enable
.EQU  I2C_CR1_SMBTYPE    , 1 << 3                  @ Bit 3 SMBTYPE: SMBus type
.EQU  I2C_CR1_SMBUS      , 1 << 1                  @ Bit 1 SMBUS: SMBus mode
.EQU  I2C_CR1_PE         , 1                       @ Bit 0 PE: Peripheral enable
@.end

@.ITEM     I2C_CR2
.EQU  I2C_CR2_LAST       , 1 << 12                 @ Bit 12 LAST: DMA last transfer
.EQU  I2C_CR2_DMAEN      , 1 << 11                 @ Bit 11 DMAEN: DMA requests enable
.EQU  I2C_CR2_ITBUFEN    , 1 << 10                 @ Bit 10 ITBUFEN: Buffer interrupt enable
.EQU  I2C_CR2_ITEVTEN    , 1 << 9                  @ Bit 9 ITEVTEN: Event interrupt enable
.EQU  I2C_CR2_FREQ_N     , 0                       @ Bits 5:0 FREQ[5:0]: Peripheral clock frequency
.EQU  I2C_CR2_FREQ_MIN   , 2                       @ 0b000010: 2 MHz
.EQU  I2C_CR2_FREQ_MAX   , 0B110010                @ 0b110010: 50 MHz
@.end

@.ITEM     I2C_OAR1
.EQU  I2C_OAR1_ADDMODE   , 1 << 15                 @ Bit 15 ADDMODE Addressing mode (slave mode)
.EQU  I2C_OAR1_VAL1      , 1 << 14                 @ Bit 14 Should always be kept at 1 by software.
.EQU  I2C_OAR1_ADD98_N   , 8                       @ Bits 9:8 ADD[9:8]: Interface address 7-bit addressing mode: don’t care 10-bit addressing mode: bits9:8 of address
.EQU  I2C_OAR1_ADD71_N   , 1                       @ Bits 7:1 ADD[7:1]: Interface address bits 7:1 of address
.EQU  I2C_OAR1_ADD0_N    , 0                       @ Bit 0 ADD0: Interface address 7-bit addressing mode: don’t care 10-bit addressing mode: bit 0 of addres
@.end

@.ITEM     I2C_OAR2
.EQU  I2C_OAR2_ADD2_N    , 1                       @ Bits 7:1 ADD2[7:1]: Interface address bits 7:1 of address in dual addressing mode
.EQU  I2C_OAR2_ENDUAL    , 1                       @ Bit 0 ENDUAL: Dual addressing mode enable
@.end

@.ITEM I2C_SR1
.EQU  I2C_SR1_SMBALERT   , 1 << 15                 @ Bit 15 SMBALERT: SMBus alert
.EQU  I2C_SR1_TIMEOUT    , 1 << 14                 @ Bit 14 TIMEOUT: Timeout or Tlow error
.EQU  I2C_SR1_PECERR     , 1 << 12                 @ Bit 12 PECERR: PEC Error in reception
.EQU  I2C_SR1_OVR        , 1 << 11                 @ Bit 11 OVR: Overrun/Underrun
.EQU  I2C_SR1_AF         , 1 << 10                 @ Bit 10 AF: Acknowledge failure
.EQU  I2C_SR1_ARLO       , 1 << 9                  @ Bit 9 ARLO: Arbitration lost (master mode)
.EQU  I2C_SR1_BERR       , 1 << 8                  @ Bit 8 BERR: Bus error
.EQU  I2C_SR1_TXE        , 1 << 7                  @ Bit 7 TxE: Data register empty (transmitters)
.EQU  I2C_SR1_RXNE       , 1 << 6                  @ Bit 6 RxNE: Data register not empty (receivers)
.EQU  I2C_SR1_STOPF      , 1 << 4                  @ Bit 4 STOPF: Stop detection (slave mode)
.EQU  I2C_SR1_ADD10      , 1 << 3                  @ Bit 3 ADD10: 10-bit header sent (Master mode)
.EQU  I2C_SR1_BTF        , 1 << 2                  @ Bit 2 BTF: Byte transfer finished
.EQU  I2C_SR1_ADDR       , 1 << 1                  @ Bit 1 ADDR: Address sent (master mode)/matched (slave mode)
.EQU  I2C_SR1_SB         , 1                       @ Bit 0 SB: Start bit (Master mode)
@.end

@.ITEM     I2C_SR2
.EQU  I2C_SR2_PEC_N      , 1 << 8                  @ Bits 15:8 PEC[7:0] Packet error checking register
.EQU  I2C_SR2_DUALF      , 1 << 7                  @ Bit 7 DUALF: Dual flag (Slave mode)
.EQU  I2C_SR2_SMBHOST    , 1 << 6                  @ Bit 6 SMBHOST: SMBus host header (Slave mode)
.EQU  I2C_SR2_SMBDEFAULT , 1 << 5                  @ Bit 5 SMBDEFAULT: SMBus device default address (Slave mode)
.EQU  I2C_SR2_GENCALL    , 1 << 4                  @ Bit 4 GENCALL: General call address (Slave mode)
.EQU  I2C_SR2_TRA        , 1 << 2                  @ Bit 2 TRA: Transmitter/receiver
.EQU  I2C_SR2_BUSY       , 1 << 1                  @ Bit 1 BUSY: Bus busy
.EQU  I2C_SR2_MSL        , 1                       @ Bit 0 MSL: Master/slave
@.end

@.ITEM     I2C_CCR
.EQU  I2C_CCR_FS         , 1 << 15                 @ Bit 15 F/S: I2C master mode selection
.EQU  I2C_CCR_DUTY       , 1 << 14                 @ Bit 14 DUTY: Fm mode duty cycle
.EQU  I2C_CCR_CCR_N      , 0                       @ Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode)
@.end

@.ITEM     I2C_TRISE
.EQU  I2C_TRISE_RSTVAL   , 0X02                    @ Reset value: 0x0002
.EQU  I2C_TRISE_M        , 0x3F                    @ Mask Bits 5:0 TRISE[5:0]: Maximum rise time in Fm/Sm mode (Master mode)
@.end

