@GNU AS
@.CHARSET  CP1251
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                         Константы EXTI                           |
@ |                  STM32F030xxx \ STM32F070xxx                     |
@ +------------------------------------------------------------------+
@.ENDDESC

.INCLUDE            "/src/inc/base.inc"

@ константы EXTI
@.ITEM     APBPERIPH_BASE
.EQU  EXTI_BASE     , APBPERIPH_BASE + 0x0400    @ EXTI Controls Registers
.EQU  EXTI          , PERIPH_BASE + EXTI_BASE
@.END

@ регистры EXTI для использования в том числе в bit band
@.ITEM     EXTI
.EQU  EXTI_IMR      , EXTI_BASE + 0x00
.EQU  EXTI_EMR      , EXTI_BASE + 0x04
.EQU  EXTI_RTSR     , EXTI_BASE + 0x08
.EQU  EXTI_FTSR     , EXTI_BASE + 0x0C
.EQU  EXTI_SWIER    , EXTI_BASE + 0x10
.EQU  EXTI_PR       , EXTI_BASE + 0x14
@.END

@ Описание битов настройки
@.ITEM EXTI_IMR
.EQU  EXTI_IMR_RST_VAL_x4, 0x0FF40000    @ 0x0FF4 0000 (STM32F030x4, STM32F030x6 devices)
.EQU  EXTI_IMR_RST_VAL_x6, 0x7FF40000    @ 0x7FF4 0000 (STM32F070x6 devices)
.EQU  EXTI_IMR_RST_VAL_x8, 0x0F940000    @ 0x0F94 0000 (STM32F030x8 devices)
.EQU  EXTI_IMR_RST_VAL_xB, 0x7F840000    @ 0x7F84 0000 (STM32F070xB and STM32F030xC devices)
                                         @ Note:The reset value for the internal lines is set to ‘1’ in order to enable the interrupt by default.
.EQU  EXTI_IMR_IM0  , 1         @ Bits 31:0 IMx: Interrupt Mask on line x (x = 31 to 0)
.EQU  EXTI_IMR_IM1  , 1 << 1    @ 0: Interrupt request from Line x is masked
.EQU  EXTI_IMR_IM2  , 1 << 2    @ 1: Interrupt request from Line x is not masked
.EQU  EXTI_IMR_IM3  , 1 << 3
.EQU  EXTI_IMR_IM4  , 1 << 4
.EQU  EXTI_IMR_IM5  , 1 << 5
.EQU  EXTI_IMR_IM6  , 1 << 6
.EQU  EXTI_IMR_IM7  , 1 << 7
.EQU  EXTI_IMR_IM8  , 1 << 8
.EQU  EXTI_IMR_IM9  , 1 << 9
.EQU  EXTI_IMR_IM10 , 1 << 10
.EQU  EXTI_IMR_IM11 , 1 << 11
.EQU  EXTI_IMR_IM12 , 1 << 12
.EQU  EXTI_IMR_IM13 , 1 << 13
.EQU  EXTI_IMR_IM14 , 1 << 14
.EQU  EXTI_IMR_IM15 , 1 << 15
.EQU  EXTI_IMR_IM16 , 1 << 16
.EQU  EXTI_IMR_IM17 , 1 << 17
.EQU  EXTI_IMR_IM18 , 1 << 18
.EQU  EXTI_IMR_IM19 , 1 << 19
.EQU  EXTI_IMR_IM20 , 1 << 20
.EQU  EXTI_IMR_IM21 , 1 << 21
.EQU  EXTI_IMR_IM22 , 1 << 22
.EQU  EXTI_IMR_IM23 , 1 << 23
.EQU  EXTI_IMR_IM24 , 1 << 24
.EQU  EXTI_IMR_IM25 , 1 << 25
.EQU  EXTI_IMR_IM26 , 1 << 26
.EQU  EXTI_IMR_IM27 , 1 << 27
.EQU  EXTI_IMR_IM28 , 1 << 28
.EQU  EXTI_IMR_IM29 , 1 << 29
.EQU  EXTI_IMR_IM30 , 1 << 30
.EQU  EXTI_IMR_IM31 , 1 << 31
@.END

@ Описание битов настройки
@.ITEM EXTI_EMR
.EQU  EXTI_EMR_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  EXTI_EMR_EM0  , 1         @ Bits 31:0 EMx: Event mask on line x (x = 31 to 0)
.EQU  EXTI_EMR_EM1  , 1 << 1    @ 0: Event request from Line x is masked
.EQU  EXTI_EMR_EM2  , 1 << 2    @ 1: Event request from Line x is not masked
.EQU  EXTI_EMR_EM3  , 1 << 3
.EQU  EXTI_EMR_EM4  , 1 << 4
.EQU  EXTI_EMR_EM5  , 1 << 5
.EQU  EXTI_EMR_EM6  , 1 << 6
.EQU  EXTI_EMR_EM7  , 1 << 7
.EQU  EXTI_EMR_EM8  , 1 << 8
.EQU  EXTI_EMR_EM9  , 1 << 9
.EQU  EXTI_EMR_EM10 , 1 << 10
.EQU  EXTI_EMR_EM11 , 1 << 11
.EQU  EXTI_EMR_EM12 , 1 << 12
.EQU  EXTI_EMR_EM13 , 1 << 13
.EQU  EXTI_EMR_EM14 , 1 << 14
.EQU  EXTI_EMR_EM15 , 1 << 15
.EQU  EXTI_EMR_EM16 , 1 << 16
.EQU  EXTI_EMR_EM17 , 1 << 17
.EQU  EXTI_EMR_EM18 , 1 << 18
.EQU  EXTI_EMR_EM19 , 1 << 19
.EQU  EXTI_EMR_EM20 , 1 << 20
.EQU  EXTI_EMR_EM21 , 1 << 21
.EQU  EXTI_EMR_EM22 , 1 << 22
.EQU  EXTI_EMR_EM23 , 1 << 23
.EQU  EXTI_EMR_EM24 , 1 << 24
.EQU  EXTI_EMR_EM25 , 1 << 25
.EQU  EXTI_EMR_EM26 , 1 << 26
.EQU  EXTI_EMR_EM27 , 1 << 27
.EQU  EXTI_EMR_EM28 , 1 << 28
.EQU  EXTI_EMR_EM29 , 1 << 29
.EQU  EXTI_EMR_EM30 , 1 << 30
.EQU  EXTI_EMR_EM31 , 1 << 31
@.END

@ Описание битов настройки
@.ITEM EXTI_RTSR
.EQU  EXTI_RTSR_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
@ Bit 31 FT31: Falling trigger event configuration bit of line 31
@           0: Falling trigger disabled (for Event and Interrupt) for input line
@           1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Bits 30:23 Reserved, must be kept at reset value.
@ Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
@              0: Falling trigger disabled (for Event and Interrupt) for input line.
@              1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Bits 18 Reserved, must be kept at reset value.
@ Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
@             0: Falling trigger disabled (for Event and Interrupt) for input line.
@             1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Note:The external wakeup lines are edge triggered.
@ No glitches must be generated on these lines.
@ If a rising edge on an external interrupt line occurs during a write operation
@ to the EXTI_RTSR register, the pending bit is not set.
@ Rising and falling edge triggers can be set for the same interrupt line.
@ In this case, both generate a trigger condition.
.EQU  EXTI_RTSR_RT0 , 1
.EQU  EXTI_RTSR_RT1 , 1 << 1
.EQU  EXTI_RTSR_RT2 , 1 << 2
.EQU  EXTI_RTSR_RT3 , 1 << 3
.EQU  EXTI_RTSR_RT4 , 1 << 4
.EQU  EXTI_RTSR_RT5 , 1 << 5
.EQU  EXTI_RTSR_RT6 , 1 << 6
.EQU  EXTI_RTSR_RT7 , 1 << 7
.EQU  EXTI_RTSR_RT8 , 1 << 8
.EQU  EXTI_RTSR_RT9 , 1 << 9
.EQU  EXTI_RTSR_RT10, 1 << 10
.EQU  EXTI_RTSR_RT11, 1 << 11
.EQU  EXTI_RTSR_RT12, 1 << 12
.EQU  EXTI_RTSR_RT13, 1 << 13
.EQU  EXTI_RTSR_RT14, 1 << 14
.EQU  EXTI_RTSR_RT15, 1 << 15
.EQU  EXTI_RTSR_RT16, 1 << 16
.EQU  EXTI_RTSR_RT17, 1 << 17
@ .EQU  EXTI_RTSR_RT18      , 1 << 18 @ Reserved
.EQU  EXTI_RTSR_RT19, 1 << 19
.EQU  EXTI_RTSR_RT20, 1 << 20
.EQU  EXTI_RTSR_RT21, 1 << 21
.EQU  EXTI_RTSR_RT22, 1 << 22
@ .EQU  EXTI_RTSR_RT23      , 1 << 23  @ Reserved
@ .EQU  EXTI_RTSR_RT24      , 1 << 24  @ Reserved
@ .EQU  EXTI_RTSR_RT25      , 1 << 25  @ Reserved
@ .EQU  EXTI_RTSR_RT26      , 1 << 26  @ Reserved
@ .EQU  EXTI_RTSR_RT27      , 1 << 27  @ Reserved
@ .EQU  EXTI_RTSR_RT28      , 1 << 28  @ Reserved
@ .EQU  EXTI_RTSR_RT29      , 1 << 29  @ Reserved
@ .EQU  EXTI_RTSR_RT30      , 1 << 30  @ Reserved
.EQU  EXTI_RTSR_RT31, 1 << 31
@.END

 @.ITEM EXTI_FTSR
.EQU EXTI_FTSR_RST_VAL, 0x00000000 @ Reset value: 0x0000 0000
@ Bit 31 FT31: Falling trigger event configuration bit of line 31
@           0: Falling trigger disabled (for Event and Interrupt) for input line
@           1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Bits 30:23 Reserved, must be kept at reset value.
@ Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
@              0: Falling trigger disabled (for Event and Interrupt) for input line.
@              1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Bits 18 Reserved, must be kept at reset value.
@ Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
@             0: Falling trigger disabled (for Event and Interrupt) for input line.
@             1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Note:The external wakeup lines are edge triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set.
@ Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
.EQU  EXTI_FTSR_FT0 , 1
.EQU  EXTI_FTSR_FT1 , 1 << 1
.EQU  EXTI_FTSR_FT2 , 1 << 2
.EQU  EXTI_FTSR_FT3 , 1 << 3
.EQU  EXTI_FTSR_FT4 , 1 << 4
.EQU  EXTI_FTSR_FT5 , 1 << 5
.EQU  EXTI_FTSR_FT6 , 1 << 6
.EQU  EXTI_FTSR_FT7 , 1 << 7
.EQU  EXTI_FTSR_FT8 , 1 << 8
.EQU  EXTI_FTSR_FT9 , 1 << 9
.EQU  EXTI_FTSR_FT10, 1 << 10
.EQU  EXTI_FTSR_FT11, 1 << 11
.EQU  EXTI_FTSR_FT12, 1 << 12
.EQU  EXTI_FTSR_FT13, 1 << 13
.EQU  EXTI_FTSR_FT14, 1 << 14
.EQU  EXTI_FTSR_FT15, 1 << 15
.EQU  EXTI_FTSR_FT16, 1 << 16
.EQU  EXTI_FTSR_FT17, 1 << 17
@ .EQU  EXTI_FTSR_FT18      , 1 << 18 @ Reserved
.EQU  EXTI_FTSR_FT19, 1 << 19
.EQU  EXTI_FTSR_FT20, 1 << 20
.EQU  EXTI_FTSR_FT21, 1 << 21
.EQU  EXTI_FTSR_FT22, 1 << 22
@ .EQU  EXTI_FTSR_FT23      , 1 << 23  @ Reserved
@ .EQU  EXTI_FTSR_FT24      , 1 << 24  @ Reserved
@ .EQU  EXTI_FTSR_FT25      , 1 << 25  @ Reserved
@ .EQU  EXTI_FTSR_FT26      , 1 << 26  @ Reserved
@ .EQU  EXTI_FTSR_FT27      , 1 << 27  @ Reserved
@ .EQU  EXTI_FTSR_FT28      , 1 << 28  @ Reserved
@ .EQU  EXTI_FTSR_FT29      , 1 << 29  @ Reserved
@ .EQU  EXTI_FTSR_FT30      , 1 << 30  @ Reserved
.EQU  EXTI_FTSR_FT31, 1 << 31
@.END




@.ITEM EXTI_SWIER
.EQU EXTI_SWIER_RST_VAL, 0x00000000 @ Reset value: 0x0000 0000
@ Bit 31 FT31: Falling trigger event configuration bit of line 31
@           0: Falling trigger disabled (for Event and Interrupt) for input line
@           1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Bits 30:23 Reserved, must be kept at reset value.
@ Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
@          0: Falling trigger disabled (for Event and Interrupt) for input line.
@          1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Bits 18 Reserved, must be kept at reset value.
@ Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
@             0: Falling trigger disabled (for Event and Interrupt) for input line.
@             1: Falling trigger enabled (for Event and Interrupt) for input line.
@ Note:The external wakeup lines are edge triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set.
@ Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
.EQU  EXTI_SWIER_SW0 , 1
.EQU  EXTI_SWIER_SW1 , 1 << 1
.EQU  EXTI_SWIER_SW2 , 1 << 2
.EQU  EXTI_SWIER_SW3 , 1 << 3
.EQU  EXTI_SWIER_SW4 , 1 << 4
.EQU  EXTI_SWIER_SW5 , 1 << 5
.EQU  EXTI_SWIER_SW6 , 1 << 6
.EQU  EXTI_SWIER_SW7 , 1 << 7
.EQU  EXTI_SWIER_SW8 , 1 << 8
.EQU  EXTI_SWIER_SW9 , 1 << 9
.EQU  EXTI_SWIER_SW10, 1 << 10
.EQU  EXTI_SWIER_SW11, 1 << 11
.EQU  EXTI_SWIER_SW12, 1 << 12
.EQU  EXTI_SWIER_SW13, 1 << 13
.EQU  EXTI_SWIER_SW14, 1 << 14
.EQU  EXTI_SWIER_SW15, 1 << 15
.EQU  EXTI_SWIER_SW16, 1 << 16
.EQU  EXTI_SWIER_SW17, 1 << 17
@ .EQU  EXTI_SWIER_SW18      , 1 << 18 @ Reserved
.EQU  EXTI_SWIER_SW19, 1 << 19
.EQU  EXTI_SWIER_SW20, 1 << 20
.EQU  EXTI_SWIER_SW21, 1 << 21
.EQU  EXTI_SWIER_SW22, 1 << 22
@ .EQU  EXTI_SWIER_SW23      , 1 << 23  @ Reserved
@ .EQU  EXTI_SWIER_SW24      , 1 << 24  @ Reserved
@ .EQU  EXTI_SWIER_SW25      , 1 << 25  @ Reserved
@ .EQU  EXTI_SWIER_SW26      , 1 << 26  @ Reserved
@ .EQU  EXTI_SWIER_SW27      , 1 << 27  @ Reserved
@ .EQU  EXTI_SWIER_SW28      , 1 << 28  @ Reserved
@ .EQU  EXTI_SWIER_SW29      , 1 << 29  @ Reserved
@ .EQU  EXTI_SWIER_SW30      , 1 << 30  @ Reserved
.EQU  EXTI_SWIER_SW31, 1 << 31
@.END


@.ITEM EXTI_PR
@ .EQU EXTI_PR_RST_VAL, @ Reset value: undefined
@ Bit 31 PIF31: Pending bit on line 31
@            0: no trigger request occurred
@            1: selected trigger request occurred
@ This bit is set when the selected edge event arrives on the external interrupt line. This bit is
@ cleared by writing a 1 to the bit.
@ Bits 30:23 Reserved, must be kept at reset value.
@ Bits 22:19 PIFx: Pending bit on line x (x = 22 to 19)
@               0: no trigger request occurred
@               1: selected trigger request occurred
@ This bit is set when the selected edge event arrives on the external interrupt line. This bit is
@ cleared by writing a 1 to the bit.
@ Bits 18 Reserved, must be kept at reset value.
@ Bits 17:0 PIFx: Pending bit on line x (x = 17 to 0)
@              0: no trigger request occurred
@              1: selected trigger request occurred
@ This bit is set when the selected edge event arrives on the external interrupt line. This bit is
@ cleared by writing a 1 to the bit.
.EQU  EXTI_PR_RIF0 , 1
.EQU  EXTI_PR_RIF1 , 1 << 1
.EQU  EXTI_PR_RIF2 , 1 << 2
.EQU  EXTI_PR_RIF3 , 1 << 3
.EQU  EXTI_PR_RIF4 , 1 << 4
.EQU  EXTI_PR_RIF5 , 1 << 5
.EQU  EXTI_PR_RIF6 , 1 << 6
.EQU  EXTI_PR_RIF7 , 1 << 7
.EQU  EXTI_PR_RIF8 , 1 << 8
.EQU  EXTI_PR_RIF9 , 1 << 9
.EQU  EXTI_PR_RIF10, 1 << 10
.EQU  EXTI_PR_RIF11, 1 << 11
.EQU  EXTI_PR_RIF12, 1 << 12
.EQU  EXTI_PR_RIF13, 1 << 13
.EQU  EXTI_PR_RIF14, 1 << 14
.EQU  EXTI_PR_RIF15, 1 << 15
.EQU  EXTI_PR_RIF16, 1 << 16
.EQU  EXTI_PR_RIF17, 1 << 17
@ .EQU  EXTI_PR_RIF18      , 1 << 18 @ Reserved
.EQU  EXTI_PR_RIF19, 1 << 19
.EQU  EXTI_PR_RIF20, 1 << 20
.EQU  EXTI_PR_RIF21, 1 << 21
.EQU  EXTI_PR_RIF22, 1 << 22
@ .EQU  EXTI_PR_RIF23      , 1 << 23  @ Reserved
@ .EQU  EXTI_PR_RIF24      , 1 << 24  @ Reserved
@ .EQU  EXTI_PR_RIF25      , 1 << 25  @ Reserved
@ .EQU  EXTI_PR_RIF26      , 1 << 26  @ Reserved
@ .EQU  EXTI_PR_RIF27      , 1 << 27  @ Reserved
@ .EQU  EXTI_PR_RIF28      , 1 << 28  @ Reserved
@ .EQU  EXTI_PR_RIF29      , 1 << 29  @ Reserved
@ .EQU  EXTI_PR_RIF30      , 1 << 30  @ Reserved
.EQU  EXTI_PR_RIF31, 1 << 31
@.END


