@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  WWDG_BASE      , APB1PERIPH_BASE + 0x2C00
.EQU  WWDG           , PERIPH_BASE + WWDG_BASE

@.ITEM     WWDG IWDG_BASE
.EQU  WWDG_CR        , 0x00                        @ Control register (WWDG_CR)
.EQU  WWDG_CFR       , 0x04                        @ Configuration re gister (WWDG_CFR)
.EQU  WWDG_SR        , 0x08                        @ Status re gister ( WWDG_SR)

@.ITEM     WWDG_CR
.EQU  WWDG_CR_WDGA   , 1 << 7                      @ Bit 7 WDGA: Activation bit
.EQU  WWDG_CR_T_N    , 0                           @ Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)

@.ITEM WWDG_CFR
.EQU  WWDG_CFR_RSTVAL, 0x07F                       @ Reset value: 0x0000 007F
.EQU  WWDG_CFR_EWI   , 1 << 9                      @ Bit 9 EWI: Early wakeup interrupt
.EQU  WWDG_CFR_WDGTB_N, 7                          @ Bits 8:7 WDGTB[1:0]: Timer base
.EQU  WWDG_CFR_WDGTB_DIV1, 0                       @ 00: CK Counter Clock (PCLK1 div 4096) div 1
.EQU  WWDG_CFR_WDGTB_DIV2, 1<<7                    @ 01: CK Counter Clock (PCLK1 div 4096) div 2
.EQU  WWDG_CFR_WDGTB_DIV4, 2<<7                    @ 10: CK Counter Clock (PCLK1 div 4096) div 4
.EQU  WWDG_CFR_WDGTB_DIV8, 3<<7                    @ 11: CK Counter Clock (PCLK1 div 4096) div 8
.EQU  WWDG_CFR_W_N   , 0                           @ Bits 6:0  W[6:0]: 7-bit window value

@.ITEM  WWDG_SR
.EQU  WWDG_SR_EWIF   , 1                           @ Bit 0 EWIF: Early wakeup interrupt flag



