@.CHARSET =CP1251 ( Cyrillic )
@GNU AS

@ +---------------------------------------------------------------+
@ |                      Определения IWDG                         |
@ |                          STM32L100                            |
@ +---------------------------------------------------------------+


.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  IWDG_BASE      , APB1PERIPH_BASE + 0x3000
.EQU  IWDG           , PERIPH_BASE + IWDG_BASE
@.END

@.ITEM     IWDG IWDG_BASE
.EQU  IWDG_KR        , 0x00                        @ Key register (IWDG_KR)
.EQU  IWDG_PR        , 0x04                        @ Prescaler register (IWDG_PR)
.EQU  IWDG_RLR       , 0x08                        @ Reload register (IWDG_RLR)
.EQU  IWDG_SR        , 0X0C                        @ Status register (IWDG_SR)
@.END

@.ITEM IWDG_PR
.EQU  IWDG_PR_PR_N   , 0            @ Bits 2:0 PR[2:0]: Prescaler divider
                                    @ These bits are write access protected seeSection 21.3.2. They are written by software to
                                    @ select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in
                                    @ order to be able to change the prescaler divider.
.EQU  IWDG_PR_PR_DIV4, 0            @ 000: divider /4
.EQU  IWDG_PR_PR_DIV8, 1            @ 001: divider /8
.EQU  IWDG_PR_PR_DIV16, 2           @ 010: divider /16
.EQU  IWDG_PR_PR_DIV32, 3           @ 011: divider /32
.EQU  IWDG_PR_PR_DIV64, 4           @ 100: divider /64
.EQU  IWDG_PR_PR_DIV128, 5          @ 101: divider /128
.EQU  IWDG_PR_PR_DIV256, 6          @ 110: divider /256
.EQU  IWDG_PR_PR_DIV256, 7          @ 111: divider /256
                              @ Note: Reading this register returns the prescaler value from the VDD voltage domain. This
                                    @ value may not be up to date/valid if a write operation to this register is ongoing. For this
                                    @ reason the value read from this register is valid only when the PVU bit in the IWDG_SR
                                    @ register is reset.
@.END

@.ITEM IWDG_RLR
.EQU  IWDG_RLR_RL_RSTVAL, 0x0FFF    @ Reset value: 0x0000 0FFF (reset by Standby mode)
@.END

@.ITEM IWDG_SR
.EQU  IWDG_SR_RVU    , 1 << 1       @ Bit  1 RVU: Watchdog counter reload value update
                                    @ This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
                                    @ by hardware when the reload value update operation is completed in the VDD voltage domain
                                    @ (takes up to 5 RC 40 kHz cycles).
                                    @ Reload value can be updated only when RVU bit is reset.
.EQU  IWDG_SR_PVU    , 1            @ Bit 0 PVU: Watchdog prescaler value update
                                    @ This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
                                    @ reset by hardware when the prescaler update operation is completed in the VDD voltage
                                    @ domain (takes up to 5 RC 40 kHz cycles).
                                    @ Prescaler value can be updated only when PVU bit is reset.
@.END



