@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Îïðåäåëåíèÿ òàéìåðîâ TIM6 - TIM7             |
@ |                              STM32FL100                          |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  TIM6_BASE          , APBPERIPH_BASE + 0x1000
.EQU  TIM7_BASE          , APBPERIPH_BASE + 0x1400
.EQU  TIM6               , PERIPH_BASE + TIM6_BASE
.EQU  TIM7               , PERIPH_BASE + TIM7_BASE
@.end


@.ITEM     TIM6_BASE TIM7_BASE TIM6 TIM7
.EQU  TIM6T7_CR1         , 0x00      @ TIM6/TIM7 control register 1 (TIMx_CR1)
.EQU  TIM6T7_CR2         , 0x04      @ TIM6/TIM7 control register 2 (TIMx_CR2)
.EQU  TIM6T7_DIER        , 0x0C      @ TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
.EQU  TIM6T7_SR          , 0x10      @ TIM6/TIM7 status register (TIMx_SR)
.EQU  TIM6T7_EGR         , 0x14      @ TIM6/TIM7 event generation register (TIMx_EGR)
.EQU  TIM6T7_CNT         , 0x24      @ TIM6/TIM7 counter (TIMx_CNT)
.EQU  TIM6T7_PSC         , 0x28      @ TIM6/TIM7 prescaler (TIMx_PSC)
.EQU  TIM6T7_ARR         , 0x2C      @ TIM6/TIM7 auto-reload register (TIMx_ARR)


@.ITEM     TIM6T7_CR1
.EQU  TIM6T7_CR1_APRE    , 1 << 7     @ Bit 7 ARPE: Auto-reload preload enable
                                      @ 0: TIMx_ARR register is not buffered.
                                      @ 1: TIMx_ARR register is buffered.
.EQU  TIM6T7_CR1_OPM     , 1 << 3     @ Bit 3 OPM: One-pulse mode
                                      @ 0: Counter is not stopped at update event
                                      @ 1: Counter stops counting at the next update event (clearing the CEN bit).
.EQU  TIM6T7_CR1_URS     , 1 << 2     @ Bit 2 URS: Update request source
                                      @ This bit is set and cleared by software to select the UEV event sources.
                                      @ 0: Any of the following events generates an update interrupt or DMA request if enabled.
                                      @ These events can be:
                                      @ – Counter overflow/underflow
                                      @ – Setting the UG bit
                                      @ – Update generation through the slave mode controller
                                      @ 1: Only counter overflow/underflow generates an update interrupt or DMA request if
                                      @ enabled.
.EQU  TIM6T7_CR1_UDIS    , 1 << 1     @ Bit 1 UDIS: Update disable
                                      @ This bit is set and cleared by software to enable/disable UEV event generation.
                                      @ 0: UEV enabled. The Update (UEV) event is generated by one of the following events:
                                      @ – Counter overflow/underflow
                                      @ – Setting the UG bit
                                      @ – Update generation through the slave mode controller
                                      @ Buffered registers are then loaded with their preload values.
                                      @ 1: UEV disabled. The Update event is not generated, shadow registers keep their value
                                      @ (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
                                      @ a hardware reset is received from the slave mode controller.
.EQU  TIM6T7_CR1_CEN     , 1          @ Bit 0 CEN: Counter enable
                                      @ 0: Counter disabled
                                      @ 1: Counter enabled
                                      @ Note: Gated mode can work only if the CEN bit has been previously set by software.
                                      @ However trigger mode can set the CEN bit automatically by hardware.
                                      @ CEN is cleared automatically in one-pulse mode, when an update event occurs.
@.end

@.ITEM     TIM6T7_CR2
.EQU  TIM6T7_CR2_MMS_N    , 4         @ Bits 6:4 MMS[1:0]: Master mode selection
                                      @ These bits allow to select the information to be sent in master mode to slave timers for
                                      @ synchronization (TRGO). The combination is as follows:
.EQU  TIM6T7_CR2_MMS_RESET, 0         @ 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
                                      @ reset is generated by the trigger input (slave mode controller configured in reset mode) then
                                      @ the signal on TRGO is delayed compared to the actual reset.
.EQU  TIM6T7_CR2_MMS_ENABLE, 1 << 4   @ 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
                                      @ useful to start several timers at the same time or to control a window in which a slave timer is
                                      @ enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
                                      @ the trigger input when configured in gated mode. When the Counter Enable signal is
                                      @ controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
                                      @ selected (see the MSM bit description in TIMx_SMCR register).
.EQU  TIM6T7_CR2_MMS_UPDATE, 2 << 4   @  010: Update - The update event is selected as trigger output (TRGO). For instance a master
                                      @ timer can then be used as a prescaler for a slave timer.
                                @ Note: The clock of the slave timer and ADC must be enabled prior to receiving events from
                                      @ the master timer, and must not be changed on-the-fly while triggers are received from
                                      @ the master timer
@.end

@.ITEM     TIM6T7_DIER
.EQU  TIM6T7_DIER_UDE    , 1 << 8     @ Bit 8 UDE: Update DMA request enable
                                      @ 0: Update DMA request disabled.
                                      @ 1: Update DMA request enabled.
.EQU  TIM6T7_DIER_UIE    , 1          @ Bit 0 UIE: Update interrupt enable
                                      @ 0: Update interrupt disabled.
                                      @ 1: Update interrupt enabled.
@.end

@.ITEM     TIM6T7_SR
.EQU  TIM6T7_SR_UIF      , 1          @  Bit 0 UIF: Update interrupt flag
                                      @ This bit is set by hardware on an update event. It is cleared by software.
                                      @ 0: No update occurred.
                                      @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                      @ –At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
                                      @ TIMx_CR1 register.
                                      @ –When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if
                                      @ URS = 0 and UDIS = 0 in the TIMx_CR1 register.
@.end

@.ITEM     TIM6T7_EGR
.EQU  TIM6T7_EGR_UG      , 1          @ Bit 0 UG: Update generation
                                      @ This bit can be set by software, it is automatically cleared by hardware.
                                      @ 0: No action.
                                      @ 1: Re-initializes the timer counter and generates an update of the registers. Note that the
                                      @ prescaler counter is cleared too (but the prescaler ratio is not affected).
@.end



