@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"
@.ITEM     APB1PERIPH_BASE
.EQU  DAC_BASE       , APB1PERIPH_BASE + 0x7400
.EQU  DAC            , PERIPH_BASE + DAC_BASE

@.ITEM     DAC DAC_BASE
.EQU  DAC_CR         , 0x00                        @ ADC status register (ADC_SR)
.EQU  DAC_SWTRIGR    , 0x04                        @ ADC control register 1 (ADC_CR1)
.EQU  DAC_DHR12R1    , 0x08                        @ ADC control register 2 (ADC_CR2)
.EQU  DAC_DHR12L1    , 0X0C                        @ ADC sample time register 1 (ADC_SMPR1)
.EQU  DAC_DHR8R1     , 0X10                        @ ADC sample time register 2 (ADC_SMPR2)
.EQU  DAC_DHR12R2    , 0X14                        @ ADC injected channel 1 data offset register  (ADC_JOFRx)
.EQU  DAC_DHR12L2    , 0X18                        @ ADC injected channel 2 data offset register  (ADC_JOFRx)
.EQU  DAC_DHR8R2     , 0X1C                        @ ADC injected channel 3 data offset register  (ADC_JOFRx)
.EQU  DAC_DHR12RD    , 0X20                        @ ADC injected channel 4 data offset register  (ADC_JOFRx)
.EQU  DAC_DHR12LD    , 0X24                        @ ADC watchdog high threshold register (ADC_HTR)
.EQU  DAC_DHR8RD     , 0X28                        @ ADC watchdog low threshold register (ADC_LTR)
.EQU  DAC_DOR1       , 0X2C                        @ ADC regular sequence register 1 (ADC_SQR1)
.EQU  DAC_DOR2       , 0X30                        @ ADC regular sequence register 2 (ADC_SQR2)
.EQU  DAC_SR         , 0X34                        @ ADC r egular sequence register 3 (ADC_SQR3)


@.ITEM     DAC_CR
.EQU  DAC_CR_DMAUDRIE2, 1 << 29                    @ Bits 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
.EQU  DAC_CR_DMAEN2  , 1 << 28                     @ Bit 28 DMAEN2: DAC channel2 DMA enable
.EQU  DAC_CR_MAMP2_N , 24                          @ Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector
.EQU  DAC_CR_MAMP_TRIAN1, 0                        @ 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
.EQU  DAC_CR_MAMP_TRIAN3, 1                        @ 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
.EQU  DAC_CR_MAMP_TRIAN7, 2                        @ 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
.EQU  DAC_CR_MAMP_TRIAN15, 3                       @ 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
.EQU  DAC_CR_MAMP_TRIAN31, 4                       @ 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
.EQU  DAC_CR_MAMP_TRIAN63, 5                       @ 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
.EQU  DAC_CR_MAMP_TRIAN127, 6                      @ 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
.EQU  DAC_CR_MAMP_TRIAN255, 7                      @ 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
.EQU  DAC_CR_MAMP_TRIAN511, 8                      @ 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
.EQU  DAC_CR_MAMP_TRIAN1023, 9                     @ 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
.EQU  DAC_CR_MAMP_TRIAN2047, 10                    @ 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
.EQU  DAC_CR_MAMP_TRIAN4095, 11                    @  1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
.EQU  DAC_CR_WAVE2_N , 22                          @ Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
.EQU  DAC_CR_WAVE_DIS, 0                           @ 00: wave generation disabled
.EQU  DAC_CR_WAVE_NOISE_EN, 1                      @ 01: Noise wave generation enabled
.EQU  DAC_CR_WAVE_TRIA_EN, 2                       @ 1x: Triangle wave generation enabled
.EQU  DAC_CR_TSEL2_N , 19                          @ Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection
.EQU  DAC_CR_TSEL_T6TRGO, 0                        @ 000: Timer 6 TRGO event
.EQU  DAC_CR_TSEL_T3TRGO, 1                        @ 001: Timer 3 TRGO event
.EQU  DAC_CR_TSEL_T7TRGO, 2                        @ 010: Timer 7 TRGO event
.EQU  DAC_CR_TSEL_T5_15TRGO, 3                     @ 011: Timer 5 or timer 15 TRGO event
.EQU  DAC_CR_TSEL_T2TRGO, 4                        @ 100: Timer 2 TRGO event
.EQU  DAC_CR_TSEL_T4TRGO, 5                        @ 101: Timer 4 TRGO event
.EQU  DAC_CR_TSEL_EXTI9, 6                         @ 110: External line9
.EQU  DAC_CR_TSEL_SOFT, 7                          @ 111: Software trigger
.EQU  DAC_CR_TEN2    , 1 << 18                     @ Bit 18 TEN2: DAC channel2 trigger enable
.EQU  DAC_CR_BOFF2   , 1 << 17                     @ Bit 17 BOFF2: DAC channel2 output buffer disable
.EQU  DAC_CR_EN2     , 1 << 16                     @ Bit 16 EN2: DAC channel2 enable
.EQU  DAC_CR_DMAUDRIE, 1 << 13                     @ Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
.EQU  DAC_CR_DMAEN1  , 1 << 12                     @ Bit 12 DMAEN1: DAC channel1 DMA enable
.EQU  DAC_CR_MAMP1_N , 8                           @ Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
.EQU  DAC_CR_WAVE1_N , 6                           @ Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
.EQU  DAC_CR_TSEL1_N , 3                           @ Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
.EQU  DAC_CR_TEN1    , 1 << 2                      @ Bit 2 TEN1: DAC channel1 trigger enable
.EQU  DAC_CR_BOFF1   , 1 << 1                      @ Bit 1 BOFF1: DAC channel1 output buffer disable
.EQU  DAC_CR_EN1     , 1                           @ Bit 0 EN1: DAC channel1 enable

@.ITEM     DAC_SWTRIGR
.EQU  DAC_SWTRIGR_SWTRIG2, 1 << 1                  @ Bit 1 SWTRIG2: DAC channel2 software trigger
.EQU  DAC_SWTRIGR_SWTRIG1, 1                       @ Bit 0 SWTRIG1: DAC channel1 software trigger

@.ITEM     DAC_DHR12R1
.EQU  DAC_DHR12R1_DACC1DHR_N, 0
.EQU  DAC_DHR12R1_DACC1DHR_M, 0X0FFF               @ Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data

@.ITEM     DAC_DHR12L1
.EQU  DAC_DHR12L1_DACC1DHR_N, 4
.EQU  DAC_DHR12L1_DACC1DHR_M, 0XFFF0               @ Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data

@.ITEM     DAC_DHR8R1
.EQU  DAC_DHR8R1_DACC1DHR_N, 0
.EQU  DAC_DHR8R1_DACC1DHR_M, 0X0FF                 @ Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data

@.ITEM     DAC_DHR12R2
.EQU  DAC_DHR12R2_DACC2DHR_N, 0
.EQU  DAC_DHR12R2_DACC2DHR_M, 0X0FFF               @ Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data

@.ITEM     DAC_DHR12L2
.EQU  DAC_DHR12L2_DACC2DHR_N, 4
.EQU  DAC_DHR12L2_DACC2DHR_M, 0XFFF0               @ Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data

@.ITEM     DAC_DHR8R2
.EQU  DAC_DHR8R2_DACC2DHR_N, 0
.EQU  DAC_DHR8R2_DACC2DHR_M, 0X0FF                 @ Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data

@.ITEM     DAC_DHR12RD
.EQU  DAC_DHR12RD_DACC2DHR_N, 16
.EQU  DAC_DHR12RD_DACC2DHR, 0X0FFF0000             @ Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
.EQU  DAC_DHR12RD_DACC1DHR_N, 0
.EQU  DAC_DHR12RD_DACC1DHR, 0X0FFF                 @ Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data

@.ITEM     DAC_DHR12LD
.EQU  DAC_DHR12LD_DACC2DHR_N, 20
.EQU  DAC_DHR12LD_DACC2DHR, 0XFFF00000             @ Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
.EQU  DAC_DHR12LD_DACC1DHR_N, 4
.EQU  DAC_DHR12LD_DACC1DHR, 0XFFF0                 @ Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data

@.ITEM     DAC_DHR8RD
.EQU  DAC_DHR8RD_DACC2DHR_N, 8
.EQU  DAC_DHR8RLD_DACC2DHR, 0XFF000                @ Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
.EQU  DAC_DHR8RLD_DACC1DHR_N, 0
.EQU  DAC_DHR8RLD_DACC1DHR, 0X00FF                 @ Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data

@.ITEM     DAC_DOR1
.EQU  DAC_DOR1_DACC1DOR_N, 0
.EQU  DAC_DOR1_DACC1DOR_M, 0X0FFF                  @ Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output

@.ITEM     DAC_DOR2
.EQU  DAC_DOR2_DACC2DOR_N, 0
.EQU  DAC_DOR2_DACC2DOR_M, 0X0FFF                  @ Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output

@.ITEM     DAC_SR
.EQU  DAC_SR_DMAUDR2 , 1 << 29                     @ Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
.EQU  DAC_SR_DMAUDR1 , 1 << 13                     @ Bit 13 DMAUDR1: DAC channel1 DMA underrun flag



