@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Αΰηξβϋε κξνρςΰνςϋ TIM3                       |
@ |                            STM32F0x0                             |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APBPERIPH_BASE
.EQU  TIM3_BASE          , APB1PERIPH_BASE + 0x400
.EQU  TIM3               , PERIPH_BASE + APB1PERIPH_BASE + 0x400
@.end

@.ITEM     TIM3_BASE
.EQU  TIM3_CR1         , 0x00      @ TIM3 control register 1 (TIM3_CR1)
.EQU  TIM3_CR2         , 0x04      @ TIM3 control register 2 (TIM3_CR2)
.EQU  TIM3_SMCR        , 0x08      @ TIM3 slave mode control register (TIM3_SMCR)
.EQU  TIM3_DIER        , 0x0C      @ TIM3 DMA/Interrupt enable register (TIM3_DIER)
.EQU  TIM3_SR          , 0x10      @ TIM3 status register (TIM3_SR)
.EQU  TIM3_EGR         , 0x14      @ TIM3 event generation register (TIM3_EGR)
.EQU  TIM3_CCMR1       , 0x18      @ TIM3 capture/compare mode register 1 (TIM3_CCMR1)
.EQU  TIM3_CCMR2       , 0x1C      @ TIM3 capture/compare mode register 2 (TIM3_CCMR2)
.EQU  TIM3_CCER        , 0x20      @ TIM3 capture/compare enable register (TIM3_CCER)
.EQU  TIM3_CNT         , 0x24      @ TIM3 counter (TIM3_CNT)
.EQU  TIM3_PSC         , 0x28      @ TIM3 prescaler (TIM3_PSC)
.EQU  TIM3_ARR         , 0x2C      @ TIM3 auto-reload register (TIM3_ARR)
.EQU  TIM3_CCR1        , 0x34      @ TIM3 capture/compare register 1 (TIM3_CCR1)
.EQU  TIM3_CCR2        , 0x38      @ TIM3 capture/compare register 2 (TIM3_CCR2)
.EQU  TIM3_CCR3        , 0x3C      @ TIM3 capture/compare register 3 (TIM3_CCR3)
.EQU  TIM3_CCR4        , 0x40      @ TIM3 capture/compare register 4 (TIM3_CCR4)
.EQU  TIM3_DCR         , 0x48      @ TIM3 DMA control register (TIM3_DCR)
.EQU  TIM3_DMAR        , 0x4C      @ TIM3 DMA address for full transfer (TIM3_DMAR)
@.end

@.ITEM     TIM3_CR1
.EQU  TIM3_CR1_CKD_N    , 8           @ Bits 9:8 CKD[1:0]: Clock division
                                      @ This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
                                      @ dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
                                      @ (ETR, TIx),
.EQU  TIM3_CR1_CKD_CK   , 0           @ 00: tDTS=tCK_INT
.EQU  TIM3_CR1_CKD_2CK  , 1 << 8      @ 01: tDTS=2*tCK_INT
.EQU  TIM3_CR1_CKD_4CK  , 2 << 8      @ 10: tDTS=4*tCK_INT
.EQU  TIM3_CR1_ARPE     , 1 << 7      @ Bit 7 ARPE: Auto-reload preload enable
                                      @ 0: TIMx_ARR register is not buffered
                                      @ 1: TIMx_ARR register is buffered
.EQU  TIM3_CR1_CMS_N    , 5           @ Bits 6:5 CMS[1:0]: Center-aligned mode selection
.EQU  TIM3_CR1_CMS_EDGE     , 0       @ 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
.EQU  TIM3_CR1_CMS_CENTER1  , 1 << 5  @ 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
                                      @ interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
                                      @ only when the counter is counting down.
.EQU  TIM3_CR1_CMS_CENTER2  , 2 << 5  @ 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
                                      @ interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
                                      @ only when the counter is counting up.
.EQU  TIM3_CR1_CMS_CENTER3  , 3 << 5  @ 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
                                      @ interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
                                      @ both when the counter is counting up or down.
                                @ Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
                                      @ the counter is enabled (CEN=1).
.EQU  TIM3_CR1_DIR      , 1 << 4      @ Bit 4 DIR: Direction
                                      @ 0: Counter used as upcounter
                                      @ 1: Counter used as downcounter
                                @ Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
                                      @ mode.
.EQU  TIM3_CR1_OPM      , 1 << 3      @ Bit 3 OPM: One pulse mode
                                      @ 0: Counter is not stopped at update event
                                      @ 1: Counter stops counting at the next update event (clearing the bit CEN)
.EQU  TIM3_CR1_URS      , 1 << 2      @ Bit 2 URS: Update request source
                                      @ This bit is set and cleared by software to select the UEV event sources.
                                      @ 0: Any of the following events generate an update interrupt or DMA request if enabled.
                                      @ These events can be:
                                      @  Counter overflow/underflow
                                      @  Setting the UG bit
                                      @  Update generation through the slave mode controller
                                      @ 1: Only counter overflow/underflow generates an update interrupt or DMA request if
                                      @ enabled.
.EQU  TIM3_CR1_UDIS     , 1 << 1      @ Bit 1 UDIS: Update disable
                                      @ This bit is set and cleared by software to enable/disable UEV event generation.
                                      @ 0: UEV enabled. The Update (UEV) event is generated by one of the following events:
                                      @  Counter overflow/underflow
                                      @  Setting the UG bit
                                      @  Update generation through the slave mode controller
                                      @ Buffered registers are then loaded with their preload values.
                                      @ 1: UEV disabled. The Update event is not generated, shadow registers keep their value
                                      @ (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
                                      @ set or if a hardware reset is received from the slave mode controller.
.EQU  TIM3_CR1_CEN      , 1           @ Bit 0 CEN: Counter enable
                                      @ 0: Counter disabled
                                      @ 1: Counter enabled
                                @ Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
                                      @ previously set by software. However trigger mode can set the CEN bit automatically by
                                      @ hardware.
                                      @ CEN is cleared automatically in one-pulse mode, when an update event occurs
@.end

@.ITEM     TIM3_CR2
.EQU  TIM3_CR2_TI1S     , 1 << 7      @ Bit 7 TI1S: TI1 selection
                                      @ 0: The TIMx_CH1 pin is connected to TI1 input
                                      @ 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
.EQU  TIM3_CR2_MMS_N    , 4           @ Bits 6:4 MMS[1:0]: Master mode selection
                                      @ These bits allow to select the information to be sent in master mode to slave timers for
                                      @ synchronization (TRGO). The combination is as follows:
.EQU  TIM3_CR2_MMS_RESET, 0           @ 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
                                      @ reset is generated by the trigger input (slave mode controller configured in reset mode) then
                                      @ the signal on TRGO is delayed compared to the actual reset.
.EQU  TIM3_CR2_MMS_ENABLE, 1 << 4     @ 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is
                                      @ useful to start several timers at the same time or to control a window in which a slave timer is
                                      @ enable. The Counter Enable signal is generated by a logic OR between CEN control bit and
                                      @ the trigger input when configured in gated mode. When the Counter Enable signal is
                                      @ controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is
                                      @ selected (see the MSM bit description in TIMx_SMCR register).
.EQU  TIM3_CR2_MMS_UPDATE, 2 << 4     @  010: Update - The update event is selected as trigger output (TRGO). For instance a master
                                      @ timer can then be used as a prescaler for a slave timer.
.EQU  TIM3_CR2_MMS_COMPARE, 3 << 4    @ 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
                                      @ set (even if it was already high), as soon as a capture or a compare match occurred.
                                      @ (TRGO).
.EQU  TIM3_CR2_MMS_OC1REF, 4 << 4     @ 100: Compare - OC1REF signal is used as trigger output (TRGO)
.EQU  TIM3_CR2_MMS_OC2REF, 5 << 4     @ 101: Compare - OC2REF signal is used as trigger output (TRGO)
.EQU  TIM3_CR2_MMS_OC3REF, 6 << 4     @ 110: Compare - OC3REF signal is used as trigger output (TRGO)
.EQU  TIM3_CR2_MMS_OC4REF, 7 << 4     @ 111: Compare - OC4REF signal is used as trigger output (TRGO)
.EQU  TIM3_CR2_CCDS     , 1 << 3      @ Bit 3 CCDS: Capture/compare DMA selection
                                      @ 0: CCx DMA request sent when CCx event occurs
                                      @ 1: CCx DMA requests sent when update event occurs
@.end

@.ITEM     TIM3_SMCR
.EQU  TIM3_SMCR_ETP     , 1 << 15     @ Bit 15 ETP: External trigger polarity
                                      @ This bit selects whether ETR or ETR is used for trigger operations
                                      @ 0: ETR is non-inverted, active at high level or rising edge.
                                      @ 1: ETR is inverted, active at low level or falling edge.
.EQU  TIM3_SMCR_ECE     , 1 << 14     @ Bit 14 ECE: External clock enable
                                      @ This bit enables External clock mode 2.
                                      @ 0: External clock mode 2 disabled
                                      @ 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
                                      @ signal.
                                      @ Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
                                      @ TRGI connected to ETRF (SMS=111 and TS=111).
                                      @ 2: It is possible to simultaneously use external clock mode 2 with the following slave
                                      @ modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
                                      @ connected to ETRF in this case (TS bits must not be 111).
                                      @ 3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
                                      @ the external clock input is ETRF
.EQU  TIM3_SMCR_ETPS_N  , 12          @ Bits 13:12 ETPS[1:0]: External trigger prescaler
                                      @ External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
                                      @ prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
                                      @ clocks.
.EQU  TIM3_SMCR_ETPS_PROFF, 0         @ 00: Prescaler OFF
.EQU  TIM3_SMCR_ETPS_DIV2, 1 << 12    @ 01: ETRP frequency divided by 2
.EQU  TIM3_SMCR_ETPS_DIV4, 2 << 12    @ 10: ETRP frequency divided by 4
.EQU  TIM3_SMCR_ETPS_DIV8, 3 << 12    @ 11: ETRP frequency divided by 8
.EQU  TIM3_SMCR_ETF_N   , 8           @ Bits 11:8 ETF[3:0]: External trigger filter
                                      @ This bit-field then defines the frequency used to sample ETRP signal and the length of the
                                      @ digital filter applied to ETRP. The digital filter is made of an event counter in which N
                                      @ consecutive events are needed to validate a transition on the output:
.EQU  TIM3_SMCR_ETF_NOF , 0           @ 0000: No filter, sampling is done at fDTS
.EQU  TIM3_SMCR_ETF_N2  , 1 << 8      @ 0001: fSAMPLING = fCK_INT, N = 2
.EQU  TIM3_SMCR_ETF_N4  , 2 << 8      @ 0010: fSAMPLING = fCK_INT, N = 4
.EQU  TIM3_SMCR_ETF_N8  , 3 << 8      @ 0011: fSAMPLING = fCK_INT, N = 8
.EQU  TIM3_SMCR_ETF_2N6 , 4 << 8      @ 0100: fSAMPLING = fDTS / 2, N = 6
.EQU  TIM3_SMCR_ETF_2N8 , 5 << 8      @ 0101: fSAMPLING = fDTS / 2, N = 8
.EQU  TIM3_SMCR_ETF_4N6 , 6 << 8      @ 0110: fSAMPLING = fDTS / 4, N = 6
.EQU  TIM3_SMCR_ETF_4N8 , 7 << 8      @ 0111: fSAMPLING = fDTS / 4, N = 8
.EQU  TIM3_SMCR_ETF_8N6 , 8 << 8      @ 1000: fSAMPLING = fDTS / 8, N = 6
.EQU  TIM3_SMCR_ETF_8N8 , 9 << 8      @ 1001: fSAMPLING = fDTS / 8, N = 8
.EQU  TIM3_SMCR_ETF_16N5, 10 << 8     @ 1010: fSAMPLING = fDTS / 16, N = 5
.EQU  TIM3_SMCR_ETF_16N6, 11 << 8     @ 1011: fSAMPLING = fDTS / 16, N = 6
.EQU  TIM3_SMCR_ETF_16N8, 12 << 8     @ 1100: fSAMPLING = fDTS / 16, N = 8
.EQU  TIM3_SMCR_ETF_32N5, 13 << 8     @ 1101: fSAMPLING = fDTS / 32, N = 5
.EQU  TIM3_SMCR_ETF_32N6, 14 << 8     @ 1110: fSAMPLING = fDTS / 32, N = 6
.EQU  TIM3_SMCR_ETF_32N8, 15 << 8     @ 1111: fSAMPLING = fDTS / 32, N = 8
                                @ Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ETF[3:0] = 1,
                                      @ 2 or 3.
.EQU  TIM3_SMCR_MSM     , 1 << 7      @ Bit 7 MSM: Master/slave mode
                                      @ 0: No action
                                      @ 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
                                      @ synchronization between the current timer and its slaves (through TRGO). It is useful if we
                                      @ want to synchronize several timers on a single external event.
.EQU  TIM3_SMCR_TS_N    , 4           @ Bits 6:4 TS[2:0]: Trigger selection
                                      @ This bit-field selects the trigger input to be used to synchronize the counter
.EQU  TIM3_SMCR_TS_ITR0 , 0           @ 000: Internal Trigger 0 (ITR0)
.EQU  TIM3_SMCR_TS_ITR1 , 1 << 4      @ 001: Internal Trigger 1 (ITR1)
.EQU  TIM3_SMCR_TS_ITR2 , 2 << 4      @ 010: Internal Trigger 2 (ITR2)
.EQU  TIM3_SMCR_TS_ITR3 , 3 << 4      @ 011: Internal Trigger 3 (ITR3)
.EQU  TIM3_SMCR_TS_TI1F_ED, 4 << 4    @ 100: TI1 Edge Detector (TI1F_ED)
.EQU  TIM3_SMCR_TS_TI1FP1, 5 << 4     @ 101: Filtered Timer Input 1 (TI1FP1)
.EQU  TIM3_SMCR_TS_TI2FP2, 6 << 4     @ 110: Filtered Timer Input 2 (TI2FP2)
.EQU  TIM3_SMCR_TS_ETRF , 7 << 4      @ 111: External Trigger input (ETRF)
                                      @ See Table 45: TIMx Internal trigger connection on page 273 for more details on ITRx meaning
                                      @ for each Timer.
                                      @ Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
                                      @ avoid wrong edge detections at the transition.
@ Table 49. TIMx Internal trigger connection
@ +-------+---------------------+-----------------+-----------------+
@ | Slave | TIM ITR0 (TS = 000) | ITR2 (TS = 010) | ITR3 (TS = 011) |
@ +-------+---------------------+-----------------+-----------------+
@ |  TIM3 |     TIM1            |       TIM15     |    TIM14        |
@ +-------+---------------------+-----------------+-----------------+
.EQU  TIM3_SMCR_OCCS, 1 << 3          @ Bit 3 OCCS: OCREF clear selection.
                                      @ This bit is used to select the OCREF clear source.
                                      @ 0:OCREF_CLR_INT is connected to the OCREF_CLR input
                                      @ 1: OCREF_CLR_INT is connected to ETRF
.EQU  TIM3_SMCR_SMS_N   , 0           @ Bits 2:0 SMS: Slave mode selection
                                      @ When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
                                      @ polarity selected on the external input (see Input Control register and Control Register
                                      @ description.
.EQU  TIM3_SMCR_SMS_SMD , 0           @ 000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock.
.EQU  TIM3_SMCR_SMS_ENCM1, 1          @ 001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
.EQU  TIM3_SMCR_SMS_ENCM2, 2          @ 010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
.EQU  TIM3_SMCR_SMS_ENCM3, 3          @ 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
                                      @ depending on the level of the other input.
.EQU  TIM3_SMCR_SMS_RSTM, 4           @ 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
                                      @ and generates an update of the registers
.EQU  TIM3_SMCR_SMS_GTDM, 5           @ 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
                                      @ counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
                                      @ the counter are controlled.
.EQU  TIM3_SMCR_SMS_TRIGM, 6          @ 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
                                      @ reset). Only the start of the counter is controlled.
.EQU  TIM3_SMCR_SMS_EXTCLK, 7         @ 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
                                      @ Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
                                      @ (TS=100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
                                      @ gated mode checks the level of the trigger signal.
                                      @ Note: The clock of the slave timer must be enabled prior to receive events from the master
                                      @ timer, and must not be changed on-the-fly while triggers are received from the master
                                      @ timer.
@.end


@.ITEM     TIM3_DIER
.EQU  TIM3_DIER_TDE     , 1 << 14     @ Bit 14 TDE: Trigger DMA request enable
                                      @ 0: Trigger DMA request disabled
                                      @ 1: Trigger DMA request enabled
.EQU  TIM3_DIER_CC4DE   , 1 << 12     @ Bit 12 CC4DE: Capture/Compare 4 DMA request enable
                                      @ 0: CC4 DMA request disabled
                                      @ 1: CC4 DMA request enabled
.EQU  TIM3_DIER_CC3DE   , 1 << 11     @ Bit 11 CC3DE: Capture/Compare 3 DMA request enable
                                      @ 0: CC3 DMA request disabled
                                      @ 1: CC3 DMA request enabled
.EQU  TIM3_DIER_CC2DE   , 1 << 10     @ Bit 10 CC2DE: Capture/Compare 2 DMA request enable
                                      @ 0: CC2 DMA request disabled
                                      @ 1: CC2 DMA request enabled
.EQU  TIM3_DIER_CC1DE   , 1 << 9      @ Bit 9 CC1DE: Capture/Compare 1 DMA request enable
                                      @ 0: CC1 DMA request disabled
                                      @ 1: CC1 DMA request enabled
.EQU  TIM3_DIER_UDE     , 1 << 8      @ Bit 8 UDE: Update DMA request enable
                                      @ 0: Update DMA request disabled
                                      @ 1: Update DMA request enabled
.EQU  TIM3_DIER_TIE     , 1 << 6      @ Bit 6 TIE: Trigger interrupt enable
                                      @ 0: Trigger interrupt disabled
                                      @ 1: Trigger interrupt enabled
.EQU  TIM3_DIER_CC4IE   , 1 << 4      @ Bit 4 CC4IE: Capture/Compare 4 interrupt enable
                                      @ 0: CC4 interrupt disabled
                                      @ 1: CC4 interrupt enabled
.EQU  TIM3_DIER_CC3IE   , 1 << 3      @ Bit 3 CC3IE: Capture/Compare 3 interrupt enable
                                      @ 0: CC3 interrupt disabled
                                      @ 1: CC3 interrupt enabled
.EQU  TIM3_DIER_CC2IE   , 1 << 2      @ Bit 2 CC2IE: Capture/Compare 2 interrupt enable
                                      @ 0: CC2 interrupt disabled
                                      @ 1: CC2 interrupt enabled
.EQU  TIM3_DIER_CC1IE   , 1 << 1      @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
                                      @ 0: CC1 interrupt disabled
                                      @ 1: CC1 interrupt enabled
.EQU  TIM3_DIER_UIE     , 1           @ Bit 0 UIE: Update interrupt enable
                                      @ 0: Update interrupt disabled
                                      @ 1: Update interrupt enabled
@.end

@.ITEM     TIM3_SR
.EQU  TIM3_SR_CC4OF     , 1 << 12     @ Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description
.EQU  TIM3_SR_CC3OF     , 1 << 11     @ Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description
.EQU  TIM3_SR_CC2OF     , 1 << 10     @ Bit 10 CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description
.EQU  TIM3_SR_CC1OF     , 1 << 9      @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
                                      @ This flag is set by hardware only when the corresponding channel is configured in input
                                      @ capture mode. It is cleared by software by writing it to 0.
                                      @ 0: No overcapture has been detected.
                                      @ 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
                                      @ already set
.EQU  TIM3_SR_TIF       , 1 << 6      @ Bit 6 TIF: Trigger interrupt flag
                                      @ This flag is set by hardware on trigger event (active edge detected on TRGI input when the
                                      @ slave mode controller is enabled in all modes but gated mode.It is cleared by software.
                                      @ 0: No trigger event occurred.
                                      @ 1: Trigger interrupt pending.
.EQU  TIM3_SR_CO4IF     , 1 << 4      @ Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description
.EQU  TIM3_SR_CO3IF     , 1 << 3      @ Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description
.EQU  TIM3_SR_CO2IF     , 1 << 2      @ Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description
.EQU  TIM3_SR_CO1IF     , 1 << 1      @ Bit 1 CC1IF: Capture/Compare 1 interrupt flag
                                      @ If channel CC1 is configured as output:
                                      @ This flag is set by hardware when the counter matches the compare value, with some
                                      @ exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
                                      @ It is cleared by software.
                                      @ 0: No match.
                                      @ 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
                                      @ When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
                                      @ bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
                                      @ underflow (in downcounting mode)
                                      @ If channel CC1 is configured as input:
                                      @ This bit is set by hardware on a capture. It is cleared by software or by reading the
                                      @ TIMx_CCR1 register.
                                      @ 0: No input capture occurred
                                      @ 1: The counter value has been captured in TIMx_CCR1 register (An edge has been
                                      @ detected on IC1 which matches the selected polarity)
.EQU  TIM3_SR_UIF        , 1          @ Bit 0 UIF: Update interrupt flag
                                      @ This bit is set by hardware on an update event. It is cleared by software.
                                      @ 0: No update occurred.
                                      @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                      @ At overflow or underflow regarding the repetition counter value (update if repetition
                                      @ counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
                                      @ When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
                                      @ and UDIS=0 in the TIMx_CR1 register.
                                      @ When CNT is reinitialized by a trigger event (refer to Section 13.4.3: TIM1 slave mode
                                      @ control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
@.end

@.ITEM     TIM3_EGR
.EQU  TIM3_EGR_TG       , 1 << 6       @ Bit 6 TG: Trigger generation
                                       @ This bit is set by software in order to generate an event, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
.EQU  TIM3_EGR_CC4G     , 1 << 4       @ Bit 4 CC4G: Capture/Compare 4 generation Refer to CC1G description
.EQU  TIM3_EGR_CC3G     , 1 << 3       @ Bit 3 CC3G: Capture/Compare 3 generation Refer to CC1G description
.EQU  TIM3_EGR_CC2G     , 1 << 2       @ Bit 2 CC2G: Capture/Compare 2 generation refer to CC1G description
.EQU  TIM3_EGR_CC1G     , 1 << 1       @ Bit 1 CC1G: Capture/Compare 1 generation
                                       @ This bit is set by software in order to generate an event, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: A capture/compare event is generated on channel 1:
                                       @ If channel CC1 is configured as output:
                                       @ CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
                                       @ If channel CC1 is configured as input:
                                       @ The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the
                                       @ corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF
                                       @ flag was already high.
.EQU  TIM3_EGR_UG       , 1            @ Bit 0 UG: Update generation
                                       @ This bit can be set by software, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
                                       @ counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
                                       @ the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
                                       @ value (TIMx_ARR) if DIR=1 (downcounting).
@.end

@.ITEM     TIM3_CCMR1
@
@  Output compare mode
@
.EQU  TIM3_CCMR1_OC2CE  , 1 << 15     @ Bit 15 OC2CE: Output Compare 2 clear enable
.EQU  TIM3_CCMR1_OC2M_N , 12          @ Bits 14:12 OC2M[2:0]: Output Compare 2 mode
.EQU  TIM3_CCMR1_OC2PE  , 1 << 11     @ Bit 11 OC2PE: Output Compare 2 preload enable
.EQU  TIM3_CCMR1_OC2FE  , 1 << 10     @ Bit 10 OC2FE: Output Compare 2 fast enable
.EQU  TIM3_CCMR1_CC2S_N , 1 << 8      @ Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
                                      @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM3_CCMR1_CC2S_OUT, 0          @ 00: CC2 channel is configured as output
.EQU  TIM3_CCMR1_CC2S_TI2, 1 << 8     @ 01: CC2 channel is configured as input, IC2 is mapped on TI2
.EQU  TIM3_CCMR1_CC2S_TI1, 2 << 8     @ 10: CC2 channel is configured as input, IC2 is mapped on TI1
.EQU  TIM3_CCMR1_CC2S_TRC, 3 << 8     @ 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
                                      @ an internal trigger input is selected through the TS bit (TIMx_SMCR register)
                                      @ Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
.EQU  TIM3_CCMR1_OC1CE  , 1 << 7      @ Bit 7 OC1CE: Output Compare 1 clear enable
                                      @ OC1CE: Output Compare 1 Clear Enable
                                      @ 0: OC1Ref is not affected by the ETRF Input
                                      @ 1: OC1Ref is cleared as soon as a High level is detected on ETRF input
.EQU  TIM3_CCMR1_OC1M_N , 4           @ Bits 6:4 OC1M: Output Compare 1 mode
                                      @ These bits define the behavior of the output reference signal OC1REF from which OC1 and
                                      @ OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
                                      @ CC1P and CC1NP bits.
.EQU  TIM3_CCMR1_OC1M_FROZEN, 0       @ 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
                                      @ counter TIMx_CNT has no effect on the outputs (this mode is used to generate a timing
                                      @ base).
.EQU  TIM3_CCMR1_OC1M_SET_CH1A, 1 <<4 @ 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
                                      @ TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM3_CCMR1_OC1M_SET_CH1I, 2 <<4 @ 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
                                      @ counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM3_CCMR1_OC1M_TOGGLE, 3 << 4  @ 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM3_CCMR1_OC1M_FORCE_INACT, 4<<4 @ 100: Force inactive level - OC1REF is forced low.
.EQU  TIM3_CCMR1_OC1M_FORCE_ACT, 5<<4 @ 101: Force active level - OC1REF is forced high.
.EQU  TIM3_CCMR1_OC1M_PWM1, 6 << 4    @ 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
                                      @ else inactive. In downcounting, channel 1 is inactive (OC1REF=0) as long as
                                      @ TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
.EQU  TIM3_CCMR1_OC1M_PWM2, 7 << 4    @ 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
                                      @ else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
                                      @ inactive.
                             @ Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
                                      @ (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
                                      @ output).
                                      @ 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
                                      @ comparison changes or when the output compare mode switches from frozen mode
                                      @ to PWM mode.
.EQU  TIM3_CCMR1_OC1PE  , 1 << 3      @ Bit 3 OC1PE: Output Compare 1 preload enable
                                      @ 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
                                      @ new value is taken in account immediately.
                                      @ 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
                                      @ register. TIMx_CCR1 preload value is loaded in the active register at each update event.
                             @ Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
                                      @ (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in
                                      @ output).
                                      @ 2: The PWM mode can be used without validating the preload register only in one
                                      @ pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
.EQU  TIM3_CCMR1_OC1FE  , 1 << 2      @ Bit 2 OC1FE: Output Compare 1 fast enable
                                      @ This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
                                      @ 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
                                      @ ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
                                      @ 5 clock cycles.
                                      @ 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
                                      @ set to the compare level independently from the result of the comparison. Delay to sample
                                      @ the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
                                      @ the channel is configured in PWM1 or PWM2 mode.
.EQU  TIM3_CCMR1_CC1S_N , 0           @ Bits 1:0 CC1S: Capture/Compare 1 selection
                                      @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM3_CCMR1_CC1S_OUT, 0          @ 00: CC1 channel is configured as output
.EQU  TIM3_CCMR1_CC1S_TI1, 1 << 0     @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM3_CCMR1_CC1S_TI2, 2 << 0     @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM3_CCMR1_CC1S_TRC, 3 << 0     @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
                                      @ an internal trigger input is selected through TS bit (TIMx_SMCR register)
                                @ Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
@
@  Input capture mode
@
.EQU  TIM3_CCMR1_IC2F_N , 12          @ Bits 15:12 IC2F: Input capture 2 filter
.EQU  TIM3_CCMR1_IC2PSC , 10          @ Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
.EQU  TIM3_CCMR1_IC1F_N , 4           @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
                                      @ This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to
                                      @ TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate
                                      @ a transition on the output:
.EQU  TIM3_CCMR1_IC1F_NOF, 0          @ 0000: No filter, sampling is done at fDTS
.EQU  TIM3_CCMR1_IC1F_N2, 1 << 4      @ 0001: fSAMPLING = fCK_INT, N = 2
.EQU  TIM3_CCMR1_IC1F_N4, 2 << 4      @ 0010: fSAMPLING = fCK_INT, N = 4
.EQU  TIM3_CCMR1_IC1F_N8, 3 << 4      @ 0011: fSAMPLING = fCK_INT, N = 8
.EQU  TIM3_CCMR1_IC1F_2N6, 4 << 4     @ 0100: fSAMPLING = fDTS / 2, N = 6
.EQU  TIM3_CCMR1_IC1F_2N8, 5 << 4     @ 0101: fSAMPLING = fDTS / 2, N = 8
.EQU  TIM3_CCMR1_IC1F_4N6, 6 << 4     @ 0110: fSAMPLING = fDTS / 4, N = 6
.EQU  TIM3_CCMR1_IC1F_4N8, 7 << 4     @ 0111: fSAMPLING = fDTS / 4, N = 8
.EQU  TIM3_CCMR1_IC1F_8N6, 8 << 4     @ 1000: fSAMPLING = fDTS / 8, N = 6
.EQU  TIM3_CCMR1_IC1F_8N8, 9 << 4     @ 1001: fSAMPLING = fDTS / 8, N = 8
.EQU  TIM3_CCMR1_IC1F_16N5, 10 << 4   @ 1010: fSAMPLING = fDTS / 16, N = 5
.EQU  TIM3_CCMR1_IC1F_16N6, 11 << 4   @ 1011: fSAMPLING = fDTS / 16, N = 6
.EQU  TIM3_CCMR1_IC1F_16N8, 12 << 4   @ 1100: fSAMPLING = fDTS / 16, N = 8
.EQU  TIM3_CCMR1_IC1F_32N5, 13 << 4   @ 1101: fSAMPLING = fDTS / 32, N = 5
.EQU  TIM3_CCMR1_IC1F_32N6, 14 << 4   @ 1110: fSAMPLING = fDTS / 32, N = 6
.EQU  TIM3_CCMR1_IC1F_32N8, 15 << 4   @ 1111: fSAMPLING = fDTS / 32, N = 8
                                @ Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3
.EQU  TIM3_CCMR1_IC1PSC_N, 2          @ Bits 3:2 IC1PSC: Input capture 1 prescaler
                                      @ This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
                                      @ The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
.EQU  TIM3_CCMR1_IC1PSC_1, 0          @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM3_CCMR1_IC1PSC_2, 1 << 2     @ 01: capture is done once every 2 events
.EQU  TIM3_CCMR1_IC1PSC_4, 2 << 2     @ 10: capture is done once every 4 events
.EQU  TIM3_CCMR1_IC1PSC_8, 3 << 2     @ 11: capture is done once every 8 events
.EQU  TIM3_CCMR1_CC1S_N , 0           @ Bits 1:0 CC1S: Capture/Compare 1 Selection
                                      @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM3_CCMR1_CC1S_OUT, 0          @ 00: CC1 channel is configured as output
.EQU  TIM3_CCMR1_CC1S_TI1, 1          @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM3_CCMR1_CC1S_TI2, 2          @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM3_CCMR1_CC1S_TRC, 3          @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an
                                      @ internal trigger input is selected through TS bit (TIMx_SMCR register)
                                      @ Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
@.END

@.ITEM     TIM3_CCMR2
@
@  Output compare mode
@
.EQU  TIM3_CCMR2_OC4CE  , 1 << 15     @ Bit 15 OC4CE: Output compare 4 clear enable
.EQU  TIM3_CCMR2_OC4M_N , 12          @ Bits 14:12 OC4M: Output compare 4 mode
.EQU  TIM3_CCMR2_OC4PE  , 1 << 11     @ Bit 11 OC4PE: Output compare 4 preload enable
.EQU  TIM3_CCMR2_OC4FE  , 1 << 10     @ Bit 10 OC4FE: Output compare 4 fast enable
.EQU  TIM3_CCMR2_CC4S_N , 1 << 8      @ Bits 9:8 CC4S: Capture/Compare 4 selection
                                      @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM3_CCMR2_CC4S_OUT, 0          @ 00: CC4 channel is configured as output
.EQU  TIM3_CCMR2_CC4S_TI1, 1 << 8     @ 01: CC4 channel is configured as input, IC4 is mapped on TI4
.EQU  TIM3_CCMR2_CC4S_TI2, 2 << 8     @ 10: CC4 channel is configured as input, IC4 is mapped on TI3
.EQU  TIM3_CCMR2_CC4S_TRC, 3 << 8     @ 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
                                      @ an internal trigger input is selected through TS bit (TIMx_SMCR register)
                                @ Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
.EQU  TIM3_CCMR2_OC3CE  , 1 << 7      @ Bit 7 OC3CE: Output compare 3 clear enable
.EQU  TIM3_CCMR2_OC3M_N , 4           @ Bits 6:4 OC3M: Output compare 3 mode
.EQU  TIM3_CCMR2_OC3PE  , 1 << 3      @ Bit 3 OC3PE: Output compare 3 preload enable
.EQU  TIM3_CCMR2_OC3FE  , 1 << 2      @ Bit 2 OC3FE: Output compare 3 fast enable
.EQU  TIM3_CCMR2_CC3S_N , 0           @ Bits 1:0 CC3S: Capture/Compare 3 selection
                                      @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM3_CCMR2_CC3S_OUT, 0          @ 00: CC3 channel is configured as output
.EQU  TIM3_CCMR2_CC3S_TI1, 1 << 0     @ 01: CC3 channel is configured as input, IC3 is mapped on TI3
.EQU  TIM3_CCMR2_CC3S_TI2, 2 << 0     @ 10: CC3 channel is configured as input, IC3 is mapped on TI4
.EQU  TIM3_CCMR2_CC3S_TRC, 3 << 0     @ 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
                                @ Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
@
@  Input capture mode
@
.EQU  TIM3_CCMR2_IC4F_N , 12          @ Bits 15:12 IC4F: Input capture 4 filter
.EQU  TIM3_CCMR2_IC4PSC , 10          @ Bits 11:10 IC4PSC: Input capture 4 prescaler
.EQU  TIM3_CCMR2_IC3F_N , 4           @ Bits 7:4 IC3F: Input capture 3 filter
.EQU  TIM3_CCMR1_IC3F_NOF, 0          @ 0000: No filter, sampling is done at fDTS
.EQU  TIM3_CCMR1_IC3F_N2, 1 << 4      @ 0001: fSAMPLING = fCK_INT, N = 2
.EQU  TIM3_CCMR1_IC3F_N4, 2 << 4      @ 0010: fSAMPLING = fCK_INT, N = 4
.EQU  TIM3_CCMR1_IC3F_N8, 3 << 4      @ 0011: fSAMPLING = fCK_INT, N = 8
.EQU  TIM3_CCMR1_IC3F_2N6, 4 << 4     @ 0100: fSAMPLING = fDTS / 2, N = 6
.EQU  TIM3_CCMR1_IC3F_2N8, 5 << 4     @ 0101: fSAMPLING = fDTS / 2, N = 8
.EQU  TIM3_CCMR1_IC3F_4N6, 6 << 4     @ 0110: fSAMPLING = fDTS / 4, N = 6
.EQU  TIM3_CCMR1_IC3F_4N8, 7 << 4     @ 0111: fSAMPLING = fDTS / 4, N = 8
.EQU  TIM3_CCMR1_IC3F_8N6, 8 << 4     @ 1000: fSAMPLING = fDTS / 8, N = 6
.EQU  TIM3_CCMR1_IC3F_8N8, 9 << 4     @ 1001: fSAMPLING = fDTS / 8, N = 8
.EQU  TIM3_CCMR1_IC3F_16N5, 10 << 4   @ 1010: fSAMPLING = fDTS / 16, N = 5
.EQU  TIM3_CCMR1_IC3F_16N6, 11 << 4   @ 1011: fSAMPLING = fDTS / 16, N = 6
.EQU  TIM3_CCMR1_IC3F_16N8, 12 << 4   @ 1100: fSAMPLING = fDTS / 16, N = 8
.EQU  TIM3_CCMR1_IC3F_32N5, 13 << 4   @ 1101: fSAMPLING = fDTS / 32, N = 5
.EQU  TIM3_CCMR1_IC3F_32N6, 14 << 4   @ 1110: fSAMPLING = fDTS / 32, N = 6
.EQU  TIM3_CCMR1_IC3F_32N8, 15 << 4   @ 1111: fSAMPLING = fDTS / 32, N = 8
                                @ Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3
.EQU  TIM3_CCMR2_IC3PSC_N, 2          @ Bits 3:2 IC3PSC: Input capture 3 prescaler
.EQU  TIM3_CCMR1_IC3PSC_1, 0          @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM3_CCMR1_IC3PSC_2, 1 << 2     @ 01: capture is done once every 2 events
.EQU  TIM3_CCMR1_IC3PSC_4, 2 << 2     @ 10: capture is done once every 4 events
.EQU  TIM3_CCMR1_IC3PSC_8, 3 << 2     @ 11: capture is done once every 8 events
.EQU  TIM3_CCMR2_CC3S_N , 0           @ Bits 1:0 CC3S: Capture/compare 3 selection
                                       @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM3_CCMR2_CC3S_OUT, 0          @ 00: CC3 channel is configured as output
.EQU  TIM3_CCMR2_CC3S_TI1, 1          @ 01: CC3 channel is configured as input, IC3 is mapped on TI3
.EQU  TIM3_CCMR2_CC3S_TI2, 2          @ 10: CC3 channel is configured as input, IC3 is mapped on TI4
.EQU  TIM3_CCMR2_CC3S_TRC, 3          @ 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
                                       @ an internal trigger input is selected through TS bit (TIMx_SMCR register)
                                       @ Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
@.END

@.ITEM TIM3_CCER
.EQU  TIM3_CCER_CC4NP  , 1 << 15    @ Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description
.EQU  TIM3_CCER_CC4P    , 1 << 13     @ Bit 13 CC4P: Capture/Compare 4 output polarity refer to CC1P description
.EQU  TIM3_CCER_CC4E    , 1 << 12     @ Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description
.EQU  TIM3_CCER_CC3NP   , 1 << 11     @ Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description
.EQU  TIM3_CCER_CC3NE   , 1 << 10     @ Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description
.EQU  TIM3_CCER_CC3P    , 1 << 9      @ Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description
.EQU  TIM3_CCER_CC3E    , 1 << 8      @ Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description
.EQU  TIM3_CCER_CC2NP   , 1 << 7      @ Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description
.EQU  TIM3_CCER_CC2NE   , 1 << 6      @ Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description
.EQU  TIM3_CCER_CC2P    , 1 << 5      @ Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description
.EQU  TIM3_CCER_CC2E    , 1 << 4      @ Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description
.EQU  TIM3_CCER_CC1NP   , 1 << 3      @ Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
                                       @ CC1 channel configuration as output:
                                       @ 0: OC1N active high.
                                       @ 1: OC1N active low.
                                       @ CC1 channel configuration as input:
                                       @ This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to
                                       @ CC1P description.
                                 @ Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
                                       @ set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
                                       @ preloaded bits only when a Commutation event is generated.
                                 @ Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
                                       @ in TIMx_BDTR register) and CC1S=00 (the channel is configured in output).
.EQU  TIM3_CCER_CC1NE   , 1 << 2      @ Bit 2 CC1NE: Capture/Compare 1 complementary output enable
                                       @ 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
                                       @ and CC1E bits.
                                       @ 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
                                       @ OSSR, OIS1, OIS1N and CC1E bits.
                                       @ Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
                                       @ set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the
                                       @ preloaded bits only when a Commutation event is generated.
.EQU  TIM3_CCER_CC1P    , 1 << 1      @ Bit 1 CC1P: Capture/Compare 1 output polarity
                                       @ CC1 channel configured as output:
                                       @ 0: OC1 active high
                                       @ 1: OC1 active low
                                       @ CC1 channel configured as input:
                                       @ CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture
                                       @ operations.
                                       @ 00: non-inverted/rising edge
                                       @ The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external
                                       @ clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).
                                       @ 01: inverted/falling edge
                                       @ The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external
                                       @ clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
                                       @ 10: reserved, do not use this configuration.
                                       @ 11: non-inverted/both edges
                                       @ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations
                                       @ in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated
                                       @ mode). This configuration must not be used in encoder mode.
                                 @ Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
                                       @ set in the TIMx_CR2 register then the CC1P active bit takes the new value from the
                                       @ preloaded bits only when a Commutation event is generated.
                                 @ Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
                                       @ in TIMx_BDTR register).
.EQU  TIM3_CCER_CC1E    , 1           @ Bit 0 CC1E: Capture/Compare 1 output enable
                                       @ CC1 channel configured as output:
                                       @ 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
                                       @ and CC1NE bits.
                                       @ 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
                                       @ OSSR, OIS1, OIS1N and CC1NE bits.
                                       @ CC1 channel configured as input:
                                       @ This bit determines if a capture of the counter value can actually be done into the input
                                       @ capture/compare register 1 (TIMx_CCR1) or not.
                                       @ 0: Capture disabled.
                                       @ 1: Capture enabled.
                                 @ Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
                                       @ set in the TIMx_CR2 register then the CC1E active bit takes the new value from the
                                       @ preloaded bits only when a Commutation event is generated.
@.END

@.ITEM     TIM3_DCR
.EQU  TIM3_DCR_DBL_N    , 8           @ Bits 12:8 DBL[4:0]: DMA burst length
                                       @ This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
                                       @ when a read or a write access is done to the TIMx_DMAR address)
                                       @ 00000: 1 transfer
                                       @ 00001: 2 transfers
                                       @ 00010: 3 transfers
                                       @ ...
                                       @ 10001: 18 transfers
.EQU  TIM3_DCR_DBA_N    , 0           @ Bits 4:0 DBA[4:0]: DMA base address
                                       @ This 5-bit vector defines the base-address for DMA transfers (when read/write access are
                                       @ done through the TIMx_DMAR address). DBA is defined as an offset starting from the address
                                       @ of the TIMx_CR1 register.
                              @ Example:
                                       @ 00000: TIMx_CR1,
                                       @ 00001: TIMx_CR2,
                                       @ 00010: TIMx_SMCR,
                                       @ ...
                              @ Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In
                                       @ this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
@.END

@.ITEM TIM3_DMAR
.EQU  TIM3_DMAR_DMAB_N, 0              @ Bits 15:0 DMAB[15:0]: DMA register for burst accesses
                                       @ A read or write operation to the DMAR register accesses the register located at the address
                                       @ (TIMx_CR1 address) + (DBA + DMA index) x 4
                                       @ where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
                                       @ address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
                                       @ transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
@.END



