@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"

@.ITEM     APB2PERIPH_BASE
.EQU  USART1_BASE        , APB2PERIPH_BASE + 0x3800
.EQU  USART1             , PERIPH_BASE + USART1_BASE

@.ITEM     APB1PERIPH_BASE
.EQU  USART2_BASE        , APB1PERIPH_BASE + 0x4400
.EQU  USART2             , PERIPH_BASE + USART2_BASE

@.ITEM     USART1_BASE USART1 USART2_BASE USART2
.EQU  USART_SR           , 0x00                    @ Status re gister ( USART_SR)
.EQU  USART_DR           , 0x04                    @ Data register (USART_DR)
.EQU  USART_BRR          , 0X08                    @ Baud rate register (USART_BRR)
.EQU  USART_CR1          , 0X0C                    @ Control register 1 (USART_CR1)
.EQU  USART_CR2          , 0X10                    @ Control register 2 (USART_CR2)
.EQU  USART_CR3          , 0X14                    @ Control register 3 (USART_CR3)
.EQU  USART_GTPR         , 0X18                    @ Guard time and prescaler register (USART_GTPR)


@.ITEM     USART_SR
.EQU  USART_SR_RSTVAL    , 0X00C00000              @ Reset value: 0x00C0 0000
.EQU  USART_SR_CTS       , 1 << 9                  @ Bit 9 CTS: CTS flag
.EQU  USART_SR_LBD       , 1 << 8                  @ Bit 8 LBD: LIN break detection flag
.EQU  USART_SR_TXE       , 1 << 7                  @ Bit 7 TXE: Transmit data register empty
.EQU  USART_SR_TC        , 1 << 6                  @ Bit 6 TC: Transmission complete
.EQU  USART_SR_RXNE      , 1 << 5                  @ Bit 5 RXNE: Read data register not empty
.EQU  USART_SR_IDLE      , 1 << 4                  @ Bit 4 IDLE: IDLE line detected
.EQU  USART_SR_ORE       , 1 << 3                  @ Bit 3 ORE: Overrun error
.EQU  USART_SR_NF        , 1 << 2                  @ Bit 2 NF: Noise detected flag
.EQU  USART_SR_FE        , 1 << 1                  @ Bit 1 FE: Framing error
.EQU  USART_SR_PE        , 1                       @ Bit 0 PE: Parity error

@.ITEM     USART_DR
.EQU  USART_DR_M         , 0X1FF                   @ Bits 8:0 DR[8:0]: Data value

@.ITEM     USART_BRR
.EQU  USART_BRR_MANT_N   , 4                       @ Bits 15:4 DIV_Mantissa[11:0]: mantissa of USARTDIV
.EQU  USART_BRR_FRACT_N  , 0                       @ Bits 3:0 DIV_Fraction[3:0]: fraction of USARTDIV

@.ITEM     USART_CR1
.EQU  USART_CR1_OVER8    , 1 << 15                 @ Bit 15 OVER8: Oversampling mode
.EQU  USART_CR1_UE       , 1 << 13                 @ Bit 13 UE: USART enable
.EQU  USART_CR1_M        , 1 << 12                 @ Bit 12 M: Word length
.EQU  USART_CR1_WAKE     , 1 << 11                 @ Bit 11 WAKE: Wakeup method
.EQU  USART_CR1_PCE      , 1 << 10                 @ Bit 10 PCE: Parity control enable
.EQU  USART_CR1_PS       , 1 << 9                  @ Bit 9 PS: Parity selection
.EQU  USART_CR1_PEIE     , 1 << 8                  @ Bit 8 PEIE: PE interrupt enable
.EQU  USART_CR1_TXEIE    , 1 << 7                  @ Bit 7 TXEIE: TXE interrupt enable
.EQU  USART_CR1_TCIE     , 1 << 6                  @ Bit 6 TCIE: Transmission complete interrupt enable
.EQU  USART_CR1_RXNEIE   , 1 << 5                  @ Bit 5 RXNEIE: RXNE interrupt enable
.EQU  USART_CR1_IDLEIE   , 1 << 4                  @ Bit 4 IDLEIE: IDLE interrupt enable
.EQU  USART_CR1_TE       , 1 << 3                  @ Bit 3 TE: Transmitter enable
.EQU  USART_CR1_RE       , 1 << 2                  @ Bit 2 RE: Receiver enable
.EQU  USART_CR1_RWU      , 1 << 1                  @ Bit 1 RWU: Receiver wakeup
.EQU  USART_CR1_SBK      , 1 << 0                  @ Bit 0 SBK: Send break

@.ITEM     USART_CR2
.EQU  USART_CR2_LINEN    , 1 << 14                 @ Bit 14 LINEN: LIN mode enable
.EQU  USART_CR2_STOP_N   , 1 << 12                 @ Bits 13:12 STOP: STOP bits
.EQU  USART_CR2_1SB      , 0 << 12                 @ 00: 1 Stop bit
.EQU  USART_CR2_0D5SB    , 1 << 12                 @ 01: 0.5 Stop bit
.EQU  USART_CR2_2SB      , 2 << 12                 @ 10: 2 Stop bits
.EQU  USART_CR2_1D5SB    , 3 << 12                 @ 11: 1.5 Stop bit
.EQU  USART_CR2_CLKEN    , 1 << 11                 @ Bit 11 CLKEN: Clock enable
.EQU  USART_CR2_CPOL     , 1 << 10                 @ Bit 10 CPOL: Clock polarity
.EQU  USART_CR2_CPHA     , 1 << 9                  @ Bit 9 CPHA: Clock phase
.EQU  USART_CR2_LBCL     , 1 << 8                  @ Bit 8 LBCL: Last bit clock pulse
.EQU  USART_CR2_LBDIE    , 1 << 6                  @ Bit 6 LBDIE: LIN break detection interrupt enable
.EQU  USART_CR2_LBDL     , 1 << 5                  @ Bit 5 LBDL: lin break detection length
.EQU  USART_CR2_ADD      , 1 << 0                  @ Bits 3:0 ADD[3:0]: Address of the USART node

@.ITEM     USART_CR3
.EQU  USART_CR3_ONEBIT   , 1 << 11                 @ Bit 11 ONEBIT: One sample bit method enable
.EQU  USART_CR3_CTSIE    , 1 << 10                 @ Bit 7 DMAT: DMA enable transmitter
.EQU  USART_CR3_CTSE     , 1 << 9                  @
.EQU  USART_CR3_RTSE     , 1 << 8                  @
.EQU  USART_CR3_DMAT     , 1 << 7                  @ Bit 7 DMAT: DMA enable transmitter
.EQU  USART_CR3_DMAR     , 1 << 6                  @ Bit 6 DMAR: DMA enable receive
.EQU  USART_CR3_SCEN     , 1 << 5                  @ Bit 5 SCEN: Smartcard mode enable
.EQU  USART_CR3_NACK     , 1 << 4                  @ Bit 4 NACK: Smartcard NACK enable
.EQU  USART_CR3_HDSEL    , 1 << 3                  @ Bit 3 HDSEL: Half-duplex selection
.EQU  USART_CR3_IRLP     , 1 << 2                  @ Bit 2 IRLP: IrDA low-power
.EQU  USART_CR3_IREN     , 1 << 1                  @ Bit 1 IREN: IrDA mode enable
.EQU  USART_CR3_EIE      , 1                       @ Bit 0 EIE: Error interrupt enable

@.ITEM     USART_GTPR
.EQU  USART_GTPR_GT_N    , 8
.EQU  USART_GTPR_PSC_N   , 0                       @ Bits 7:0 PSC[7:0]: Prescaler value



