@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                     Áàçîâûå êîíñòàíòû RCC                        |
@ |                           STM32F303                              |
@ +------------------------------------------------------------------+
@.ENDDESC


.INCLUDE   "/src/inc/base.inc"

@.ITEM     AHB1PERIPH_BASE
.EQU  RCC_BASE                    , ( AHB1PERIPH_BASE + 0x1000 )    @ Áàçîâûé àäðåñ RCC
.EQU  RCC                         , PERIPH_BASE + RCC_BASE
@.END

@.ITEM     RCC_BASE RCC
.EQU  RCC_CR                      , 0x00    @ RCC clock control register
.EQU  RCC_CFGR                    , 0x04    @ Clock configuration register
.EQU  RCC_CIR                     , 0x08    @ Clock interrupt register
.EQU  RCC_APB2RSTR                , 0x0C    @ RCC APB2 peripheral reset register
.EQU  RCC_APB1RSTR                , 0x10    @ RCC APB1 peripheral reset register
.EQU  RCC_AHBENR                  , 0x14    @ RCC AHB peripheral clock register
.EQU  RCC_APB2ENR                 , 0x18    @ RCC APB2 peripheral clock enable register
.EQU  RCC_APB1ENR                 , 0x1C    @ RCC APB1 peripheral clock enable register
.EQU  RCC_BDCR                    , 0x20    @ RCC Backup domain control register
.EQU  RCC_CSR                     , 0x24    @ RCC clock control & status register
.EQU  RCC_AHBRSTR                 , 0x28    @ RCC AHB peripheral reset register
.EQU  RCC_CFGR2                   , 0x2C    @ RCC clock configuration register 2
.EQU  RCC_CFGR3                   , 0x30    @ RCC clock configuration register 3
@.END

@.ITEM     RCC_CR
.EQU  RCC_CR_HSION_N              , 0     @ Bit 0 HSION: HSI clock enable
.EQU  RCC_CR_HSION                , ( 0x1 << 0 )    @ 1: HSI oscillator ON
.EQU  RCC_CR_HSIRDY_N             , 1     @ Bit 1 HSIRDY: HSI clock ready flag
.EQU  RCC_CR_HSITRIM_N            , 3     @ Bits 7:3 HSITRIM[4:0]: HSI clock trimming
.EQU  RCC_CR_HSICAL_N             , 8     @ Bits 15:8 HSICAL[7:0]: HSI clock calibration
.EQU  RCC_CR_HSEON_N              , 16    @ Bit 16 HSEON: HSE clock enable
.EQU  RCC_CR_HSEON                , ( 0x1 << 16 )    @ 1: HSE oscillator ON
.EQU  RCC_CR_HSERDY_N             , 17    @ Bit 17 HSERDY: HSE clock ready flag
.EQU  RCC_CR_HSEBYP_N             , 18    @ Bit 18 HSEBYP: HSE crystal oscillator bypass
.EQU  RCC_CR_HSEBYP               , ( 0x1 << 18 )    @ 1: HSE crystal oscillator bypassed with external clock
.EQU  RCC_CR_CSSON_N              , 19    @ Bit 19 CSSON: Clock security system enable
.EQU  RCC_CR_CSSON                , ( 0x1 << 19 )    @ 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not).
.EQU  RCC_CR_PLLON_N              , 24    @ Bit 24 PLLON: PLL enable
.EQU  RCC_CR_PLLON                , ( 0x1 << 24 )    @ 1: PLL ON
.EQU  RCC_CR_PLLRDY_N             , 25    @ Bit 25 PLLRDY: PLL clock ready flag
@.END

@.ITEM     RCC_CFGR
.EQU  RCC_CFGR_SW_N               , 0     @ Bits 1:0 SW: System clock switch
.EQU  RCC_CFGR_SW_HSI             , 0x00000000    @ HSI selected as system clock
.EQU  RCC_CFGR_SW_HSE             , 0x00000001    @ HSE selected as system clock
.EQU  RCC_CFGR_SW_PLL             , 0x00000002    @ PLL selected as system clock
.EQU  RCC_CFGR_SWS_N              , 2     @ Bits 3:2 SWS: System clock switch status
.EQU  RCC_CFGR_SWS_HSI            , 0x00000000    @ HSI oscillator used as system clock
.EQU  RCC_CFGR_SWS_HSE            , 0x00000004    @ HSE oscillator used as system clock
.EQU  RCC_CFGR_SWS_PLL            , 0x00000008    @ PLL used as system clock
.EQU  RCC_CFGR_HPRE_N             , 4     @   Bits 7:4 HPRE: (AHB prescaler)
.EQU  RCC_CFGR_HPRE_DIV1          , 0x00000000    @ SYSCLK not divided
.EQU  RCC_CFGR_HPRE_DIV2          , 0x00000080    @ SYSCLK divided by 2
.EQU  RCC_CFGR_HPRE_DIV4          , 0x00000090    @ SYSCLK divided by 4
.EQU  RCC_CFGR_HPRE_DIV8          , 0x000000A0    @ SYSCLK divided by 8
.EQU  RCC_CFGR_HPRE_DIV16         , 0x000000B0    @ SYSCLK divided by 16
.EQU  RCC_CFGR_HPRE_DIV64         , 0x000000C0    @ SYSCLK divided by 64
.EQU  RCC_CFGR_HPRE_DIV128        , 0x000000D0    @ SYSCLK divided by 128
.EQU  RCC_CFGR_HPRE_DIV256        , 0x000000E0    @ SYSCLK divided by 256
.EQU  RCC_CFGR_HPRE_DIV512        , 0x000000F0    @ SYSCLK divided by 512
.EQU  RCC_CFGR_PPRE1_N            , 8     @ Bits 10:8 PPRE1: APB low-speed prescaler (APB1)
.EQU  RCC_CFGR_PPRE1_DIV2         , 4 << 8    @ HCLK divided by 2
.EQU  RCC_CFGR_PPRE1_DIV4         , 5 << 8    @ HCLK divided by 4
.EQU  RCC_CFGR_PPRE1_DIV8         , 6 << 8    @ HCLK divided by 8
.EQU  RCC_CFGR_PPRE1_DIV16        , 7 << 8    @ HCLK divided by 16
.EQU  RCC_CFGR_PPRE2_N            , 11    @ Bits 13:11 PPRE2: APB high-speed prescaler (APB2)
.EQU  RCC_CFGR_PPRE2_DIV2         , 4 << 11    @ HCLK divided by 2
.EQU  RCC_CFGR_PPRE2_DIV4         , 5 << 11    @ HCLK divided by 4
.EQU  RCC_CFGR_PPRE2_DIV8         , 6 << 11    @ HCLK divided by 8
.EQU  RCC_CFGR_PPRE2_DIV16        , 7 << 11    @ HCLK divided by 16
.EQU  RCC_CFGR_PLLSRC             , 0x01 << 16    @ Bit 16 PLLSRC: PLL entry clock source, 0: âõîäíàÿ ÷àñòîòà PLL=HSI/2, 1:Clock from PREDIV1 selected as the PLL input clock
.EQU  RCC_CFGR_PLLXTPRE           , 0x01 << 17    @ Bit 17 PLLXTPRE: LSB of division factor PREDIV1
.EQU  RCC_CFGR_PLLMUL_N           , 18    @ Bits 21:18 PLLMUL: PLL multiplication factor
.EQU  RCC_CFGR_PLLMUL2            , 0x00 << 18    @ PLL * 2
.EQU  RCC_CFGR_PLLMUL3            , 0x01 << 18    @ PLL * 3
.EQU  RCC_CFGR_PLLMUL4            , 0x02 << 18    @ PLL * 4
.EQU  RCC_CFGR_PLLMUL5            , 0x03 << 18    @ PLL * 5
.EQU  RCC_CFGR_PLLMUL6            , 0x04 << 18    @ PLL * 6
.EQU  RCC_CFGR_PLLMUL7            , 0x05 << 18    @ PLL * 7
.EQU  RCC_CFGR_PLLMUL8            , 0x06 << 18    @ PLL * 8
.EQU  RCC_CFGR_PLLMUL9            , 0x07 << 18    @ PLL * 9
.EQU  RCC_CFGR_PLLMUL10           , 0x08 << 18    @ PLL * 10
.EQU  RCC_CFGR_PLLMUL11           , 0x09 << 18    @ PLL * 11
.EQU  RCC_CFGR_PLLMUL12           , 0x0A << 18    @ PLL * 12
.EQU  RCC_CFGR_PLLMUL13           , 0x0B << 18    @ PLL * 13
.EQU  RCC_CFGR_PLLMUL14           , 0x0C << 18    @ PLL * 14
.EQU  RCC_CFGR_PLLMUL15           , 0x0D << 18    @ PLL * 15
.EQU  RCC_CFGR_PLLMUL16           , 0x0E << 18    @ PLL * 16
.EQU  RCC_CFGR_PLLMUL_16          , 0x0F << 18    @ PLL * 16

.EQU  RCC_CFGR_USBPRE_N           , 22    @ Bit 22 USBPRE: USB prescaler
.EQU  RCC_CFGR_USBPRE             , 0x1 << 22    @ USB prescaler
.EQU  RCC_CFGR_I2SSRC_N           , 23    @ I2S configuration
.EQU  RCC_CFGR_I2SSRC             , 0x1 << 23    @ I2S external clock source selection
.EQU  RCC_CFGR_MCO_N              , 24    @ Bits 26:24 MCO: Microcontroller clock output
.EQU  RCC_CFGR_MCO_0              , 0x00    @ MCO output disabled, no clock on MCO
.EQU  RCC_CFGR_MCO_1              , 1 << 24    @ Reserved
.EQU  RCC_CFGR_MCO_2              , 2 << 24    @ LSI clock selected.
.EQU  RCC_CFGR_MCO_3              , 3 << 24    @ LSE clock selected.
.EQU  RCC_CFGR_MCO_4              , 4 << 24    @ System clock (SYSCLK) selected
.EQU  RCC_CFGR_MCO_5              , 5 << 24    @ HSI clock selected
.EQU  RCC_CFGR_MCO_6              , 6 << 24    @ HSE clock selected
.EQU  RCC_CFGR_MCO_7              , 7 << 24    @ PLL clock selected (divided by 1 or 2 depending on PLLNODIV bit).
.EQU  RCC_CFGR_MCOPRE_N           , 28    @ Bit 28 MCOF: Microcontroller Clock Output Flag (STM32F303xB/C and STM32F358xC only)
.EQU  RCC_CFGR_MCOPRE_1           , 0 << 28    @ MCO is divided by 1
.EQU  RCC_CFGR_MCOPRE_2           , 1 << 28    @ MCO is divided by 2
.EQU  RCC_CFGR_MCOPRE_4           , 2 << 28    @ MCO is divided by 4
.EQU  RCC_CFGR_MCOPRE_8           , 3 << 28    @ MCO is divided by 8
.EQU  RCC_CFGR_MCOPRE_16          , 4 << 28    @ MCO is divided by 16
.EQU  RCC_CFGR_MCOPRE_32          , 5 << 28    @ MCO is divided by 32
.EQU  RCC_CFGR_MCOPRE_64          , 6 << 28    @ MCO is divided by 64
.EQU  RCC_CFGR_MCOPRE_128         , 7 << 28    @ MCO is divided by 128
.EQU  RCC_CFGR_PLLNODIV_N         , 31    @ Bit 31 PLLNODIV: Do not divide PLL to MCO (in STM32F303x6/8 and STM32F328x8 , STM32F303xDxE and STM32F398xE only)
.EQU  RCC_CFGR_PLLNODIV           , 1 << 31    @ 1: PLL is not divided before MCO
@.END

@.ITEM     RCC_CIR
.EQU  RCC_CIR_LSIRDYF_N           , 0     @ Bit 0 LSIRDYF: LSI ready interrupt flag
.EQU  RCC_CIR_LSERDYF_N           , 1     @ Bit 1 LSERDYF: LSE ready interrupt flag
.EQU  RCC_CIR_HSIRDYF_N           , 2     @ Bit 2 HSIRDYF: HSI ready interrupt flag
.EQU  RCC_CIR_HSERDYF_N           , 3     @ Bit 3 HSERDYF: HSE ready interrupt flag
.EQU  RCC_CIR_PLLRDYF_N           , 4     @ Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
.EQU  RCC_CIR_CSSF_N              , 7     @ Bit 7 CSSF: Clock security system interrupt flag
.EQU  RCC_CIR_LSIRDYIE_N          , 8     @ Bit 8 LSIRDYIE: LSI ready interrupt enable
.EQU  RCC_CIR_LSIRDYIE            , 0x00000100
.EQU  RCC_CIR_LSERDYIE_N          , 9     @ Bit 9 LSERDYIE: LSE ready interrupt enable
.EQU  RCC_CIR_LSERDYIE            , 0x00000200
.EQU  RCC_CIR_HSIRDYIE_N          , 10    @ Bit 10 HSIRDYIE: HSI ready interrupt enable
.EQU  RCC_CIR_HSIRDYIE            , 0x00000400
.EQU  RCC_CIR_HSERDYIE_N          , 11    @ Bit 11 HSERDYIE: HSE ready interrupt enable
.EQU  RCC_CIR_HSERDYIE            , 0x00000800
.EQU  RCC_CIR_PLLRDYIE_N          , 12    @ Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
.EQU  RCC_CIR_PLLRDYIE            , 0x00001000
.EQU  RCC_CIR_LSIRDYC_N           , 16    @ Bit 16 LSIRDYC: LSI ready interrupt clear
.EQU  RCC_CIR_LSIRDYC             , 0x00010000
.EQU  RCC_CIR_LSERDYC_N           , 17    @ Bit 17 LSERDYC: LSE ready interrupt clear
.EQU  RCC_CIR_LSERDYC             , 0x00020000
.EQU  RCC_CIR_HSIRDYC_N           , 18    @ Bit 18 HSIRDYC: HSI ready interrupt clear
.EQU  RCC_CIR_HSIRDYC             , 0x00040000
.EQU  RCC_CIR_HSERDYC_N           , 19    @ Bit 19 HSERDYC: HSE ready interrupt clear
.EQU  RCC_CIR_HSERDYC             , 0x00080000
.EQU  RCC_CIR_PLLRDYC_N           , 20    @ Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
.EQU  RCC_CIR_PLLRDYC             , 0x00100000
.EQU  RCC_CIR_CSSC_N              , 23    @ Bit 23 CSSC: Clock security system interrupt clear
.EQU  RCC_CIR_CSSC                , 0x00800000
@.END

@.ITEM     RCC_APB2RSTR
.EQU  RCC_APB2RSTR_SYSCFGRST_N    , 0     @ Bit 0 SYSCFGRST: SYSCFG, Comparators and operational amplifiers rese
.EQU  RCC_APB2RSTR_TIM1RST_N      , 11    @ Bit 11 TIM1RST: TIM1 timer reset
.EQU  RCC_APB2RSTR_SPI1RST_N      , 12    @ Bit 12 SPI1RST: SPI1 reset
.EQU  RCC_APB2RSTR_TIM8RST_N      , 13    @ Bit 13 TIM8RST: TIM8 timer reset (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE
.EQU  RCC_APB2RSTR_USART1RST_N    , 14    @ Bit 14 USART1RST: USART1 reset
.EQU  RCC_APB2RSTR_SPI4RST_N      , 15    @ Bit 15 SPI4RST: SPI4 reset (only onSTM32F303xD/E and STM32F398xE devices
.EQU  RCC_APB2RSTR_TIM15RST_N     , 16    @ Bit 16 TIM15RST: TIM15 timer reset
.EQU  RCC_APB2RSTR_TIM16RST_N     , 17    @ Bit 17 TIM16RST: TIM16 timer reset
.EQU  RCC_APB2RSTR_TIM17RST_N     , 18    @ Bit 18 TIM17RST: TIM17 timer reset
.EQU  RCC_APB2RSTR_TIM20RST_N     , 20    @ Bit 20 TIM20RST: TIM20 timer reset (only on STM32F303xD/E and STM32F398xE devices
.EQU  RCC_APB2RSTR_SYSCFGRST      , 1 << 0    @ 1: Reset SYSCFG, COMP, and OPAM
.EQU  RCC_APB2RSTR_TIM1RST        , 1 << 11    @ 1: Reset TIM1 timer
.EQU  RCC_APB2RSTR_SPI1RST        , 1 << 12    @ 1: Reset SPI1
.EQU  RCC_APB2RSTR_TIM8RST        , 1 << 13    @ 1: Reset TIM8 timer
.EQU  RCC_APB2RSTR_USART1RST      , 1 << 14    @ 1: Reset USART1
.EQU  RCC_APB2RSTR_SPI4RST        , 1 << 15    @ 1: Reset SPI4
.EQU  RCC_APB2RSTR_TIM15RST       , 1 << 16    @ 1: Reset TIM15 timer
.EQU  RCC_APB2RSTR_TIM16RST       , 1 << 17    @ 1: Reset TIM16 timer
.EQU  RCC_APB2RSTR_TIM17RST       , 1 << 18    @ 1: Reset TIM17 timer
.EQU  RCC_APB2RSTR_TIM20RST       , 1 << 20    @ 1: Reset TIM20 timer
@.END

@.ITEM     RCC_APB1RSTR
.EQU  RCC_APB1RSTR_TIM2RST_N      , 0
.EQU  RCC_APB1RSTR_TIM3RST_N      , 1
.EQU  RCC_APB1RSTR_TIM4RST_N      , 2
.EQU  RCC_APB1RSTR_TIM6RST_N      , 4
.EQU  RCC_APB1RSTR_TIM7RST_N      , 5
.EQU  RCC_APB1RSTR_WWDGRST_N      , 11
.EQU  RCC_APB1RSTR_SPI2RST_N      , 14
.EQU  RCC_APB1RSTR_SPI3RST_N      , 15
.EQU  RCC_APB1RSTR_USART2RST_N    , 17
.EQU  RCC_APB1RSTR_USART3RST_N    , 18
.EQU  RCC_APB1RSTR_UART4RST_N     , 19
.EQU  RCC_APB1RSTR_UART5RST_N     , 20
.EQU  RCC_APB1RSTR_I2C1RST_N      , 21
.EQU  RCC_APB1RSTR_I2C2RST_N      , 22
.EQU  RCC_APB1RSTR_USBRST_N       , 23
.EQU  RCC_APB1RSTR_CANRST_N       , 25
.EQU  RCC_APB1RSTR_DAC2RST_N      , 26
.EQU  RCC_APB1RSTR_PWRRST_N       , 28
.EQU  RCC_APB1RSTR_DAC1RST_N      , 29
.EQU  RCC_APB1RSTR_I2C3RST_N      , 30
@.END

@.ITEM     RCC_AHBENR
.EQU  RCC_AHBENR_DMA1EN_N         , 0     @ Bit 0 DMA1EN: DMA1 clock enable
.EQU  RCC_AHBENR_DMA1EN           , 1     @ 1: DMA1 clock enabled
.EQU  RCC_AHBENR_DMA2EN_N         , 1     @ Bit 1 DMA2EN: DMA2 clock enable
.EQU  RCC_AHBENR_DMA2EN           , 1 << 1    @ 1: DMA2 clock enabled
.EQU  RCC_AHBENR_SRAMEN_N         , 2     @ Bit 2 SRAMEN: SRAM interface clock enable
.EQU  RCC_AHBENR_SRAMEN           , 1 << 2    @ 1: SRAM interface clock enabled during Sleep mode
.EQU  RCC_AHBENR_FLITFEN_N        , 4     @ Bit 4 FLITFEN: FLITF clock enable
.EQU  RCC_AHBENR_FLITFEN          , 1 << 4    @ 1: FLITF clock enabled during Sleep mode
.EQU  RCC_AHBENR_FMCEN_N          , 5     @ Bit 5 FMCEN: FMC clock enable. (Only on STM32F303xDxE)
.EQU  RCC_AHBENR_FMCEN            , 1 << 5    @ 1: FMC clock enabled
.EQU  RCC_AHBENR_CRCEN_N          , 6     @ Bit 6 CRCEN: CRC clock enable
.EQU  RCC_AHBENR_CRCEN            , 1 << 6    @ 1: CRC clock enabled
.EQU  RCC_AHBENR_IOPHEN_N         , 16    @ Bit 16 IOPHEN: IO port H clock enable. (Only on STM32F303xDxE)
.EQU  RCC_AHBENR_IOPHEN           , 1 << 16    @ 1: IO port H clock enabled
.EQU  RCC_AHBENR_IOPAEN_N         , 17    @ Bit 17 IOPAEN: I/O port A clock enable
.EQU  RCC_AHBENR_IOPAEN           , 1 << 17    @ 1: I/O port A clock enabled
.EQU  RCC_AHBENR_IOPBEN_N         , 18    @ Bit 18 IOPBEN: I/O port B clock enable
.EQU  RCC_AHBENR_IOPBEN           , 1 << 18    @ 1: I/O port B clock enabled
.EQU  RCC_AHBENR_IOPCEN_N         , 19    @ Bit 19 IOPCEN: I/O port C clock enable
.EQU  RCC_AHBENR_IOPCEN           , 1 << 19    @ 1: I/O port C clock enabled
.EQU  RCC_AHBENR_IOPDEN_N         , 20    @ Bit 20 IOPDEN: I/O port D clock enable
.EQU  RCC_AHBENR_IOPDEN           , 1 << 20    @ 1: I/O port D clock enabled
.EQU  RCC_AHBENR_IOPEEN_N         , 21    @ Bit 21 IOPEEN: I/O port E clock enable(STM32F303xB/C and STM32F358xC devices only)
.EQU  RCC_AHBENR_IOPEEN           , 1 << 21    @ 1: I/O port E clock enabled
.EQU  RCC_AHBENR_IOPFEN_N         , 22    @ Bit 22 IOPFEN: I/O port F clock enable
.EQU  RCC_AHBENR_IOPFEN           , 1 << 22    @ 1: I/O port F clock enabled
.EQU  RCC_AHBENR_IOPGEN_N         , 23    @ Bit 23 IOPGEN: IO port G clock enable. (Only on STM32F303xDxE).
.EQU  RCC_AHBENR_IOPGEN           , 1 << 23    @ 1: IO port G clock enabled
.EQU  RCC_AHBENR_TSCEN_N          , 24    @ Bit 24 TSCEN: Touch sensing controller clock enable
.EQU  RCC_AHBENR_TSCEN            , 1 << 24    @ 1: TSC clock enabled
.EQU  RCC_AHBENR_ADC12EN_N        , 28    @ Bit 28 ADC12EN: ADC1 and ADC2 enable
.EQU  RCC_AHBENR_ADC12EN          , 1 << 28    @ 1: ADC1 and ADC2 clock enabled
.EQU  RCC_AHBENR_ADC34EN_N        , 29    @ Bit 29 ADC34EN: ADC3 and ADC4 enable (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.EQU  RCC_AHBENR_ADC34EN          , 1 << 29    @ 1: ADC3 and ADC4 clock enabled
@.END

@.ITEM     RCC_APB2ENR
.EQU  RCC_APB2ENR_SYSCFGEN_N      , 0     @ Bit 0 SYSCFGEN: SYSCFG clock enable
.EQU  RCC_APB2ENR_TIM1EN_N        , 11    @ Bit 11 TIM1EN: TIM1 timer clock enable
.EQU  RCC_APB2ENR_SPI1EN_N        , 12    @ Bit 12 SPI1EN: SPI1 clock enable
.EQU  RCC_APB2ENR_TIM8EN_N        , 13    @ Bit 13 TIM8EN: TIM8 timer clock enable (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.EQU  RCC_APB2ENR_USART1EN_N      , 14    @ Bit 14 USART1EN: USART1 clock enable
.EQU  RCC_APB2ENR_SPI4EN_N        , 15    @ Bit 15 SPI4EN: SPI4 clock enable (STM32F303xD/E and STM32F398xE only)
.EQU  RCC_APB2ENR_TIM15EN_N       , 16    @ Bit 16 TIM15EN: TIM15 timer clock enable
.EQU  RCC_APB2ENR_TIM16EN_N       , 17    @ Bit 17 TIM16EN: TIM16 timer clock enable
.EQU  RCC_APB2ENR_TIM17EN_N       , 18    @ Bit 18 TIM17EN: TIM17 timer clock enable
.EQU  RCC_APB2ENR_TIM20EN_N       , 20    @ Bit 20 TIM20EN: TIM20 timer clock enable (STM32F303xD/E and STM32F398xE only)
@.END

@.ITEM     RCC_APB1ENR
.EQU  RCC_APB1ENR_TIM2EN_N        , 0     @ Bit 0 TIM2EN: TIM2 clock enable
.EQU  RCC_APB1ENR_TIM3EN_N        , 1     @ Bit 1 TIM3EN: TIM3 clock enable
.EQU  RCC_APB1ENR_TIM4EN_N        , 2     @ Bit 2 TIM4EN: TIM4 clock enable
.EQU  RCC_APB1ENR_TIM6EN_N        , 4     @ Bit 4 TIM6EN: TIM6 clock enable
.EQU  RCC_APB1ENR_TIM7EN_N        , 5     @ Bit 5 TIM7EN: TIM7 clock enable
.EQU  RCC_APB1ENR_WWDGEN_N        , 11    @ Bit 11 WWDGEN: Window watchdog clock enable
.EQU  RCC_APB1ENR_SPI2EN_N        , 14    @ Bit 14 SPI2EN: SPI2 clock enable
.EQU  RCC_APB1ENR_SPI3EN_N        , 15    @ Bit 15 SPI3EN: SPI3 clock enable
.EQU  RCC_APB1ENR_USART2EN_N      , 17    @ Bit 17 USART2EN: USART2 clock enable
.EQU  RCC_APB1ENR_USART3EN_N      , 18    @ Bit 18 USART3EN: USART3 clock enable
.EQU  RCC_APB1ENR_UART4EN_N       , 19    @ Bit 19 UART4EN: UART4 clock enable       
.EQU  RCC_APB1ENR_UART5EN_N       , 20    @ Bit 20 UART5EN: UART5 clock enable
.EQU  RCC_APB1ENR_I2C1EN_N        , 21    @ Bit 21 I2C1EN: I2C1 clock enable
.EQU  RCC_APB1ENR_I2C2EN_N        , 22    @ Bit 22 I2C2EN: I2C2 clock enable
.EQU  RCC_APB1ENR_USBEN_N         , 23    @ Bit 23 USBEN: USB clock enable
.EQU  RCC_APB1ENR_CANEN_N         , 25    @ Bit 25 CANEN: CAN 1 clock enable
.EQU  RCC_APB1ENR_DAC2EN_N        , 26    @ Bit 26 DAC2EN: DAC 2 clock enable
.EQU  RCC_APB1ENR_PWREN_N         , 28    @ Bit 28 PWREN: PWR clock enable
.EQU  RCC_APB1ENR_DAC1EN_N        , 29    @ Bit 29 DAC1EN: DAC1 interface clock enable
.EQU  RCC_APB1ENR_I2C3EN_N        , 30    @ Bit 30 I2C3EN: I2C3 clock enable
@.END

@.ITEM     RCC_BDCR
.EQU  RCC_BDCR_LSEON_N            , 0     @ Bit 0 LSEON: External low-speed oscillator enable
.EQU  RCC_BDCR_LSERDY_N           , 1     @ Bit 1 LSERDY: External low-speed oscillator ready
.EQU  RCC_BDCR_LSEBYP_N           , 2     @ Bit 2 LSEBYP: External low-speed oscillator bypass
.EQU  RCC_BDCR_LSEDRV_N           , 3     @ Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
.EQU  RCC_BDCR_LSEDRV_0           , 0 << 3    @ ‘Xtal mode’ lower driving capability
.EQU  RCC_BDCR_LSEDRV_1           , 1 << 3    @ ‘Xtal mode’ medium high driving capability
.EQU  RCC_BDCR_LSEDRV_2           , 2 << 3    @ ‘Xtal mode’ medium low driving capability
.EQU  RCC_BDCR_LSEDRV_3           , 3 << 3    @ ‘Xtal mode’ higher driving capability (reset value)
.EQU  RCC_BDCR_RTCSEL_N           , 8     @ Bits 9:8 RTCSEL[1:0]: RTC clock source selection
.EQU  RCC_BDCR_RTCSEL_NO_CLOCK    , 0x00 << 8    @ Bits 9:8 RTCSEL[1:0]: RTC clock source selection
.EQU  RCC_BDCR_RTCSEL_LSE         , 0x01 << 8
.EQU  RCC_BDCR_RTCSEL_LSI         , 0x02 << 8
.EQU  RCC_BDCR_RTCSEL_HSE         , 0x03 << 8
.EQU  RCC_BDCR_RTCEN_N            , 15    @ Bit 15 RTCEN: RTC clock enable
.EQU  RCC_BDCR_BDRST_N            , 16    @ Bit 16 BDRST: Backup domain software reset
@.END

@.ITEM     RCC_CSR
.EQU  RCC_CSR_LSION_N             , 0     @ Bit 0 LSION: Internal low-speed oscillator enable
.EQU  RCC_CSR_LSION               , 0x00000001
.EQU  RCC_CSR_LSIRDY_N            , 1     @ Bit 1 LSIRDY: Internal low-speed oscillator ready
.EQU  RCC_CSR_V18PWRRSTF_N        , 23    @ Bit 23 V18PWRRSTF: Reset flag of the 1.8 V domain.
.EQU  RCC_CSR_RMVF_N              , 24    @ Bit 24 RMVF: Remove reset flag
.EQU  RCC_CSR_OBLRSTF_N           , 25    @ Bit 25 OBLRSTF: Option byte loader reset flag
.EQU  RCC_CSR_PINRSTF_N           , 26    @ Bit 26 PINRSTF: PIN reset flag
.EQU  RCC_CSR_PORRSTF_N           , 27    @ Bit 27 PORRSTF: POR/PDR reset flag
.EQU  RCC_CSR_SFTRSTF_N           , 28    @ Bit 28 SFTRSTF: Software reset flag
.EQU  RCC_CSR_IWDGRSTF_N          , 29    @ Bit 29 IWDGRSTF: Independent watchdog reset flag
.EQU  RCC_CSR_WWDGRSTF_N          , 30    @ Bit 30 WWDGRSTF: Window watchdog reset flag
.EQU  RCC_CSR_LPWRRSTF_N          , 31    @Bit 31 LPWRRSTF: Low-power reset flag
@.END

@.ITEM     RCC_AHBRSTR
.EQU  RCC_AHBRSTR_FMCRST_N        , 5     @ Bit 5 FMCRST: FMC reset (Only on STM32F303xDxE).
.EQU  RCC_AHBRSTR_FMCRST          , 1 << 5    @ 1: Reset FMC
.EQU  RCC_AHBRSTR_IOPHRST_N       , 16    @ Bit 16 IOPHRST: I/O port H reset (Only on STM32F303xDxE).
.EQU  RCC_AHBRSTR_IOPHRST         , 1 << 16    @ 1: Reset I/O port H
.EQU  RCC_AHBRSTR_IOPARST_N       , 17    @ Bit 17 IOPARST: I/O port A reset
.EQU  RCC_AHBRSTR_IOPARST         , 1 << 17    @ 1: Reset I/O port A
.EQU  RCC_AHBRSTR_IOPBRST_N       , 18    @ Bit 18 IOPBRST: I/O port B reset
.EQU  RCC_AHBRSTR_IOPBRST         , 1 << 18    @ 1: Reset I/O port B
.EQU  RCC_AHBRSTR_IOPCRST_N       , 19    @ Bit 19 IOPCRST: I/O port C reset
.EQU  RCC_AHBRSTR_IOPCRST         , 1 << 19    @ 1: Reset I/O port C
.EQU  RCC_AHBRSTR_IOPDRST_N       , 20    @ Bit 20 IOPDRST: I/O port D reset
.EQU  RCC_AHBRSTR_IOPDRST         , 1 << 20    @ 1: Reset I/O port D
.EQU  RCC_AHBRSTR_IOPERST_N       , 21    @ Bit 21 IOPERST: I/O port E reset
.EQU  RCC_AHBRSTR_IOPERST         , 1 << 21    @ 1: Reset I/O port E
.EQU  RCC_AHBRSTR_IOPFRST_N       , 22    @ Bit 22 IOPFRST: I/O port F reset
.EQU  RCC_AHBRSTR_IOPFRST         , 1 << 22    @ 1: Reset I/O port F
.EQU  RCC_AHBRSTR_IOPGRST_N       , 23    @ Bit 23 IOPGRST: I/O port G reset. (Only on STM32F303xDxE)
.EQU  RCC_AHBRSTR_IOPGRST         , 1 << 23    @ 1: Reset I/O port G
.EQU  RCC_AHBRSTR_TSCRST_N        , 24    @ Bit 24 TSCRST: Touch sensing controller reset
.EQU  RCC_AHBRSTR_TSCRST          , 1 << 24    @ 1: Reset TSC
.EQU  RCC_AHBRSTR_ADC12RST_N      , 28    @ Bit 28 ADC12RST: ADC1 and ADC2 reset
.EQU  RCC_AHBRSTR_ADC12RST        , 1 << 28    @ 1: resets the ADC1 and ADC2
.EQU  RCC_AHBRSTR_ADC34RST_N      , 29    @ Bit 29 ADC34RST: ADC3 and ADC4 reset (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.EQU  RCC_AHBRSTR_ADC34RST        , 1 << 29    @ 1: resets the ADC3 and ADC4
@.END

@.ITEM     RCC_CFGR2
.EQU  RCC_CFGR2_PREDIV_N          , 0     @ Bits 3:0 PREDIV: PREDIV division factor
.EQU  RCC_CFGR2_PREDIV_2          , 1     @ HSE input to PLL divided by 2
.EQU  RCC_CFGR2_PREDIV_3          , 2     @ HSE input to PLL divided by 3
.EQU  RCC_CFGR2_PREDIV_4          , 3     @ HSE input to PLL divided by 4
.EQU  RCC_CFGR2_PREDIV_5          , 4     @ HSE input to PLL divided by 5
.EQU  RCC_CFGR2_PREDIV_6          , 5     @ HSE input to PLL divided by 6
.EQU  RCC_CFGR2_PREDIV_7          , 6     @ HSE input to PLL divided by 7
.EQU  RCC_CFGR2_PREDIV_8          , 7     @ HSE input to PLL divided by 8
.EQU  RCC_CFGR2_PREDIV_9          , 8     @ HSE input to PLL divided by 9
.EQU  RCC_CFGR2_PREDIV_10         , 9     @ HSE input to PLL divided by 10
.EQU  RCC_CFGR2_PREDIV_11         , 10    @ HSE input to PLL divided by 11
.EQU  RCC_CFGR2_PREDIV_12         , 11    @ HSE input to PLL divided by 12
.EQU  RCC_CFGR2_PREDIV_13         , 12    @ HSE input to PLL divided by 13
.EQU  RCC_CFGR2_PREDIV_14         , 13    @ HSE input to PLL divided by 14
.EQU  RCC_CFGR2_PREDIV_15         , 14    @ HSE input to PLL divided by 15
.EQU  RCC_CFGR2_PREDIV_16         , 15    @ HSE input to PLL divided by 16
.EQU  RCC_CFGR2_ADC12PRES_N       , 4     @ Bits 8:4 ADC12PRES: ADC12 prescaler
.EQU  RCC_CFGR2_ADC34PRES_N       , 9     @ Bits 13:9 ADC34PRES: ADC34 prescaler (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE only)
.EQU  RCC_CFGR2_ADCxxPRES_1       , 0B10000    @ PLL clock divided by 1
.EQU  RCC_CFGR2_ADCxxPRES_2       , 0B10001    @ PLL clock divided by 2
.EQU  RCC_CFGR2_ADCxxPRES_4       , 0B10010    @ PLL clock divided by 4
.EQU  RCC_CFGR2_ADCxxPRES_6       , 0B10011    @ PLL clock divided by 6
.EQU  RCC_CFGR2_ADCxxPRES_8       , 0B10100    @ PLL clock divided by 8
.EQU  RCC_CFGR2_ADCxxPRES_10      , 0B10101    @ PLL clock divided by 10
.EQU  RCC_CFGR2_ADCxxPRES_12      , 0B10110    @ PLL clock divided by 12
.EQU  RCC_CFGR2_ADCxxPRES_16      , 0B10111    @ PLL clock divided by 16
.EQU  RCC_CFGR2_ADCxxPRES_32      , 0B11000    @ PLL clock divided by 32
.EQU  RCC_CFGR2_ADCxxPRES_64      , 0B11001    @ PLL clock divided by 64
.EQU  RCC_CFGR2_ADCxxPRES_128     , 0B11010    @ PLL clock divided by 128
.EQU  RCC_CFGR2_ADCxxPRES_256     , 0B11011    @ PLL clock divided by 256
@.END

@.ITEM     RCC_CFGR3
.EQU  RCC_CFGR3_USART1SW_N        , 0     @ Bits 1:0 USART1SW[1:0]: USART1 clock source selection
.EQU  RCC_CFGR3_USART1SW_PCLK     , 0     @ PCLK2 clock used as USART1 clock source
.EQU  RCC_CFGR3_USART1SW_SYSCLK   , 1     @ System clock selected as USART1 clock source
.EQU  RCC_CFGR3_USART1SW_LSE      , 2     @ LSE oscillator clock used as USART1 clock source
.EQU  RCC_CFGR3_USART1SW_HSI      , 3     @ HSI oscillator clock used as USART1 clock source
.EQU  RCC_CFGR3_I2C1SW_N          , 4     @ Bit 4 I2C1SW: I2C1 clock source selection
.EQU  RCC_CFGR3_I2C1SW_HSI        , 0 << 4    @ 0: HSI clock selected as I2C1 clock source (defau
.EQU  RCC_CFGR3_I2C1SW_SYSCLK     , 1 << 4    @ 1: SYSCLK clock selected as I2C1 cloc
.EQU  RCC_CFGR3_I2C2SW_N          , 5     @ Bit 5 I2C2SW: I2C2 clock source selection (STM32F303xB/C/D/E, STM32F358
.EQU  RCC_CFGR3_I2C2SW_HSI        , 0 << 5    @  HSI oscillator clock used as I2C2 clock source */
.EQU  RCC_CFGR3_I2C2SW_SYSCLK     , 1 << 5    @  1: SYSCLK clock selected as I2C2 clock
.EQU  RCC_CFGR3_I2C3SW_N          , 6     @ Bit 6 I2C3SW: I2C3 clock source selection (STM32F303xB/C/D/E, STM32F358
.EQU  RCC_CFGR3_I2C3SW_HSI        , 0 << 6    @  HSI oscillator clock used as I2C3 clock source */
.EQU  RCC_CFGR3_I2C3SW_SYSCLK     , 1 << 6    @  1: SYSCLK clock selected as I2C3 clock
.EQU  RCC_CFGR3_TIM1SW_N          , 8     @ Bit 8 TIM1SW: Timer1 clock source selection
.EQU  RCC_CFGR3_TIM1SW_PCLK2      , 0 << 8    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM1SW_PLL        , 1 << 8    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_TIM8SW_N          , 9     @ Bit 9 TIM8SW: Timer8 clock source selection (STM32F303xB/C/D/E, STM32F3358xC and
.EQU  RCC_CFGR3_TIM8SW_PCLK2      , 0 << 9    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM8SW_PLL        , 1 << 9    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_TIM15SW_N         , 10    @ Bit 10 TIM15SW: Timer15 clock source selection
.EQU  RCC_CFGR3_TIM15SW_PCLK2     , 0 << 10    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM15SW_PLL       , 1 << 10    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_TIM16SW_N         , 11    @ Bit 11 TIM16SW: Timer16 clock source selection
.EQU  RCC_CFGR3_TIM16SW_PCLK2     , 0 << 11    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM16SW_PLL       , 1 << 11    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_TIM17SW_N         , 13    @ Bit 13 TIM17SW: Timer17 clock source selection
.EQU  RCC_CFGR3_TIM17SW_PCLK2     , 0 << 13    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM17SW_PLL       , 1 << 13    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_TIM20SW_N         , 15    @ Bit 15 TIM20SW: Timer20 clock source selection
.EQU  RCC_CFGR3_TIM20SW_PCLK2     , 0 << 15    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM20SW_PLL       , 1 << 15    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_USART2SW_N        , 16    @ Bits 17:16 USART2SW[1:0]: USART2 clock source selection
.EQU  RCC_CFGR3_USART2SW_PCLK     , 0x00 << 16    @ PCLK clock used as USART2 clock source
.EQU  RCC_CFGR3_USART2SW_SYSCLK   , 0x01 << 16    @ System clock selected as USART2 clock source
.EQU  RCC_CFGR3_USART2SW_LSE      , 0x10 << 16    @ LSE oscillator clock used as USART2 clock source
.EQU  RCC_CFGR3_USART2SW_HSI      , 0x11 << 16    @ HSI oscillator clock used as USART2 clock source
.EQU  RCC_CFGR3_USART3SW_N        , 18    @ Bits 19:18 USART3SW[1:0]: USART3 clock source selection
.EQU  RCC_CFGR3_USART3SW_PCLK     , 0x00 << 18    @ PCLK1 clock used as USART3 clock source
.EQU  RCC_CFGR3_USART3SW_SYSCLK   , 0x01 << 18    @ System clock selected as USART3 clock source
.EQU  RCC_CFGR3_USART3SW_LSE      , 0x10 << 18    @ LSE oscillator clock used as USART3 clock source
.EQU  RCC_CFGR3_USART3SW_HSI      , 0x11 << 18    @ HSI oscillator clock used as USART3 clock source
.EQU  RCC_CFGR3_USART4SW_N        , 20    @ Bits 21:20 UART4SW[1:0]: UART4 clock source selection (STM32F303xB/C/D/E, STM32F358xC and
.EQU  RCC_CFGR3_USART4SW_PCLK     , 0x00 << 20    @ PCLK clock used as USART4 clock source
.EQU  RCC_CFGR3_USART4SW_SYSCLK   , 0x01 << 20    @ System clock selected as USART4 clock source
.EQU  RCC_CFGR3_USART4SW_LSE      , 0x10 << 20    @ LSE oscillator clock used as USART4 clock source
.EQU  RCC_CFGR3_USART4SW_HSI      , 0x11 << 20    @ HSI oscillator clock used as USART4 clock source
.EQU  RCC_CFGR3_USART5SW_N        , 22    @ Bits 23:22 UART4SW[1:0]: UART5 clock source selection (STM32F303xB/C/D/E, STM32F358xC and
.EQU  RCC_CFGR3_USART5SW_PCLK     , 0x00 << 22    @ PCLK clock used as USART5 clock source
.EQU  RCC_CFGR3_USART5SW_SYSCLK   , 0x01 << 22    @ System clock selected as USART5 clock source
.EQU  RCC_CFGR3_USART5SW_LSE      , 0x10 << 22    @ LSE oscillator clock used as USART5 clock source
.EQU  RCC_CFGR3_USART5SW_HSI      , 0x11 << 22    @ HSI oscillator clock used as USART5 clock source
.EQU  RCC_CFGR3_TIM2SW_N          , 24    @ Bit 24 TIM2SW: Timer2 clock source selection
.EQU  RCC_CFGR3_TIM2SW_PCLK2      , 0 << 24    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM2SW_PLL        , 1 << 24    @ 1: PLL vco output (running up to 144 MHz)
.EQU  RCC_CFGR3_TIM34SW_N         , 25    @ Bit 25 TIM34SW: Timer34 clock source selection
.EQU  RCC_CFGR3_TIM34SW_PCLK2     , 0 << 25    @ 0: PCLK2 clock (doubled frequency when prescaled) (default)
.EQU  RCC_CFGR3_TIM34SW_PLL       , 1 << 25    @ 1: PLL vco output (running up to 144 MHz)
@.END

