@.CharSet=CP1251 (Cyrillic)
@GNU AS

@.desc type=module
@ +------------------------------------------------------------------+
@ |                    Áàçîâûå êîíñòàíòû SYSCFG                      |
@ |                         STM32FL100xxx                            |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.item APB2PERIPH_BASE
.equ SYSCFG_BASE                , APB2PERIPH_BASE + 0x3800

@.item SYSCFG_BASE
.equ SYSCFG_MEMRMP              , 0x00 @ SYSCFG memory remap register (SYSCFG_MEMRMP)
.equ SYSCFG_PMC                 , 0x04 @ SYSCFG peripheral mode configuration register (SYSCFG_PMC)
.equ SYSCFG_EXTICR1             , 0x08 @ SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
.equ SYSCFG_EXTICR2             , 0x0C @ SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)
.equ SYSCFG_EXTICR3             , 0x10 @ SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)
.equ SYSCFG_EXTICR4             , 0x14 @ SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
@.end

@.item SYSCFG_MEMRMP
.equ SYSCFG_MEMRMP_BOOT_MODE_N, 8      @ Bits 9:8 BOOT_MODE: Boot mode selected by the boot pins
                                       @ These bits are read only. They indicate the boot mode selected by the boot pins. Bit 9
                                       @ corresponds to the value sampled on the BOOT1 pin, and bit 8 corresponds to value sampled
                                       @ on the BOOT0 pin. See also Section 2.7: Boot configuration on page 50.
.equ SYSCFG_MEMRMP_BOOT_MODE_MAIN, 0   @ 00: Main Flash memory boot mode
.equ SYSCFG_MEMRMP_BOOT_MODE_SYS, 1<<8 @ 01: System Flash memory boot mode
                                       @ 10: Reserved
.equ SYSCFG_MEMRMP_BOOT_MODE_RAM, 3<<8 @ 11: Embedded SRAM boot mode
.equ SYSCFG_MEMRMP_MEM_MODE_N, 0       @ Bits 1:0 MEM_MODE: Memory mapping selection
                                       @ Set and cleared by software. This bit controls the memory’s internal mapping at address
                                       @ 0x0000 0000. After reset these bits take on the memory mapping selected by the BOOT pins.
.equ SYSCFG_MEMRMP_MEM_MODE_MAIN, 0    @ 00: Main Flash memory mapped at 0x0000 0000
.equ SYSCFG_MEMRMP_MEM_MODE_SYS, 1     @ 01: System Flash memory mapped at 0x0000 0000
.equ SYSCFG_MEMRMP_MEM_MODE_FSMC, 2    @ 10: FSMC
.equ SYSCFG_MEMRMP_MEM_MODE_RAM, 3     @ 11: SRAM mapped at 0x0000 0000
@.end

@.item SYSCFG_PMC
.equ SYSCFG_PMC_USB_PU_N         , 0   @ Bit 0 USB_PU USB pull-up enable on DP line
                                       @ Set and cleared by software. This bit controls the internal pull-up (1.5 k) on the USB DP line.
                                       @ 0: no pull-up on the USB DP line (even if USB is not in power down mode)
.equ SYSCFG_PMC_USB_PU, 1              @ 1: internal pull-up is connected on USB DP line (only if USB is not in power down mode)
.equ SYSCFG_PMC_LCD_CAPA_N, 1          @ Bit 5:1 LCD_CAPA decoupling capacitance connection (see device datasheet for this device
                                       @ capability)
                                       @ Bit 1 controls the connection of VLCDrail2 on PB2/LCD_VCAP2
                                       @         0: VLCDrail2 not connected to PB2/LCD_VCAP2
.equ SYSCFG_PMC_LCD_CAPA_VLCDrail2, 1<<1  @      1: VLCDrail2 connected to PB2/LCD_VCAP2
.equ SYSCFG_PMC_LCD_CAPA_VLCDrail1, 1<<2  @ Bit 2 controls the connection of VLCDrail1 on PB12/LCD_VCAP1
.equ SYSCFG_PMC_LCD_CAPA_VLCDrail3, 1<<3  @ Bit 3 controls the connection of VLCDrail3 on PB0/LCD_VCAP3
.equ SYSCFG_PMC_LCD_CAPA_VLCDrail1A, 1<<4 @ Bit 4 controls the connection of VLCDrail1 on PE11/LCD_VCAP1
.equ SYSCFG_PMC_LCD_CAPA_VLCDrail3A, 1<<5 @ Bit 5 controls the connection of VLCDrail3 on PE12/LCD_VCAP3
@.end

@.item SYSCFG_EXTICR1
@ Bits 15:0  EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
@ These bits are written by software to select the source input for the EXTIx external interrupt.
@ 0000: PA[x] pin
@ 0001: PB[x] pin
@ 0010: PC[x] pin
@ 0011: PD[x] pin
@ 0100: PE[x] pin
@ 0101: PH[x] (only PH[2:0], PH3 is not available)
@ 0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
@ 0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
.equ SYSCFG_EXTICR1_EXTI0_N     , 0
.equ SYSCFG_EXTICR1_EXTI1_N     , 4
.equ SYSCFG_EXTICR1_EXTI2_N     , 8
.equ SYSCFG_EXTICR1_EXTI3_N     , 12
@.end

@.item SYSCFG_EXTICR2
@ Bits 15:0  EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
@ These bits are written by software to select the source input for the EXTIx external interrupt.
@ 0000: PA[x] pin
@ 0001: PB[x] pin
@ 0010: PC[x] pin
@ 0011: PD[x] pin
@ 0100: PE[x] pin
@ 0101: PH[x] (only PH[2:0], PH3 is not available)
@ 0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
@ 0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
.equ SYSCFG_EXTICR2_EXTI4_N     , 0
.equ SYSCFG_EXTICR2_EXTI5_N     , 4
.equ SYSCFG_EXTICR2_EXTI6_N     , 8
.equ SYSCFG_EXTICR2_EXTI7_N     , 12
@.end

@.item SYSCFG_EXTICR3
@ Bits 15:0  EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
@ These bits are written by software to select the source input for the EXTIx external interrupt.
@ 0000: PA[x] pin
@ 0001: PB[x] pin
@ 0010: PC[x] pin
@ 0011: PD[x] pin
@ 0100: PE[x] pin
@ 0101: PH[x] (only PH[2:0], PH3 is not available)
@ 0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
@ 0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
.equ SYSCFG_EXTICR3_EXTI8_N     , 0
.equ SYSCFG_EXTICR3_EXTI9_N     , 4
.equ SYSCFG_EXTICR3_EXTI10_N    , 8
.equ SYSCFG_EXTICR3_EXTI11_N    , 12
@.end


@.item SYSCFG_EXTICR4
@ Bits 15:0  EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
@ These bits are written by software to select the source input for the EXTIx external interrupt.
@ 0000: PA[x] pin
@ 0001: PB[x] pin
@ 0010: PC[x] pin
@ 0011: PD[x] pin
@ 0100: PE[x] pin
@ 0101: PH[x] (only PH[2:0], PH3 is not available)
@ 0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
@ 0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)
.equ SYSCFG_EXTICR4_EXTI12_N    , 0
.equ SYSCFG_EXTICR4_EXTI13_N    , 4
.equ SYSCFG_EXTICR4_EXTI14_N    , 8
.equ SYSCFG_EXTICR4_EXTI15_N    , 12
@.end

@.item SYSCFG_EXTICR1 SYSCFG_EXTICR2 SYSCFG_EXTICR3 SYSCFG_EXTICR4
.equ SYSCFG_EXTICR_EXTI_PA    , 0
.equ SYSCFG_EXTICR_EXTI_PB    , 1
.equ SYSCFG_EXTICR_EXTI_PC    , 2
.equ SYSCFG_EXTICR_EXTI_PD    , 3
.equ SYSCFG_EXTICR_EXTI_PE    , 4
.equ SYSCFG_EXTICR_EXTI_PH    , 7
@.end


