@.CHARSET=CP1251

@ +------------------------------------------------------------------+
@ |                       Îðåäåëåíèÿ RCC (ðàçäåë 7)                  |
@ |                      STM32F030xxx \ STM32F070xxx                 |
@ +------------------------------------------------------------------+
.INCLUDE            "/src/inc/base.inc"

@.ITEM  AHB1PERIPH_BASE
.EQU  RCC_BASE           , AHB1PERIPH_BASE + 0x1000
.EQU  RCC                , PERIPH_BASE + RCC_BASE
@.END

@.ITEM     RCC RCC_BASE
.EQU  RCC_CR             , 0x00          @ Clock control register (RCC_CR)
.EQU  RCC_CFGR           , 0x04          @ Clock configuration register (RCC_CFGR)
.EQU  RCC_CIR            , 0x08          @ Clock interrupt register (RCC_CIR)
.EQU  RCC_APB2RSTR       , 0x0C          @ APB peripheral reset register 2 (RCC_APB2RSTR)
.EQU  RCC_APB1RSTR       , 0x10          @ APB peripheral reset register 1 (RCC_APB1RSTR)
.EQU  RCC_AHBENR         , 0x14          @ AHB peripheral clock enable register (RCC_AHBENR)
.EQU  RCC_APB2ENR        , 0x18          @ APB peripheral clock enable register 2 (RCC_APB2ENR)
.EQU  RCC_APB1ENR        , 0x1C          @ APB peripheral clock enable register 1 (RCC_APB1ENR)
.EQU  RCC_BDCR           , 0x20          @ RTC domain control register (RCC_BDCR)
.EQU  RCC_CSR            , 0x24          @ Control/status register (RCC_CSR)
.EQU  RCC_AHBRSTR        , 0x28          @ AHB peripheral reset register (RCC_AHBRSTR)
.EQU  RCC_CFGR2          , 0x2C          @ Clock configuration register 2 (RCC_CFGR2)
.EQU  RCC_CFGR3          , 0x30          @ Clock configuration register 3 (RCC_CFGR3)
.EQU  RCC_CR2            , 0x34          @ Clock control register 2 (RCC_CR2)
@.END

@.ITEM     RCC_CR
.EQU  RCC_CR_PLLRDY      , 1 << 25       @ PLL clock ready flag
                                        @ Set by hardware to indicate that the PLL is locked
                                        @ 0: PLL unlocked
                                        @ 1: PLL locked
.EQU  RCC_CR_PLLON       , 1 << 24       @ PLL enable
                                        @ 0: PLL OFF
                                        @ 1: PLL ON
.EQU  RCC_CR_CSSON       , 1 << 19       @ Clock security system enable
                                        @ 0: Clock security system disabled (clock detector OFF)
                                        @ 1: Clock security system enabled (clock detector ON if the HSE is ready, OFF in not)
.EQU  RCC_CR_HSEBYP      , 1 << 18       @ HSE crystal oscillator bypass
                                        @ 0: HSE crystal oscillator not bypassed
                                        @ 1: HSE crystal oscillator bypassed with external clock
.EQU  RCC_CR_HSERDY      , 1 << 17       @ HSE clock ready flag
                                        @ 0: HSE oscillator not ready
                                        @ 1: HSE oscillator ready
.EQU  RCC_CR_HSEON       , 1 << 16       @ HSE clock enable
                                        @ 0: HSE oscillator OFF
                                        @ 1: HSE oscillator ON
.EQU  RCC_CR_HSICAL_M    , 0x0000FF00    @ HSI clock calibration HSICAL[7:0]
.EQU  RCC_CR_HSITRIM_N   , 3             @ HSI clock trimming HSITRIM[4:0]
.EQU  RCC_CR_HSIRDY      , 1 << 1        @ HSI clock ready flag
                                        @ 0: HSI oscillator not ready
                                        @ 1: HSI oscillator ready
.EQU  RCC_CR_HSION       , 1 << 0        @ HSI clock enable
                                        @ 0: HSI oscillator OFF
                                        @ 1: HSI oscillator ON
@.END

@.ITEM     RCC_CFGR
.EQU  RCC_CFGR_PLLNODIV  , 1 << 31       @ PLL clock not divided for MCO (not avaiable on STM32F030x8 devices)
                                        @ 0: PLL is divided by 2 for MCO
                                        @ 1: PLL is not divided for MCO
.EQU  RCC_CFGR_MCOPRE_N  , 28            @ MCOPRE[2:0] Microcontroller Clock Output Prescaller (not avaiable on STM32F030x8)
.EQU  RCC_CFGR_MCOPRE1   , 0x00 << 28    @ MCO is divided by 1
.EQU  RCC_CFGR_MCOPRE2   , 0x01 << 28    @ MCO is divided by 2
.EQU  RCC_CFGR_MCOPRE4   , 0x02 << 28    @ MCO is divided by 4
.EQU  RCC_CFGR_MCOPRE8   , 0x03 << 28    @ MCO is divided by 8
.EQU  RCC_CFGR_MCOPRE16  , 0x04 << 28    @ MCO is divided by 16
.EQU  RCC_CFGR_MCOPRE32  , 0x05 << 28    @ MCO is divided by 32
.EQU  RCC_CFGR_MCOPRE64  , 0x06 << 28    @ MCO is divided by 64
.EQU  RCC_CFGR_MCOPRE128 , 0x07 << 28    @ MCO is divided by 128
.EQU  RCC_CFGR_MCO_N     , 24            @ Microcontroller clock output MCO[3:0]
.EQU  RCC_CFGR_MCO0      , 0x00 << 24    @ 0000: MCO output disabled, no clock on MCO
.EQU  RCC_CFGR_MCO1      , 0x01 << 24    @ 0001: Internal RC 14MHz (HSI14) oscillator clock selected
.EQU  RCC_CFGR_MCO2      , 0x02 << 24    @ 0010: Internal low speed (LSI) oscillator clock selected
.EQU  RCC_CFGR_MCO3      , 0x03 << 24    @ 0011: External low speed (LSE) oscillator clock selected
.EQU  RCC_CFGR_MCO4      , 0x04 << 24    @ 0100: System clock selected
.EQU  RCC_CFGR_MCO5      , 0x05 << 24    @ 0101: Internal RC 8MHz (HSI) oscillator clock selected
.EQU  RCC_CFGR_MCO6      , 0x06 << 24    @ 0110: External 4-32MHZ (HSE) oscillator clock selected
.EQU  RCC_CFGR_MCO7      , 0x07 << 24    @ 0111: PLL clock selected (divided by 1 or 2, depending on PLLNODIV)
.EQU  RCC_CFGR_PLLMUL_N  , 18            @ PLL multiplication factor PLLMUL[3:0]
.EQU  RCC_CFGR_PLLMUL0   , 0x00 << 18    @ 0000: PLL input clock x2
.EQU  RCC_CFGR_PLLMUL1   , 0x01 << 18    @ 0001: PLL input clock x3
.EQU  RCC_CFGR_PLLMUL2   , 0x02 << 18    @ 0010: PLL input clock x4
.EQU  RCC_CFGR_PLLMUL3   , 0x03 << 18    @ 0011: PLL input clock x5
.EQU  RCC_CFGR_PLLMUL4   , 0x04 << 18    @ 0100: PLL input clock x6
.EQU  RCC_CFGR_PLLMUL5   , 0x05 << 18    @ 0101: PLL input clock x7
.EQU  RCC_CFGR_PLLMUL6   , 0x06 << 18    @ 0110: PLL input clock x8
.EQU  RCC_CFGR_PLLMUL7   , 0x07 << 18    @ 0111: PLL input clock x9
.EQU  RCC_CFGR_PLLMUL8   , 0x08 << 18    @ 1000: PLL input clock x10
.EQU  RCC_CFGR_PLLMUL9   , 0x09 << 18    @ 1001: PLL input clock x11
.EQU  RCC_CFGR_PLLMUL10  , 0x0A << 18    @ 1010: PLL input clock x12
.EQU  RCC_CFGR_PLLMUL11  , 0x0B << 18    @ 1011: PLL input clock x13
.EQU  RCC_CFGR_PLLMUL12  , 0x0C << 18    @ 1100: PLL input clock x14
.EQU  RCC_CFGR_PLLMUL13  , 0x0D << 18    @ 1101: PLL input clock x15
.EQU  RCC_CFGR_PLLMUL14  , 0x0E << 18    @ 1110: PLL input clock x16
.EQU  RCC_CFGR_PLLMUL15  , 0x0F << 18    @ 1111: PLL input clock x16
.EQU  RCC_CFGR_PLLXTPRE  , 1 << 17       @ HSE divider for PLL input clock
                                        @ This bit is the same bit as bit PREDIV[0] from RCC_CFGR2.
                                        @ Refer to RCC_CFGR2 PREDIV bits description for its meaning
.EQU  RCC_CFGR_PLLSRC    , 1 << 16       @ PLL entry clock source
                                        @ 0: HSI/2 selected as PLL input clock
                                        @ 1: HSE/PREDIV selected as PLL input clock
.EQU  RCC_CFGR_ADCPRE    , 1 << 14       @ ADC prescaler
                                        @ Obsolete setting. Proper ADC clock selection is done inside the ADC_CFGR2
.EQU  RCC_CFGR_PPRE_N    , 8             @ PCLK prescaler PPRE[2:0]
.EQU  RCC_CFGR_PPRE0     , 0x00 << 8     @ HCLK not divided
.EQU  RCC_CFGR_PPRE2     , 0x04 << 8     @ HCLK divided by 2
.EQU  RCC_CFGR_PPRE4     , 0x05 << 8     @ HCLK divided by 4
.EQU  RCC_CFGR_PPRE8     , 0x06 << 8     @ HCLK divided by 8
.EQU  RCC_CFGR_PPRE16    , 0x07 << 8     @ HCLK divided by 16
.EQU  RCC_CFGR_HPRE_N    , 4             @ HCLK prescaler HPRE[3:0]
.EQU  RCC_CFGR_HPRE0     , 0x00 << 4     @ SYSCLK not divided
.EQU  RCC_CFGR_HPRE2     , 0x08 << 4     @ SYSCLK divided by 2
.EQU  RCC_CFGR_HPRE4     , 0x09 << 4     @ SYSCLK divided by 4
.EQU  RCC_CFGR_HPRE8     , 0x0A << 4     @ SYSCLK divided by 8
.EQU  RCC_CFGR_HPRE16    , 0x0B << 4     @ SYSCLK divided by 16
.EQU  RCC_CFGR_HPRE64    , 0x0C << 4     @ SYSCLK divided by 64
.EQU  RCC_CFGR_HPRE128   , 0x0D << 4     @ SYSCLK divided by 128
.EQU  RCC_CFGR_HPRE256   , 0x0E << 4     @ SYSCLK divided by 256
.EQU  RCC_CFGR_HPRE512   , 0x0F << 4     @ SYSCLK divided by 512
.EQU  RCC_CFGR_SWS_N     , 2             @ System clock switch status SWS[1:0]
.EQU  RCC_CFGR_SWS0      , 0x00 << 2     @ 00: HSI oscillator used as system clock
.EQU  RCC_CFGR_SWS1      , 0x01 << 2     @ 01: HSE oscillator used as system clock
.EQU  RCC_CFGR_SWS2      , 0x02 << 2     @ 10: PLL used as system clock
.EQU  RCC_CFGR_SWS3      , 0x03 << 2     @ 11: Reserved, must be kept at reset value
.EQU  RCC_CFGR_SW_N      , 0             @ System clock switch SW[1:0]
.EQU  RCC_CFGR_SW0       , 0x00 << 0     @ 00: HSI selected as system clock
.EQU  RCC_CFGR_SW1       , 0x01 << 0     @ 01: HSE selected as system clock
.EQU  RCC_CFGR_SW2       , 0x02 << 0     @ 10: PLL selected as system clock
.EQU  RCC_CFGR_SW3       , 0x03 << 0     @ 11: Reserved, must be kept at reset value
@.END

@.ITEM     RCC_CIR
.EQU  RCC_CIR_CSSC       , 1 << 23       @ Clock security system interrupt clear (CSSF flag)
                                        @ 0: No effect
                                        @ 1: Clear CSSF flag
.EQU  RCC_CIR_HSI14RDYC  , 1 << 21       @ HSI14 ready interrupt clear
                                        @ 0: No effect
                                        @ 1: Clear HSI14RDYF flag
.EQU  RCC_CIR_PLLRDYC    , 1 << 20       @ PLL ready interrupt clear
                                        @ 0: No effect
                                        @ 1: Clear PLLRDYF flag
.EQU  RCC_CIR_HSERDYC    , 1 << 19       @ HSE ready interrupt clear
                                        @ 0: No effect
                                        @ 1: Clear HSERDYF flag
.EQU  RCC_CIR_HSIRDYC    , 1 << 18       @ HSI ready interrupt clear
                                        @ 0: No effect
                                        @ 1: Clear HSIRDYF flag
.EQU  RCC_CIR_LSERDYC    , 1 << 17       @ LSE ready interrupt clear
.EQU  RCC_CIR_LSIRDYC    , 1 << 16       @ LSI ready interrupt clear
.EQU  RCC_CIR_HSI14RDYIE , 1 << 13       @ HSI14 ready interrupt enable 0: disable 1: enable
.EQU  RCC_CIR_PLLRDYIE   , 1 << 12       @ PLL ready interrupt enable 0: disable 1: enable
.EQU  RCC_CIR_HSERDYIE   , 1 << 11       @ HSE ready interrupt enable 0: disable 1: enable
.EQU  RCC_CIR_HSIRDYIE   , 1 << 10       @ HSI ready interrupt enable 0: disable 1: enable
.EQU  RCC_CIR_LSERDYIE   , 1 << 9        @ LSE ready interrupt enable 0: disable 1: enable
.EQU  RCC_CIR_LSIRDYIE   , 1 << 8        @ LSI ready interrupt enable 0: disable 1: enable
.EQU  RCC_CIR_CSSF       , 1 << 7        @ Clock security system interrupt flag
                                        @ 0: No clock security interrupt caused by HSE clock failure
                                        @ 1: Clock security interrupt caused by HSE clock failure
.EQU  RCC_CIR_HSI14RDYF  , 1 << 5        @ HSI14 ready interrupt flag
.EQU  RCC_CIR_PLLRDYF    , 1 << 4        @ PLL ready interrupt flag
.EQU  RCC_CIR_HSERDYF    , 1 << 3        @ HSE ready interrupt flag
.EQU  RCC_CIR_HSIRDYF    , 1 << 2        @ HSI ready interrupt flag
.EQU  RCC_CIR_LSERDYF    , 1 << 1        @ LSE ready interrupt flag
.EQU  RCC_CIR_LSIRDYF    , 1 << 0        @ LSI ready interrupt flag
@.END

@.ITEM     RCC_APB2RSTR
.EQU  RCC_APB2RSTR_DBGMCURST, 1 << 22    @ Debug MCU reset 0: No effect 1: Reset Debug MCU
.EQU  RCC_APB2RSTR_TIM17RST, 1 << 18     @ TIM17 timer reset  0: No effect 1: Reset TIM17
.EQU  RCC_APB2RSTR_TIM16RST, 1 << 17     @ TIM16 timer reset  0: No effect 1: Reset TIM16
.EQU  RCC_APB2RSTR_TIM15RST, 1 << 16     @ TIM16 timer reset  0: No effect 1: Reset TIM15
.EQU  RCC_APB2RSTR_USART1RST, 1 << 14    @ USART1 reset  0: No effect 1: Reset
.EQU  RCC_APB2RSTR_SPI1RST, 1 << 12      @ SPI1 reset 0: No effect 1: Reset
.EQU  RCC_APB2RSTR_TIM1RST, 1 << 11      @ TIM1 timer reset  0: No effect 1: Reset TIM1
.EQU  RCC_APB2RSTR_ADCRST, 1 << 9        @ ADC interface reset
.EQU  RCC_APB2RSTR_USART6RST, 1 << 5     @ USART6 reset
.EQU  RCC_APB2RSTR_SYSCFGRST, 1 << 0     @ SYSCFG reset
@.END

@.ITEM     RCC_APB1RSTR
.EQU  RCC_APB1RSTR_PWRRST, 1 << 28       @ Power interface reset 0: No effect 1: Reset
.EQU  RCC_APB1RSTR_USBRST, 1 << 23       @ USB interface reset
.EQU  RCC_APB1RSTR_I2C2RST, 1 << 22      @ I2C2 reset
.EQU  RCC_APB1RSTR_I2C1RST, 1 << 21      @ I2C1 reset
.EQU  RCC_APB1RSTR_USART5RST, 1 << 20    @ USART5 reset
.EQU  RCC_APB1RSTR_USART4RST, 1 << 19    @ USART4 reset
.EQU  RCC_APB1RSTR_USART3RST, 1 << 18    @ USART3 reset
.EQU  RCC_APB1RSTR_USART2RST, 1 << 17    @ USART2 reset
.EQU  RCC_APB1RSTR_SPI2RST, 1 << 14      @ SPI2 reset
.EQU  RCC_APB1RSTR_WWDGRST, 1 << 11      @ Window watchdog reset
.EQU  RCC_APB1RSTR_TIM14RST, 1 << 8      @ TIM14 timer reset
.EQU  RCC_APB1RSTR_TIM7RST, 1 << 5       @ TIM7 timer reset
.EQU  RCC_APB1RSTR_TIM6RST, 1 << 4       @ TIM6 timer reset
.EQU  RCC_APB1RSTR_TIM3RST, 1 << 1       @ TIM3 timer reset
@.END

@.ITEM     RCC_AHBENR
.EQU  RCC_AHBENR_IOPFEN  , 1 << 22       @ I/O Port F clock enable  0: disabled  1: enabled
.EQU  RCC_AHBENR_IOPDEN  , 1 << 20       @ I/O Port D clock enable  0: disabled  1: enabled
.EQU  RCC_AHBENR_IOPCEN  , 1 << 19       @ I/O Port C clock enable  0: disabled  1: enabled
.EQU  RCC_AHBENR_IOPBEN  , 1 << 18       @ I/O Port B clock enable  0: disabled  1: enabled
.EQU  RCC_AHBENR_IOPAEN  , 1 << 17       @ I/O Port A clock enable  0: disabled  1: enabled
.EQU  RCC_AHBENR_CRCEN   , 1 << 6        @ CRC clock enable  0: disabled  1: enabled
.EQU  RCC_AHBENR_FLITFEN , 1 << 4        @ FLITF clock enable  0: disabled  1: enabled during Sleep mode
.EQU  RCC_AHBENR_SRAMEN  , 1 << 2        @ SRAM interface clock enable  0: disabled  1: enabled during Sleep mode
.EQU  RCC_AHBENR_DMAEN   , 1 << 0        @ DMA clock enable  0: disabled  1: enabled
@.END

@.ITEM     RCC_APB2ENR
.EQU  RCC_APB2ENR_DBGMCUEN, 1 << 22      @ MCU debug module clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_TIM17EN, 1 << 18       @ TIM17 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_TIM16EN, 1 << 17       @ TIM16 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_TIM15EN, 1 << 16       @ TIM15 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_USART1EN, 1 << 14      @ USART1 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_SPI1EN , 1 << 12       @ SPI1 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_TIM1EN , 1 << 11       @ TIM1 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_ADCEN  , 1 << 9        @ ADC interface clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_USART6EN, 1 << 5       @ USART6 clock enable  0: disabled  1: enabled
.EQU  RCC_APB2ENR_SYSCFGEN, 1 << 0       @ SYSCFG clock enable  0: disabled  1: enabled
@.END

@.ITEM     RCC_APB1ENR
.EQU  RCC_APB1ENR_PWREN  , 1 << 28       @ Power interface clock enable
.EQU  RCC_APB1ENR_USBEN  , 1 << 23       @ USB interface clock enable
.EQU  RCC_APB1ENR_I2C2EN , 1 << 22       @ I2C2 clock enable
.EQU  RCC_APB1ENR_I2C1EN , 1 << 21       @ I2C1 clock enable
.EQU  RCC_APB1ENR_USART5EN, 1 << 20      @ USART5 clock enable
.EQU  RCC_APB1ENR_USART4EN, 1 << 19      @ USART4 clock enable
.EQU  RCC_APB1ENR_USART3EN, 1 << 18      @ USART3 clock enable
.EQU  RCC_APB1ENR_USART2EN, 1 << 17      @ USART2 clock enable
.EQU  RCC_APB1ENR_SPI2EN , 1 << 14       @ SPI2 clock enable
.EQU  RCC_APB1ENR_WWDGEN , 1 << 11       @ Window watchdog clock enable
.EQU  RCC_APB1ENR_TIM14EN, 1 << 8        @ TIM14 timer clock enable
.EQU  RCC_APB1ENR_TIM7EN , 1 << 5        @ TIM7 timer clock enable
.EQU  RCC_APB1ENR_TIM6EN , 1 << 4        @ TIM6 timer clock enable
.EQU  RCC_APB1ENR_TIM3EN , 1 << 1        @ TIM3 timer clock enable
@.END

@.ITEM     RCC_BDCR
.EQU  RCC_BDCR_BDRST     , 1 << 16       @ RTC domain software reset
.EQU  RCC_BDCR_RTCEN     , 1 << 15       @ RTC clock enable
.EQU  RCC_BDCR_RTCSEL_N  , 8             @ RTC clock source selection
.EQU  RCC_BDCR_RTCSEL0   , 0x00 << 8     @ 00: No clock
.EQU  RCC_BDCR_RTCSEL1   , 0x01 << 8     @ 01: LSE oscillator clock used as RTC clock
.EQU  RCC_BDCR_RTCSEL2   , 0x02 << 8     @ 10: LSI oscillator clock used as RTC clock
.EQU  RCC_BDCR_RTCSEL3   , 0x03 << 8     @ 11: HSE oscillator clock divided by 32 used as RTC clock
.EQU  RCC_BDCR_LSEDRV_N  , 3             @ LSE oscillator drive capability
.EQU  RCC_BDCR_LSEDRV0   , 0x00 << 3     @ 00: ‘Xtal mode’ lower driving capability
.EQU  RCC_BDCR_LSEDRV1   , 0x01 << 3     @ 01: ‘Xtal mode’ medium high driving capability
.EQU  RCC_BDCR_LSEDRV2   , 0x02 << 3     @ 10: ‘Xtal mode’ medium low driving capability
.EQU  RCC_BDCR_LSEDRV3   , 0x03 << 3     @ 11: ‘Xtal mode’ higher driving capability (reset value)
.EQU  RCC_BDCR_LSEBYP    , 1 << 2        @ LSE oscillator bypass
                                        @ 0: LSE oscillator not bypassed
                                        @ 1: LSE oscillator bypassed
.EQU  RCC_BDCR_LSERDY    , 1 << 1        @ LSE oscillator ready
                                        @ 0: LSE oscillator not ready
                                        @ 1: LSE oscillator ready
.EQU  RCC_BDCR_LSEON     , 1 << 0        @ LSE oscillator enable
@.END

@.ITEM     RCC_CSR
.EQU  RCC_CSR_LPWRRSTF   , 1 << 31       @ Low-power reset flag
                                        @ 0: No Low-power management reset occurred
                                        @ 1: Low-power management reset occurred
.EQU  RCC_CSR_WWDGRSTF   , 1 << 30       @ Window watchdog reset flag
                                        @ 0: No window watchdog reset occurred
                                        @ 1: Window watchdog reset occurred
.EQU  RCC_CSR_IWDGRSTF   , 1 << 29       @ Independent watchdog reset flag
.EQU  RCC_CSR_SFTRSTF    , 1 << 28       @ Software reset flag
.EQU  RCC_CSR_PORRSTF    , 1 << 27       @ POR/PDR reset flag
.EQU  RCC_CSR_PINRSTF    , 1 << 26       @ Pin reset flag
                                        @ Set by hardware when a reset from the NRST pin occurs.
                                        @ Cleared by writing to the RMVF bit.
                                        @ 0: No reset from NRST pin occurred
                                        @ 1: Reset from NRST pin occurred
.EQU  RCC_CSR_OBLRSTF    , 1 << 25       @ Option byte loader reset flag
.EQU  RCC_CSR_RMVF       , 1 << 24       @ Remove reset flag
.EQU  RCC_CSR_V18PWRRSTF , 1 << 23       @ Reset flag of the 1.8 V domain.
                                        @ Set by hardware when a POR/PDR of the 1.8 V domain occurred.
                                        @ Cleared by writing to the RMVF bit.
                                        @ 0: No POR/PDR reset of the 1.8 V domain occurred
                                        @ 1: POR/PDR reset of the 1.8 V domain occurred
.EQU  RCC_CSR_LSIRDY     , 1 << 1        @ LSI oscillator ready
.EQU  RCC_CSR_LSION      , 1 << 0        @ LSI oscillator enable
@.END

@.ITEM     RCC_AHBRSTR
.EQU  RCC_AHBRSTR_IOPFRST, 1 << 22       @ I/O port F reset
.EQU  RCC_AHBRSTR_IOPDRST, 1 << 20       @ I/O port D reset
.EQU  RCC_AHBRSTR_IOPCRST, 1 << 19       @ I/O port C reset
.EQU  RCC_AHBRSTR_IOPBRST, 1 << 18       @ I/O port B reset
.EQU  RCC_AHBRSTR_IOPARST, 1 << 17       @ I/O port A reset
@.END

@.ITEM     RCC_CFGR2
.EQU  RCC_CFGR2_PREDIV_N , 0             @ PREDIV[3:0] PREDIV division factor
.EQU  RCC_CFGR2_PREDIV0  , 0x00 << 0     @ 0000: PREDIV input clock not divided
.EQU  RCC_CFGR2_PREDIV1  , 0x01 << 0     @ 0001: PREDIV input clock divided by 2
.EQU  RCC_CFGR2_PREDIV2  , 0x02 << 0     @ 0010: PREDIV input clock divided by 3
.EQU  RCC_CFGR2_PREDIV3  , 0x03 << 0     @ 0011: PREDIV input clock divided by 4
.EQU  RCC_CFGR2_PREDIV4  , 0x04 << 0     @ 0100: PREDIV input clock divided by 5
.EQU  RCC_CFGR2_PREDIV5  , 0x05 << 0     @ 0101: PREDIV input clock divided by 6
.EQU  RCC_CFGR2_PREDIV6  , 0x06 << 0     @ 0110: PREDIV input clock divided by 7
.EQU  RCC_CFGR2_PREDIV7  , 0x07 << 0     @ 0111: PREDIV input clock divided by 8
.EQU  RCC_CFGR2_PREDIV8  , 0x08 << 0     @ 1000: PREDIV input clock divided by 9
.EQU  RCC_CFGR2_PREDIV9  , 0x09 << 0     @ 1001: PREDIV input clock divided by 10
.EQU  RCC_CFGR2_PREDIV10 , 0x0A << 0     @ 1010: PREDIV input clock divided by 11
.EQU  RCC_CFGR2_PREDIV11 , 0x0B << 0     @ 1011: PREDIV input clock divided by 12
.EQU  RCC_CFGR2_PREDIV12 , 0x0C << 0     @ 1100: PREDIV input clock divided by 13
.EQU  RCC_CFGR2_PREDIV13 , 0x0D << 0     @ 1101: PREDIV input clock divided by 14
.EQU  RCC_CFGR2_PREDIV14 , 0x0E << 0     @ 1110: PREDIV input clock divided by 15
.EQU  RCC_CFGR2_PREDIV15 , 0x0F << 0     @ 1111: PREDIV input clock divided by 16
@.END

@.ITEM     RCC_CFGR3
.EQU  RCC_CFGR3_ADCSW    , 1 << 8        @ ADC clock source selection
                                        @ Obsolete setting. To be kept at reset value, connecting the HSI14 clock to the ADC
                                        @ asynchronous clock input. Proper ADC clock selection is done inside the ADC_CFGR2
.EQU  RCC_CFGR3_USBSW    , 1 << 7        @ USB clock source selection
                                        @ This bit is set and cleared by software to select the USB clock source.
                                        @ 0: USB clock disabled (default)
                                        @ 1: PLL clock (PLLCLK) selected as USB clock
.EQU  RCC_CFGR3_I2C1SW   , 1 << 4        @ I2C1 clock source selection
                                        @ This bit is set and cleared by software to select the I2C1 clock source.
                                        @ 0: HSI clock selected as I2C1 clock source (default)
                                        @ 1: System clock (SYSCLK) selected as I2C1 clock
.EQU  RCC_CFGR3_USART1SW_N, 0            @ USART1 clock source selection
.EQU  RCC_CFGR3_USART1SW0, 0x00 << 0     @ 00: PCLK selected as USART1 clock source (default)
.EQU  RCC_CFGR3_USART1SW1, 0x01 << 0     @ 01: System clock (SYSCLK) selected as USART1 clock
.EQU  RCC_CFGR3_USART1SW2, 0x02 << 0     @ 10: LSE clock selected as USART1 clock
.EQU  RCC_CFGR3_USART1SW3, 0x03 << 0     @ 11: HSI clock selected as USART1 clock
@.END

@.ITEM     RCC_CR2
.EQU  RCC_CR2_HSI14CAL_M , 0xFF000000    @ HSI14 clock calibration. These bits are initialized automatically at startup.
.EQU  RCC_CR2_HSI14TRIM_N, 3             @ HSI14 clock trimming  HSI14TRIM[4:0]
.EQU  RCC_CR2_HSI14DIS   , 1 << 2        @ HSI14 clock request from ADC disable
                                        @ When set this bit prevents the ADC interface from enabling the HSI14 oscillator.
                                        @ 0: ADC interface can turn on the HSI14 oscillator
                                        @ 1: ADC interface can not turn on the HSI14 oscillator
.EQU  RCC_CR2_HSI14RDY   , 1 << 1        @ HSI14 clock ready flag
                                        @ 0: HSI14 oscillator not ready
                                        @ 1: HSI14 oscillator ready
.EQU  RCC_CR2_HSI14ON    , 1 << 0        @ HSI14 clock enable
                                        @ 0: HSI14 oscillator OFF
                                        @ 1: HSI14 oscillator ON
@.END




