@GNU AS
@.CHARSET =CP1251 ( Cyrillic )

@.DESC     type=module
@ +------------------------------------------------------------------+
@ |               Константы  System control block ( SCB )            |
@ |                           Cortex-M4 Core                         |
@ +------------------------------------------------------------------+
@.ENDDESC

.include    "/src/inc/base.inc"

@.ITEM     SCB_BASE
.EQU  SCB_CPUID     , 0x00         @ (R)  CPUID Base Register
.EQU  SCB_ICSR      , 0x04         @ (R/W)  Interrupt Control and State Register
.EQU  SCB_VTOR      , 0x08         @ (R/W)  Vector Table Offset Register
.EQU  SCB_AIRCR     , 0x0C         @ (R/W)  Application Interrupt and Reset Control Register
.EQU  SCB_SCR       , 0x10         @ (R/W)  System Control Register
.EQU  SCB_CCR       , 0x14         @ (R/W)  Configuration Control Register
.EQU  SCB_SHPR1     , 0x18         @ (R/W)  System Handlers Priority Registers
.EQU  SCB_SHPR2     , 0x1C         @
.EQU  SCB_SHPR3     , 0x20         @
.EQU  SCB_SHCSR     , 0x24         @ (R/W)  System Handler Control and State Register
.EQU  SCB_CFSR      , 0x28         @ (R/W)  Configurable Fault Status Register
.EQU  SCB_HFSR      , 0x2C         @ (R/W)  HardFault Status Register
.EQU  SCB_DFSR      , 0x30         @ (R/W)  Debug Fault Status Register
.EQU  SCB_MMFAR     , 0x34         @ (R/W)  MemManage Fault Address Register
.EQU  SCB_BFAR      , 0x38         @ (R/W)  BusFault Address Register
.EQU  SCB_AFSR      , 0x3C         @ (R/W)  Auxiliary Fault Status Register
.EQU  SCB_PFR0      , 0x40         @ (R)  Processor Feature Register0
.EQU  SCB_PFR1      , 0x44         @ (R)  Processor Feature Register1
.EQU  SCB_DFR0      , 0x48         @ (R)  Debug Feature Register
.EQU  SCB_AFR0      , 0x4C         @ (R)  Auxiliary Feature Register
.EQU  SCB_MMFR0     , 0x50         @ (R)  Memory Model Feature Register0
.EQU  SCB_MMFR1     , 0x54         @ (R)  Memory Model Feature Register1
.EQU  SCB_MMFR2     , 0x58         @ (R)  Memory Model Feature Register2
.EQU  SCB_MMFR3     , 0x5C         @ (R)  Memory Model Feature Register3
.EQU  SCB_ISAR0     , 0x60         @ (R)  Instruction Set Attributes Register0
.EQU  SCB_ISAR1     , 0x64         @ (R)  Instruction Set Attributes Register1
.EQU  SCB_ISAR2     , 0x68         @ (R)  Instruction Set Attributes Register2
.EQU  SCB_ISAR3     , 0x6C         @ (R)  Instruction Set Attributes Register3
.EQU  SCB_ISAR4     , 0x70         @ (R)  Instruction Set Attributes Register4
.EQU  SCB_CPACR     , 0x88         @ (R/W)  Coprocessor Access Control Register
.EQU  SCB_STIR      , 0x100        @ (W)  Software Triggered Interrupt Register
@.END


@.ITEM     SCB_CPUID
.equ SCB_CPUID_ResetValue       , 0x410FC241                        @ Значение после сброса
.equ SCB_CPUID_IMPLEMENTER_N    , 24
.equ SCB_CPUID_IMPLEMENTER_M    , 0xFF << SCB_CPUID_IMPLEMENTER_N   @ Bits 31:24 Implementer code
.equ SCB_CPUID_IMPLEMENTER_arm_code , 0x41 << SCB_CPUID_IMPLEMENTER_N  @ 0x41: код Arm
.equ SCB_CPUID_VARIANT_N        , 20
.equ SCB_CPUID_VARIANT_M        , 0xF << SCB_CPUID_VARIANT_N        @ Bits 23:20 Variant number. The r value in the rnpn product revision identifier
.equ SCB_CPUID_CONSTANT_N       , 16
.equ SCB_CPUID_CONSTANT_M       , 0xF << SCB_CPUID_CONSTANT_N       @ Bits 19:16 Constant: Reads as 0xF
.equ SCB_CPUID_PARTNO_N         , 4
.equ SCB_CPUID_PARTNO_M         , 0xFFF << SCB_CPUID_PARTNO_N       @ Bits 15:4 PartNo: Part number of the processor.
.equ SCB_CPUID_PARTNO_Cortex_M3 , 0xC23 << SCB_CPUID_PARTNO_N       @ Код Cortex-M3
.equ SCB_CPUID_PARTNO_Cortex_M4 , 0xC24 << SCB_CPUID_PARTNO_N       @ Код Cortex-M4
.equ SCB_CPUID_REVISION_N       , 0
.equ SCB_CPUID_REVISION_M       , 0xF << SCB_CPUID_REVISION_N       @ Bits 3:0 Revision: Revision number. The p value in the rnpn product revision identifier, indicates patch release.                                                                    @    0x1: = patch 1
@.END


@.ITEM     SCB_ICSR
.equ SCB_ICSR_Reset_Value      , 0                           @ Значение после сброса
.equ SCB_ICSR_NMIPENDSET_N     , 31
.equ SCB_ICSR_NMIPENDSET       , 1 << SCB_ICSR_NMIPENDSET_N  @ Bit 31 NMI set-pending bit.
                                                             @ Write:
                                                             @   0: No effect
                                                             @   1: Change NMI exception state to pending.
                                                             @ Read:
                                                             @   0: NMI exception is not pending
                                                             @   1: NMI exception is pending
.equ SCB_ICSR_PENDSVSET_N      , 28
.equ SCB_ICSR_PENDSVSET        , 1 << SCB_ICSR_PENDSVSET_N   @ Bit 28 PendSV set-pending bit. Writing 1 to this bit is the only way to set the PendSV exception state to pending.
                                                             @ Write:
                                                             @   0: No effect
                                                             @   1: Change PendSV exception state to pending.
                                                             @ Read:
                                                             @   0: PendSV exception is not pending
                                                             @   1: PendSV exception is pending

.equ SCB_ICSR_PENDSVCLR_N      , 27
.equ SCB_ICSR_PENDSVCLR        , 1 << SCB_ICSR_PENDSVCLR_N   @ Bit 27 PendSV clear-pending bit. This bit is write-only. On a read, value is unknown.
                                                             @ Write:
                                                             @   0: No effect
                                                             @   1: Removes the pending state from the PendSV exception.
.equ SCB_ICSR_PENDSTSET_N      , 26
.equ SCB_ICSR_PENDSTSET        , 1 << SCB_ICSR_PENDSTSET_N   @ Bit 26 SysTick exception set-pending bit.
                                                             @ Write:
                                                             @   0: No effect
                                                             @   1: Change SysTick exception state to pending
                                                             @ Read:
                                                             @   0: SysTick exception is not pending
                                                             @   1: SysTick exception is pending
.equ SCB_ICSR_PENDSTCLR_N      , 25
.equ SCB_ICSR_PENDSTCLR        , 1 << SCB_ICSR_PENDSTCLR_N   @ Bit 25 SysTick exception clear-pending bit. Write-only. On a read, value is unknown.
                                                             @ Write:
                                                             @   0: No effect
                                                             @   1: Removes the pending state from the SysTick exception.
.equ SCB_ICSR_ISRPREEMPT_N     , 23
.equ SCB_ICSR_ISRPREEMPT       , 1 << SCB_ICSR_ISRPREEMPT_N  @ Bit 23 This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
.equ SCB_ICSR_ISRPENDING_N     , 22
.equ SCB_ICSR_ISRPENDING       , 1 << SCB_ICSR_ISRPENDING_N  @ Bit 22 Interrupt pending flag, excluding NMI and Faults.
                                                             @ 0: Interrupt not pending
                                                             @ 1: Interrupt pending
.equ SCB_ICSR_VECTPENDING_N    , 12
.equ SCB_ICSR_VECTPENDING_M    , 0x1FF << SCB_ICSR_VECTPENDING_N   @ Bits 18:12 Pending vector. Indicates the exception number of the highest priority
                                                             @ pending enabled exception.
                                                             @ 0: No pending exceptions
                                                             @ Other values: The exception number of the highest priority pending enabled exception.
                                                             @ The value indicated by this field includes the effect of the BASEPRI and FAULTMASK
                                                             @ registers, but not any effect of the PRIMASK register.
.equ SCB_ICSR_RETTOBASE_N       , 11
.equ SCB_ICSR_RETTOBASE         , 1 << SCB_ICSR_RETTOBASE_N   @ Bit 11 Return to base level. Indicates whether there are preempted active exceptions:
                                                             @ 0: There are preempted active exceptions to execute
                                                             @ 1: There are no active exceptions, or the currently-executing exception is the only active exception.
.equ SCB_ICSR_VECTACTIVE_N     , 0
.equ SCB_ICSR_VECTACTIVE_M     , 0x1FF << SCB_ICSR_VECTACTIVE_N    @ Bit 0 Active vector. Contains the active exception number:
                                                             @ 0: Thread mode
                                                             @ Other values: The exception number of the currently active exception.
                                                             @ То же значение что и IPSR [8:0]
@.END


@.ITEM     SCB_VTOR
.equ SCB_VTOR_ResetValue  , 0                                @ Значение после сброса
.equ SCB_VTOR_TBLOFF_N    , 9
.equ SCB_VTOR_TBLOFF_M    , 0x1FFFFFF << SCB_VTOR_TBLOFF_N   @ Bits 29:9 TBLOFF[29:9]: Vector table base offset field.
.equ SCB_VTOR_TBLOFF_SRAM , 1 << 29                          @ Bit 29 determines whether the vector table is in the code or SRAM memory region. 0: Code 1: SRAM
@.END


@.ITEM     SCB_AIRCR
.equ SCB_AIRCR_ResetValue      , 0xFA050000                         @ Значение после сброса
.equ SCB_AIRCR_VECTKEY_N       , 16
.equ SCB_AIRCR_VECTKEY_M       , 0xFFFF << SCB_AIRCR_VECTKEY_N      @ Bits 31:16 VECTKEYSTAT/ VECTKEY Register key
.equ SCB_AIRCR_VECTKEY_code    , 0x05FA << SCB_AIRCR_VECTKEY_N      @ On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
.equ SCB_AIRCR_VECTKEYSTAT_N   , 16
.equ SCB_AIRCR_VECTKEYSTAT_M   , 0xFFFF << SCB_AIRCR_VECTKEYSTAT_N  @ Reads as 0xFA05
.equ SCB_AIRCR_ENDIANESS_N     , 15
.equ SCB_AIRCR_ENDIANESS       , 1 << SCB_AIRCR_ENDIANESS_N         @ Bit 15 ENDIANESS Data endianness bit. Reads as 0.
                                                                    @   0: Little-endian
.equ SCB_AIRCR_PRIGROUP_N      , 8
.equ SCB_AIRCR_PRIGROUP_M      , 7 << SCB_AIRCR_PRIGROUP_N          @ Bits 10:8 PRIGROUP: Interrupt priority grouping field
.equ SCB_AIRCR_SYSRESETREQ_N   , 2
.equ SCB_AIRCR_SYSRESETREQ     , 1 << SCB_AIRCR_SYSRESETREQ_N       @ Bit 2 SYSRESETREQ System reset request. This is intended to force a large
                                                                    @     system reset of all major components except for debug.
                                                                    @ This bit reads as 0.
                                                                    @   0: No system reset request
                                                                    @   1: Asserts a signal to the outer system that requests a reset.
.equ SCB_AIRCR_VECTCLRACTIVE_N , 1
.equ SCB_AIRCR_VECTCLRACTIVE   , 1 << SCB_AIRCR_VECTCLRACTIVE_N     @ Bit 1 Reserved for Debug use. This bit reads as 0. When writing to the register you
                                                                    @    must write 0 to this bit, otherwise behavior is unpredictable.
.equ SCB_AIRCR_VECTRESET_N     , 0
.equ SCB_AIRCR_VECTRESET       , 1 << SCB_AIRCR_VECTRESET_N         @ Bit 0 Reserved for Debug use. This bit reads as 0. When writing to the register you
                                                                    @     must write 0 to this bit, otherwise behavior is unpredictable.
@.END






@.ITEM     SCB_SCR
.equ SCB_SCR_ResetValue     , 0                           @ Значение после сброса
.equ SCB_SCR_SEVONPEND_N    , 4
.equ SCB_SCR_SEVONPEND      , 1 << SCB_SCR_SEVONPEND_N    @ Bit 4 Send Event on Pending bit
                                                          @ 0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
.equ SCB_SCR_SEVONPEND_All  , 1 << SCB_SCR_SEVONPEND_N    @ 1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
.equ SCB_SCR_SLEEPDEEP_N    , 2
.equ SCB_SCR_SLEEPDEEP      , 1 << SCB_SCR_SLEEPDEEP_N    @ Bit 2 Controls whether the processor uses sleep or deep sleep as its low power mode:
                                                          @   0: Sleep
                                                          @   1: Deep sleep.
.equ SCB_SCR_SLEEPONEXIT_N  , 1
.equ SCB_SCR_SLEEPONEXIT    , 1 << SCB_SCR_SLEEPONEXIT_N  @ Bit 1 Configures sleep-on-exit when returning from Handler mode to Thread mode.
                                                          @   0: Do not sleep when returning to Thread mode.
                                                          @   1: Enter sleep, or deep sleep, on return from an interrupt service routine.
@.END


@.ITEM     SCB_CCR
.equ SCB_CCR_ResetValue       , 0x00000200                @ Значение после сброса
.equ SCB_CCR_STKALIGN_N       , 9
.equ SCB_CCR_STKALIGN         , 1 << SCB_CCR_STKALIGN_N   @ Bit 9 Configures stack alignment on exception entry. On exception entry, the processor uses bit 9 of
                                                          @   the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
                                                          @  0: 4-byte aligned
.equ SCB_CCR_STKALIGN_8_bytes , 1 << SCB_CCR_STKALIGN_N   @  1: 8-byte aligned
.equ SCB_CCR_BFHFNMIGN_N      , 8
.equ SCB_CCR_BFHFNMIGN        , 1 << SCB_CCR_BFHFNMIGN_N  @ Bit 8 Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions.
                                                          @  0: Data bus faults caused by load and store instructions cause a lock-up
                                                          @  1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
.equ SCB_CCR_DIV_0_TRP_N      , 4
.equ SCB_CCR_DIV_0_TRP        , 1 << SCB_CCR_DIV_0_TRP_N  @ Bit 4 Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
                                                          @   0: Do not trap divide by 0
                                                          @   1: Trap divide by 0. D этом случае деление на 0 даст частное = 0
.equ SCB_CCR_UNALIGN_TRP_N    , 3
.equ SCB_CCR_UNALIGN_TRP      , 1 << SCB_CCR_UNALIGN_TRP_N  @ Bit 3 Enables unaligned access traps:
                                                          @   0: Do not trap unaligned halfword and word accesses
                                                          @   1: Trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault.
                                                          @   Невыровненные LDM, STM, LDRD, and STRD инструкции всегда дают сбой независимо от этого бита
.equ SCB_CCR_USERSETMPEND_N   , 1
.equ SCB_CCR_USERSETMPEND     , 1 << SCB_CCR_USERSETMPEND_N   @ Bit 1 Enables unprivileged software access to the NVIC_STIR
                                                              @   0: Disable
                                                              @   1: Enable.
.equ SCB_CCR_NONBASETHRDENA_N , 0
.equ SCB_CCR_NONBASETHRDENA   , 1 << SCB_CCR_NONBASETHRDENA_N @ Bit 0 Configures how the processor enters Thread mode.
                                                              @   0: Processor can enter Thread mode only when no exception is active.
                                                              @   1: Processor can enter Thread mode from any level under the control of an EXC_RETURN value.
@.END

@.ITEM     SCB_SHPR1
.EQU  SCB_SHPR1_ResetValue, 0  @ Значение после сброса
.EQU  SCB_SHPR1_PRI_4_N, 0     @ Bits 7:0 PRI_4[7:0]: Priority of system handler 4, memory management fault
.EQU  SCB_SHPR1_PRI_4_M, 0xFF << SCB_SHPR1_PRI_4_N
.EQU  SCB_SHPR1_PRI_5_N, 8     @ Bits 15:8 PRI_5[7:0]: Priority of system handler 5, bus fault
.EQU  SCB_SHPR1_PRI_5_M, 0xFF << SCB_SHPR1_PRI_5_N
.EQU  SCB_SHPR1_PRI_6_N, 16    @ Bits 23:16 PRI_6[7:0]: Priority of system handler 6, usage fault
.EQU  SCB_SHPR1_PRI_6_M, 0xFF << SCB_SHPR1_PRI_6_N
@.END

@.ITEM     SCB_SHPR2
.EQU  SCB_SHPR2_ResetValue, 0  @ Значение после сброса
.EQU  SCB_SHPR2_PRI_11_N, 24   @ Bits 31:24 PRI_11[7:0]: Priority of system handler 11, SVCall
.EQU  SCB_SHPR2_PRI_11_M, 0xFF << SCB_SHPR2_PRI_11_N
@.END

@.ITEM     SCB_SHPR3
.EQU  SCB_SHPR3_RestValue, 0   @ Значение после сброса
.EQU  SCB_SHPR3_PRI_15_N, 24   @ Bits 31:24 PRI_15[7:0]: Priority of system handler 15, SysTick exception
.EQU  SCB_SHPR3_PRI_15_M, 0xFF << SCB_SHPR3_PRI_15_N
.EQU  SCB_SHPR3_PRI_14_N, 16   @ Bits 23:16 PRI_14[7:0]: Priority of system handler 14, PendSV
.EQU  SCB_SHPR3_PRI_14_M, 0xFF << SCB_SHPR3_PRI_14_N
@.END

@.ITEM     SCB_SHCSR
.equ SCB_SHCSR_ResetValue         , 0                                @ Значение после сброса
.equ SCB_SHCSR_USGFAULTENA_N      , 18
.equ SCB_SHCSR_USGFAULTENA        , 1 << SCB_SHCSR_USGFAULTENA_N     @ Bit 18 USGFAULTENA: Usage fault enable bit, set to 1 to enable
.equ SCB_SHCSR_BUSFAULTENA_N      , 17
.equ SCB_SHCSR_BUSFAULTENA        , 1 << SCB_SHCSR_BUSFAULTENA_N     @ Bit 17 BUSFAULTENA: Bus fault enable bit, set to 1 to enable
.equ SCB_SHCSR_MEMFAULTENA_N      , 16
.equ SCB_SHCSR_MEMFAULTENA        , 1 << SCB_SHCSR_MEMFAULTENA_N     @ Bit 16 MEMFAULTENA: Memory management fault enable bit, set to 1 to enable
.equ SCB_SHCSR_SVCALLPENDED_N     , 15
.equ SCB_SHCSR_SVCALLPENDED       , 1 << SCB_SHCSR_SVCALLPENDED_N    @ Bit 15 SVCALLPENDED: SVC call pending bit, reads as 1 if exception is pending
.equ SCB_SHCSR_BUSFAULTPENDED_N   , 14
.equ SCB_SHCSR_BUSFAULTPENDED     , 1 << SCB_SHCSR_BUSFAULTPENDED_N  @ Bit 14 BUSFAULTPENDED: Bus fault exception pending bit, reads as 1 if exception is pending
.equ SCB_SHCSR_MEMFAULTPENDED_N   , 13
.equ SCB_SHCSR_MEMFAULTPENDED     , 1 << SCB_SHCSR_MEMFAULTPENDED_N  @ Bit 13 MEMFAULTPENDED: Memory management fault exception pending bit, reads as 1 if exception  is pending
.equ SCB_SHCSR_USGFAULTPENDED_N   , 12
.equ SCB_SHCSR_USGFAULTPENDED     , 1 << SCB_SHCSR_USGFAULTPENDED_N  @ Bit 12 USGFAULTPENDED: Usage fault exception pending bit, reads as 1 if exception is pending
.equ SCB_SHCSR_SYSTICKACT_N       , 11
.equ SCB_SHCSR_SYSTICKACT         , 1 << SCB_SHCSR_SYSTICKACT_N      @ Bit 11 SYSTICKACT: SysTick exception active bit, reads as 1 if exception is active
.equ SCB_SHCSR_PENDSVACT_N        , 10
.equ SCB_SHCSR_PENDSVACT          , 1 << SCB_SHCSR_PENDSVACT_N       @ Bit 10 PENDSVACT: PendSV exception active bit, reads as 1 if exception is active
.equ SCB_SHCSR_MONITORACT_N       , 8
.equ SCB_SHCSR_MONITORACT         , 1 << SCB_SHCSR_MONITORACT_N      @ Bit 8 MONITORACT: Debug monitor active bit, reads as 1 if Debug monitor is active
.equ SCB_SHCSR_SVCALLACT_N        , 7
.equ SCB_SHCSR_SVCALLACT          , 1 << SCB_SHCSR_SVCALLACT_N       @ Bit 7 SVCALLACT: SVC call active bit, reads as 1 if SVC call is active
.equ SCB_SHCSR_USGFAULTACT_N      , 3
.equ SCB_SHCSR_USGFAULTACT        , 1 << SCB_SHCSR_USGFAULTACT_N     @ Bit 3 USGFAULTACT: Usage fault exception active bit, reads as 1 if exception is active
.equ SCB_SHCSR_BUSFAULTACT_N      , 1
.equ SCB_SHCSR_BUSFAULTACT        , 1 << SCB_SHCSR_BUSFAULTACT_N     @ Bit 1 BUSFAULTACT: Bus fault exception active bit, reads as 1 if exception is active
.equ SCB_SHCSR_MEMFAULTACT_N      , 0
.equ SCB_SHCSR_MEMFAULTACT        , 1 << SCB_SHCSR_MEMFAULTACT_N     @ Bit 0 MEMFAULTACT: Memory management fault exception active bit, reads as 1 if exception is active
@.END



@.ITEM     SCB_CFSR
.equ SCB_CFSR_ResetValue    , 0                   @ Значение после сброса
.EQU SCB_CFSR_MMFSR_ADR, SCB_BASE + SCB_CFSR      @ MMFSR with a byte access
.EQU SCB_CFSR_BFSR_ADR , SCB_BASE + SCB_CFSR + 1  @ BFSR with a byte access
.EQU SCB_CFSR_UFSR_ADR , SCB_BASE + SCB_CFSR + 2  @ UFSR with a halfword access
.equ SCB_CFSR_DIVBYZERO_N   , 25
.equ SCB_CFSR_DIVBYZERO     , 1 << SCB_CFSR_DIVBYZERO_N   @ Bit 25 DIVBYZERO: Divide by zero usage fault. Enable trapping of divide by zero by setting in SCB_CCR_DIV_0_TRP
                                                          @   0: No divide by zero fault, or divide by zero trapping not enabled
                                                          @   1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
.equ SCB_CFSR_UNALIGNED_N   , 24
.equ SCB_CFSR_UNALIGNED     , 1 << SCB_CFSR_UNALIGNED_N   @ Bit 24 UNALIGNED: Unaligned access usage fault. Enable trapping of unaligned accesses by setting in SCB_CCR_UNALIGN_TRP
                                                          @   0: No unaligned access fault, or unaligned access trapping not enabled
                                                          @   1: the processor has made an unaligned memory access.
.equ SCB_CFSR_NOCP_N        , 19
.equ SCB_CFSR_NOCP          , 1 << SCB_CFSR_NOCP_N        @ Bit 19 NOCP: No coprocessor usage fault.
                                                          @   0: No usage fault caused by attempting to access a coprocessor
                                                          @   1: the processor has attempted to access a coprocessor.
.equ SCB_CFSR_INVPC_N       , 18
.equ SCB_CFSR_INVPC         , 1 << SCB_CFSR_INVPC_N       @ Bit 18 INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
                                                          @   0: No invalid PC load usage fault
                                                          @   1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value.
.equ SCB_CFSR_INVSTATE_N    , 17
.equ SCB_CFSR_INVSTATE      , 1 << SCB_CFSR_INVSTATE_N    @ Bit 17 INVSTATE: Invalid state usage fault.
                                                          @   0: No invalid state usage fault
                                                          @   1: The processor has attempted to execute an instruction that makes illegal use of the EPSR.
.equ SCB_CFSR_UNDEFINSTR_N  , 16
.equ SCB_CFSR_UNDEFINSTR    , 1 << SCB_CFSR_UNDEFINSTR_N  @ Bit 16 UNDEFINSTR: Undefined instruction usage fault.
                                                          @   0: No undefined instruction usage fault
                                                          @   1: The processor has attempted to execute an undefined instruction.
.equ SCB_CFSR_BFARVALID_N   , 15
.equ SCB_CFSR_BFARVALID     , 1 << SCB_CFSR_BFARVALID_N   @ Bit 15 BFARVALID: Bus Fault Address Register (BFAR) valid flag.
                                                          @   0: Value in BFAR is not a valid fault address
                                                          @   1: BFAR holds a valid fault address.
.equ SCB_CFSR_LSPERR_N      , 13
.equ SCB_CFSR_LSPERR        , 1 << SCB_CFSR_LSPERR_N      @ Bit 13 LSPERR: Bus fault on floating-point lazy state preservation.
                                                          @   0: No bus fault occurred during floating-point lazy state preservation.
                                                          @   1: A bus fault occurred during floating-point lazy state preservation
.equ SCB_CFSR_STKERR_N      , 12
.equ SCB_CFSR_STKERR        , 1 << SCB_CFSR_STKERR_N      @ Bit 12 STKERR: Bus fault on stacking for exception entry.
                                                          @   0: No stacking fault
                                                          @   1: Stacking for an exception entry has caused one or more bus faults.
.equ SCB_CFSR_UNSTKERR_N    , 11
.equ SCB_CFSR_UNSTKERR      , 1 << SCB_CFSR_UNSTKERR_N    @ Bit 11 UNSTKERR: Bus fault on unstacking for a return from exception.
                                                          @   0: No unstacking fault
                                                          @   1: Unstack for an exception return has caused one or more bus faults.
.equ SCB_CFSR_IMPRECISERR_N , 10
.equ SCB_CFSR_IMPRECISERR   , 1 << SCB_CFSR_IMPRECISERR_N @ Bit 10 IMPRECISERR: Imprecise data bus error.
                                                          @   0: No imprecise data bus error
                                                          @   1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.
.equ SCB_CFSR_PRECISERR_N   , 9
.equ SCB_CFSR_PRECISERR     , 1 << SCB_CFSR_PRECISERR_N   @ Bit 9 PRECISERR: Precise data bus error.
                                                          @   0: No precise data bus error
                                                          @   1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.
.equ SCB_CFSR_IBUSERR_N     , 8
.equ SCB_CFSR_IBUSERR       , 1 << SCB_CFSR_IBUSERR_N     @ Bit 8 IBUSERR: Instruction bus error.
                                                          @   0: No instruction bus error
                                                          @   1: Instruction bus error.
.equ SCB_CFSR_MMARVALID_N   , 7
.equ SCB_CFSR_MMARVALID     , 1 << SCB_CFSR_MMARVALID_N   @ Bit 7 MMARVALID: Memory Management Fault Address Register (MMAR) valid flag.
                                                          @   0: Value in MMAR is not a valid fault address
                                                          @   1: MMAR holds a valid fault address.
.equ SCB_CFSR_MLSPERR_N     , 5
.equ SCB_CFSR_MLSPERR       , 1 << SCB_CFSR_MLSPERR_N     @ Bit 5 MLSPERR:
                                                          @   0: No MemManage fault occurred during floating-point lazy state preservation
                                                          @   1: A MemManage fault occurred during floating-point lazy state preservation
.equ SCB_CFSR_MSTKERR_N     , 4
.equ SCB_CFSR_MSTKERR       , 1 << SCB_CFSR_MSTKERR_N     @ Bit 4 MSTKERR: Memory manager fault on stacking for exception entry.
                                                          @   0: No stacking fault
                                                          @   1: Stacking for an exception entry has caused one or more access violations.
.equ SCB_CFSR_MUNSTKERR_N   , 3
.equ SCB_CFSR_MUNSTKERR     , 1 << SCB_CFSR_MUNSTKERR_N   @ Bit 3 MUNSTKERR: Memory manager fault on unstacking for a return from exception.
                                                          @   0: No unstacking fault
                                                          @   1: Unstack for an exception return has caused one or more access violations.
.equ SCB_CFSR_DACCVIOL_N    , 1
.equ SCB_CFSR_DACCVIOL      , 1 << SCB_CFSR_DACCVIOL_N    @ Bit 1 DACCVIOL: Data access violation flag.
                                                          @   0: No data access violation fault
                                                          @   1: The processor attempted a load or store at a location that does not permit the operation.
.equ SCB_CFSR_IACCVIOL_N    , 0
.equ SCB_CFSR_IACCVIOL      , 1 << SCB_CFSR_IACCVIOL_N    @ Bit 0 IACCVIOL: Instruction access violation flag.
                                                          @   0: No instruction access violation fault
                                                          @   1: The processor attempted an instruction fetch from a location that does not permit execution.
@.END

@.ITEM     SCB_HFSR
.equ SCB_HFSR_ResetValue  , 0                         @ Значение после сброса
.equ SCB_HFSR_DEBUGEVT_N  , 31
.equ SCB_HFSR_DEBUGEVT    , 1 << SCB_HFSR_DEBUGEVT_N  @ Bit 31 DEBUG_VT: Reserved   for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is unpredictable
.equ SCB_HFSR_FORCED_N    , 30
.equ SCB_HFSR_FORCED      , 1 << SCB_HFSR_FORCED_N    @ Bit 30 FORCED: Forced hard fault
                                                      @   0: No forced hard fault
                                                      @   1: Forced hard fault.
.equ SCB_HFSR_VECTTBL_N   , 1
.equ SCB_HFSR_VECTTBL     , 1 << SCB_HFSR_VECTTBL_N   @ Bit 1 VECTTBL: Vector table hard fault
                                                      @   0: No bus fault on vector table read
                                                      @   1: Bus fault on vector table read.
@.END


@.ITEM     SCB_DFSR
.equ SCB_DFSR_EXTERNAL_N  , 4
.equ SCB_DFSR_EXTERNAL    , 1 << SCB_DFSR_EXTERNAL_N  @ EDBGRQ signal asserted
.equ SCB_DFSR_VCATCH_N    , 3
.equ SCB_DFSR_VCATCH      , 1 << SCB_DFSR_VCATCH_N    @ Vector fetch occurred
.equ SCB_DFSR_DWTTRAP_N   , 2
.equ SCB_DFSR_DWTTRAP     , 1 << SCB_DFSR_DWTTRAP_N   @ DWT match occurred
.equ SCB_DFSR_BKPT_N      , 1
.equ SCB_DFSR_BKPT        , 1 << SCB_DFSR_BKPT_N      @ BKPT instruction executed
.equ SCB_DFSR_HALTED_N    , 0
.equ SCB_DFSR_HALTED      , 1 << SCB_DFSR_HALTED_N    @ Halt requested in NVIC
@.END


@.ITEM     SCB_CPACR
.equ SCB_CPACR_CP11_N           , 22
.equ SCB_CPACR_CP11_M           , 3 << SCB_CPACR_CP11_N  @ Access privileges for coprocessor 11
.equ SCB_CPACR_CP10_N           , 20
.equ SCB_CPACR_CP10_M           , 3 << SCB_CPACR_CP10_N  @ Access privileges for coprocessor 10
.equ SCB_CPACR_CP11_Privileged  , 1 << SCB_CPACR_CP11_N
.equ SCB_CPACR_CP11_Full        , 3 << SCB_CPACR_CP11_N
.equ SCB_CPACR_CP10_Privileged  , 1 << SCB_CPACR_CP10_N
.equ SCB_CPACR_CP10_Full        , 3 << SCB_CPACR_CP10_N
@.END




