@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                       Константы DMA2D    STM32F4xx                        |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"


@.ITEM     AHB1PERIPH_BASE
.EQU  DMA2D_BASE     , AHB1PERIPH_BASE + 0xB000
.EQU  DMA2D          , PERIPH_BASE + DMA2D_BASE
@.END

@.ITEM     DMA2D_BASE DMA2D
.EQU  DMA2D_CR           , 0x00    @ control register
.EQU  DMA2D_ISR          , 0x04    @ Interrupt Status Register
.EQU  DMA2D_IFCR         , 0x08    @ interrupt flag clear register
.EQU  DMA2D_FGMAR        , 0x0C    @ foreground memory address register
.EQU  DMA2D_FGOR         , 0x10    @ foreground offset register
.EQU  DMA2D_BGMAR        , 0x14    @ background memory address register
.EQU  DMA2D_BGOR         , 0x18    @ background offset register
.EQU  DMA2D_FGPFCCR      , 0x1C    @ foreground PFC control register
.EQU  DMA2D_FGCOLR       , 0x20    @ foreground color register
.EQU  DMA2D_FGPFCCR      , 0x24    @ background PFC control register
.EQU  DMA2D_BGCOLR       , 0x28    @ background color register
.EQU  DMA2D_FGCMAR       , 0x2C    @ foreground CLUT memory address register
.EQU  DMA2D_BGCMAR       , 0x30    @ background CLUT memory address register
.EQU  DMA2D_OPFCCR       , 0x34    @ output PFC control register
.EQU  DMA2D_OCOLR        , 0x38    @ output color register
.EQU  DMA2D_OMAR         , 0x3C    @ output memory address register
.EQU  DMA2D_OOR          , 0x40    @ output offset register
.EQU  DMA2D_NLR          , 0x44    @ number of line register
.EQU  DMA2D_LWR          , 0x48    @ line watermark register
.EQU  DMA2D_AMTCR        , 0x4C    @ AHB master timer configuration register
.EQU  DMA2D_FGCLUT       , 0x0400    @  0x0400-0x07FF  APLHA[7:0][255:0] RED[7:0][255:0] GREEN[7:0][255:0] BLUE[7:0][255:0]
.EQU  DMA2D_BGCLUT       , 0x0800    @  0x0800-0x0BFF  APLHA[7:0][255:0] RED[7:0][255:0] GREEN[7:0][255:0] BLUE[7:0][255:0]
@.END

@.ITEM     DMA2D_CR
.EQU  DMA2D_CR_RST_VAL   , 0x00000000 @ Reset value: 0x0000 0000
.EQU  DMA2D_CR_MODE_N    , 16         @ Bits 17:16 MODE: DMA2D mode
.EQU  DMA2D_CR_MODE_M    , 3 << 16    @ 11: Register-to-memory (no FG nor BG, only output stage active)                                     @ 11: Register-to-memory (no FG nor BG, only output stage active)
.EQU  DMA2D_CR_MODE_0    , 1 << 16    @ 01: Memory-to-memory with PFC (FG fetch only with FG PFC active)
.EQU  DMA2D_CR_MODE_1    , 2 << 16    @ 10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
.EQU  DMA2D_CR_MODE_00   , 0x00       @ 00: Memory-to-memory (FG fetch only)
.EQU  DMA2D_CR_CEIE_N    , 13         @ Bit 13 CEIE: Configuration Error Interrupt Enable
.EQU  DMA2D_CR_CEIE_1    , 1 << 13    @ 1: CE interrupt enable
.EQU  DMA2D_CR_CTCIE_N   , 12         @ Bit 12 CTCIE: CLUT transfer complete interrupt enable
.EQU  DMA2D_CR_CTCIE_1   , 1 << 12    @ 1: CTC interrupt enable
.EQU  DMA2D_CR_CAEIE_N   , 11         @ Bit 11 CAEIE: CLUT access error interrupt enable
.EQU  DMA2D_CR_CAEIE_1   , 1 << 11    @ 1: CAE interrupt enable
.EQU  DMA2D_CR_TWIE_N    , 10         @ Bit 10 TWIE: Transfer watermark interrupt enable
.EQU  DMA2D_CR_TWIE_1    , 1 << 10    @ 1: TW interrupt enable
.EQU  DMA2D_CR_TCIE_N    , 9          @ Bit 9 TCIE: Transfer complete interrupt enable
.EQU  DMA2D_CR_TCIE_1    , 1 << 9     @ 1: TC interrupt enable
.EQU  DMA2D_CR_TEIE_N    , 8          @ Bit 8 TEIE: Transfer error interrupt enable
.EQU  DMA2D_CR_TEIE_1    , 1 << 8     @ 1: TE interrupt enable
.EQU  DMA2D_CR_ABORT_N   , 2          @ Bit 2 ABORT: Abort
.EQU  DMA2D_CR_ABORT_1   , 1 << 2     @ 1: Transfer abort requested
.EQU  DMA2D_CR_SUSP_N    , 1          @ Bit 1 SUSP: Suspend
.EQU  DMA2D_CR_SUSP_1    , 1 << 1     @ 1: Transfer suspended
.EQU  DMA2D_CR_START_N   , 0          @ Bit 0 START: Start
.EQU  DMA2D_CR_START_1   , 1          @
@.END

@.ITEM     DMA2D_ISR
.EQU  DMA2D_ISR_CEIF_N   , 5          @ Bit 5 CEIF: Configuration error interrupt flag
.EQU  DMA2D_ISR_CTCIF_N  , 4          @ Bit 4 CTCIF: CLUT transfer complete interrupt flag
.EQU  DMA2D_ISR_CAEIF_N  , 3          @ Bit 3 CAEIF: CLUT access error interrupt flag
.EQU  DMA2D_ISR_TWIF_N   , 2          @ Bit 2 TWIF: Transfer watermark interrupt flag
.EQU  DMA2D_ISR_TCIF_N   , 1          @ Bit 1 TCIF: Transfer complete interrupt flag
.EQU  DMA2D_ISR_TEIF_N   , 0          @ Bit 0 TEIF: Transfer error interrupt flag
@.END

@.ITEM     DMA2D_IFCR
.EQU  DMA2D_IFCR_RST_VAL , 0          @ Reset value: 0x0000 0000
.EQU  DMA2D_IFCR_CCEIF_N , 5          @ Bit 5 CCEIF: Clear configuration error interrupt flag
.EQU  DMA2D_IFCR_CCEIF   , 1 << 5     @ Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
.EQU  DMA2D_IFCR_CCTCIF_N, 4          @ Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
.EQU  DMA2D_IFCR_CCTCIF  , 1 << 4     @ Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
.EQU  DMA2D_IFCR_CAECIF_N, 3          @ Bit 3 CAECIF: Clear CLUT access error interrupt flag
.EQU  DMA2D_IFCR_CAECIF  , 1 << 3     @ Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
.EQU  DMA2D_IFCR_CTWIF_N , 2          @ Bit 2 CTWIF: Clear transfer watermark interrupt flag
.EQU  DMA2D_IFCR_CTWIF   , 1 << 2     @ Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
.EQU  DMA2D_IFCR_CTCIF_N , 1          @ Bit 1 CTCIF: Clear transfer complete interrupt flag
.EQU  DMA2D_IFCR_CTCIF   , 1 << 1     @ Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
.EQU  DMA2D_IFCR_CTEIF_N , 0          @ Bit 0 CTEIF: Clear Transfer error interrupt flag
.EQU  DMA2D_IFCR_CTEIF   , 0          @ Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
@.END

@.ITEM     DMA2D_FGPFCCR
.EQU  DMA2D_FGPFCCR_RST_VAL, 0x00000000    @ Reset value: 0x0000 0000
.EQU  DMA2D_FGPFCCR_ALPHA_N, 24           @ Bits 31:24 ALPHA[7: 0]: Alpha value
.EQU  DMA2D_FGPFCCR_ALPHA_M, 0xFF000000    @
.EQU  DMA2D_FGPFCCR_AM_N , 16             @ Bits 17:16 AM[1: 0]: Alpha mode
.EQU  DMA2D_FGPFCCR_AM_0 , 1 << 16        @ Replace original foreground image alpha channel value by ALPHA[7: 0]
.EQU  DMA2D_FGPFCCR_AM_1 , 2 << 16        @ 10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied
.EQU  DMA2D_FGPFCCR_CS_N    , 8               @ Bits 15:8 CS[7: 0]: CLUT size
.EQU  DMA2D_FGPFCCR_CS_M    , 0x0000FF00      @
.EQU  DMA2D_FGPFCCR_START_N , 5               @ Bit 5 START: Start
.EQU  DMA2D_FGPFCCR_START   , 1 << 5          @
.EQU  DMA2D_FGPFCCR_CCM_N   , 4               @ Bit 4 CCM: CLUT color mode
.EQU  DMA2D_FGPFCCR_CCM_0, 0 << 4         @ 0: ARGB8888
.EQU  DMA2D_FGPFCCR_CCM_1, 1 << 4         @ 1: RGB888
.EQU  DMA2D_FGPFCCR_CM_N , 0              @ Bits 3:0 CM[3: 0]: Color mode
.EQU  DMA2D_FGPFCCR_CM_0 , 0              @ 0000: ARGB8888
.EQU  DMA2D_FGPFCCR_CM_1 , 1              @ 0001: RGB888
.EQU  DMA2D_FGPFCCR_CM_2 , 2              @ 0010: RGB565
.EQU  DMA2D_FGPFCCR_CM_3 , 3              @ 0011: ARGB1555
.EQU  DMA2D_FGPFCCR_CM_4 , 4              @ 0100: ARGB4444
.EQU  DMA2D_FGPFCCR_CM_5 , 5              @ 0101: L8
.EQU  DMA2D_FGPFCCR_CM_6 , 6              @ 0110: AL44
.EQU  DMA2D_FGPFCCR_CM_7 , 7              @ 0111: AL88
.EQU  DMA2D_FGPFCCR_CM_8 , 8              @ 1000: L4
.EQU  DMA2D_FGPFCCR_CM_9 , 9              @ 1001: A8
.EQU  DMA2D_FGPFCCR_CM_10, 10             @ 1010: A4
@.END

@.ITEM     DMA2D_FGCOLR
.EQU  DMA2D_FGCOLR_RST_VAL  , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_FGCOLR_RED_N    , 16              @ Bits 23:16 RED[7: 0]: Red Value
.EQU  DMA2D_FGCOLR_RED_M    , 0x00FF0000      @
.EQU  DMA2D_FGCOLR_GREEN_N  , 8            @ Bits 15:8 GREEN[7: 0]: Green Value
.EQU  DMA2D_FGCOLR_GREEN_M  , 0x0000FF00      @
.EQU  DMA2D_FGCOLR_BLUE_N   , 0            @ Bits 7:0 BLUE[7: 0]: Blue Value
.EQU  DMA2D_FGCOLR_BLUE_M   , 0x000000FF      @
@.END

@.ITEM     DMA2D_BGPFCCR
.EQU  DMA2D_BGPFCCR_RST_VAL , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_BGPFCCR_ALPHA_N , 24              @ Bits 31:24 ALPHA[7: 0]: Alpha value
.EQU  DMA2D_BGPFCCR_ALPHA_M , 0xFF000000      @ These bits define a fixed alpha channel value which can replace the original alpha value
.EQU  DMA2D_BGPFCCR_AM_N    , 16              @ Bits 17:16 AM[1: 0]: Alpha mode
.EQU  DMA2D_BGPFCCR_AM_0    , 1 << 16         @ 01: Replace original background image alpha channel value by ALPHA[7: 0]
.EQU  DMA2D_BGPFCCR_AM_1    , 2 << 16         @ 10: Replace original background image alpha channel value by ALPHA[7:0] multiplied
.EQU  DMA2D_BGPFCCR_CS_N    , 8               @ Bits 15:8 CS[7: 0]: CLUT size
.EQU  DMA2D_BGPFCCR_CS_M    , 0x0000FF00      @
.EQU  DMA2D_BGPFCCR_START_N , 5               @ Bit 5 START: Start
.EQU  DMA2D_BGPFCCR_START   , 1 << 5          @
.EQU  DMA2D_BGPFCCR_CCM_N   , 4               @ Bit 4 CCM: CLUT color mode
.EQU  DMA2D_BGPFCCR_CCM_0   , 0 << 4          @ 0: ARGB8888
.EQU  DMA2D_BGPFCCR_CCM_1   , 1 << 4          @ 1: RGB888
.EQU  DMA2D_BGPFCCR_CM_N    , 0               @ Bits 3:0 CM[3: 0]: Color mode
.EQU  DMA2D_BGPFCCR_CM_0    , 0               @ 0000: ARGB8888
.EQU  DMA2D_BGPFCCR_CM_1    , 1               @ 0001: RGB888
.EQU  DMA2D_BGPFCCR_CM_2    , 2               @ 0010: RGB565
.EQU  DMA2D_BGPFCCR_CM_3    , 3               @ 0011: ARGB1555
.EQU  DMA2D_BGPFCCR_CM_4    , 4               @ 0100: ARGB4444
.EQU  DMA2D_BGPFCCR_CM_5    , 5               @ 0101: L8
.EQU  DMA2D_BGPFCCR_CM_6    , 6               @ 0110: AL44
.EQU  DMA2D_BGPFCCR_CM_7    , 7               @ 0111: AL88
.EQU  DMA2D_BGPFCCR_CM_8    , 8               @ 1000: L4
.EQU  DMA2D_BGPFCCR_CM_9    , 9               @ 1001: A8
.EQU  DMA2D_BGPFCCR_CM_10   , 10              @ 1010: A4
@.END

@.ITEM     DMA2D_BGCOLR
.EQU  DMA2D_BGCOLR_RST_VAL  , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_BGCOLR_RED_N    , 16              @ Bits 23:16 RED[7: 0]: Red Value
.EQU  DMA2D_BGCOLR_RED_M    , 0x00FF0000      @
.EQU  DMA2D_BGCOLR_GREEN_N  , 8            @ Bits 15:8 GREEN[7: 0]: Green Value
.EQU  DMA2D_BGCOLR_GREEN_M  , 0x0000FF00      @
.EQU  DMA2D_BGCOLR_BLUE_N   , 0            @ Bits 7:0 BLUE[7: 0]: Blue Value
.EQU  DMA2D_BGCOLR_BLUE_M   , 0x000000FF      @
@.END

@.ITEM     DMA2D_FGCMAR
.EQU  DMA2D_FGCMAR_MA_N     , 0               @ Bits 31: 0 MA[31: 0]: Memory Address
.EQU  DMA2D_FGCMAR_MA_M     , 0xFFFFFFFF      @
@.END

@.ITEM     DMA2D_BGCMAR
.EQU  DMA2D_BGCMAR_MA_N     , 0               @ Bits 31: 0 MA[31: 0]: Memory Address
.EQU  DMA2D_BGCMAR_MA_M     , 0xFFFFFFFF      @
@.END

@.ITEM     DMA2D_OPFCCR
.EQU  DMA2D_OPFCCR_RST_VAL  , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_OPFCCR_CM_N, 0     @ Bits 2: 0 CM[2: 0]: Color mode
.EQU  DMA2D_OPFCCR_CM_0, 1     @ 001: RGB888   000: ARGB8888
.EQU  DMA2D_OPFCCR_CM_1, 2     @ 010: RGB565   011: ARGB1555
.EQU  DMA2D_OPFCCR_CM_2, 4     @ 100: ARGB4444
@.END


@.ITEM     DMA2D_OCOLR
.EQU  DMA2D_OCOLR_RST_VAL   , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_OCOLR_ALPHA_N   , 24              @ Bits 31:24 ALPHA[7: 0]: Alpha Channel Value
.EQU  DMA2D_OCOLR_ALPHA_M   , 0xFF000000      @
.EQU  DMA2D_OCOLR_RED_N     , 16              @ Bits 23:16 RED[7: 0]: Red Value
.EQU  DMA2D_OCOLR_RED_M     , 0x00FF0000      @
.EQU  DMA2D_OCOLR_GREEN_N   , 8               @ Bits 15:8 GREEN[7: 0]: Green Value
.EQU  DMA2D_OCOLR_GREEN_M   , 0x0000FF00      @
.EQU  DMA2D_OCOLR_BLUE_N    , 0               @ Bits 7:0 BLUE[7: 0]: Blue Value
.EQU  DMA2D_OCOLR_BLUE_M    , 0x000000FF      @
@.END

@.ITEM     DMA2D_OOR
.EQU  DMA2D_OOR_RST_VAL     , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_OOR_LO_N        , 0               @ Bits 13:0 LO[13: 0]: Line Offset
.EQU  DMA2D_OOR_LO_M        , 0x00003FFF      @
@.END

@.ITEM     DMA2D_NLR
.EQU  DMA2D_NLR_RST_VAL     , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_NLR_PL_N        , 16              @ Bits 29:16 PL[13: 0]: Pixel per lines
.EQU  DMA2D_NLR_PLM         , 0x7FFF0000      @
.EQU  DMA2D_NLR_NL_N        , 0               @ Bits 15:0 NL[15: 0]: Number of lines
.EQU  DMA2D_NLR_NL_M        , 0x0000FFFF      @
@.END

@.ITEM     DMA2D_LWR
.EQU  DMA2D_LWR_RST_VAL     , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_LWR_LO_N        , 0               @ Bits 15:0 LW[15:0]: Line watermark
.EQU  DMA2D_LWR_LO_M        , 0x0000FFFF      @
@.END

@.ITEM     DMA2D_LWR
.EQU  DMA2D_LWR_RST_VAL     , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_LWR_LO_N        , 0               @ Bits 15:0 LW[15:0]: Line watermark
.EQU  DMA2D_LWR_LO_M        , 0x0000FFFF      @
@.END

@.ITEM     DMA2D_AMTCR
.EQU  DMA2D_AMTCR_RST_VAL   , 0x00000000      @ Reset value: 0x0000 0000
.EQU  DMA2D_AMTCR_DT_N      , 8               @ Bits 15:8 DT[7: 0]: Dead Time
.EQU  DMA2D_AMTCR_DT_M      , 0x0000FF00      @
.EQU  DMA2D_AMTCR_EN_N      , 0               @ Bit 0 EN: Enable
.EQU  DMA2D_AMTCR_EN        , 1               @
@.END

