@.CHARSET =CP1251 ( Cyrillic )
@GNU AS

@.ITEM     ADC1 ADC1_BASE ADC2 ADC2_BASE ADC3 ADC3_BASE
.EQU  ADC_SR         , 0x00                        @ ADC status register (ADC_SR)
.EQU  ADC_CR1        , 0x04                        @ ADC control register 1 (ADC_CR1)
.EQU  ADC_CR2        , 0x08                        @ ADC control register 2 (ADC_CR2)
.EQU  ADC_SMPR1      , 0X0C                        @ ADC sample time register 1 (ADC_SMPR1)
.EQU  ADC_SMPR2      , 0X10                        @ ADC sample time register 2 (ADC_SMPR2)
.EQU  ADC_JOFR1      , 0X14                        @ ADC injected channel 1 data offset register  (ADC_JOFRx)
.EQU  ADC_JOFR2      , 0X18                        @ ADC injected channel 2 data offset register  (ADC_JOFRx)
.EQU  ADC_JOFR3      , 0X1C                        @ ADC injected channel 3 data offset register  (ADC_JOFRx)
.EQU  ADC_JOFR4      , 0X20                        @ ADC injected channel 4 data offset register  (ADC_JOFRx)
.EQU  ADC_HTR        , 0X24                        @ ADC watchdog high threshold register (ADC_HTR)
.EQU  ADC_LTR        , 0X28                        @ ADC watchdog low threshold register (ADC_LTR)
.EQU  ADC_SQR1       , 0X2C                        @ ADC regular sequence register 1 (ADC_SQR1)
.EQU  ADC_SQR2       , 0X30                        @ ADC regular sequence register 2 (ADC_SQR2)
.EQU  ADC_SQR3       , 0X34                        @ ADC r egular sequence register 3 (ADC_SQR3)
.EQU  ADC_JSQR       , 0X38                        @ ADC injected sequence register (ADC_JSQR)
.EQU  ADC_JDR1       , 0X3C                        @ ADC injected data register 1 (ADC_JDRx)
.EQU  ADC_JDR2       , 0X40                        @ ADC injected data register 2 (ADC_JDRx)
.EQU  ADC_JDR3       , 0X44                        @ ADC injected data register 3 (ADC_JDRx)
.EQU  ADC_JDR4       , 0X48                        @ ADC injected data register 4 (ADC_JDRx)
.EQU  ADC_DR         , 0X4C                        @ ADC regular data register (ADC_DR)
@.END

@.ITEM     ADC_SR
.EQU  ADC_SR_STRT    , 1 << 4                      @ Bit 4 STRT: Regular channel Start flag
.EQU  ADC_SR_JSTRT   , 1 << 3                      @ Bit 3 JSTRT: Injected channel Start flag
.EQU  ADC_SR_JEOC    , 1 << 2                      @ Bit 2 JEOC: Injected channel end of conversion
.EQU  ADC_SR_EOC     , 1 << 1                      @ Bit 1 EOC: End of conversion
.EQU  ADC_SR_AWD     , 1                           @ Bit 0 AWD: Analog watchdog flag
 @.END

@.ITEM     ADC_CR1
.EQU  ADC_CR1_AWDEN  , 1 << 23      @ Bit 23 AWDEN: Analog watchdog enable on regular channels
.EQU  ADC_CR1_JAWDEN , 1 << 22      @ Bit 22 JAWDEN: Analog watchdog enable on injected channels
.EQU  ADC_CR1_DUALMOD_N, 16         @ Bits 19:16 DUALMOD[3:0]: Dual mode selection
@ Note: These bits are reserved in ADC2 and ADC3.
@ In dual mode, a change of channel configuration generates a restart that can produce a
@ loss of synchronization. It is recommended to disable dual mode before any
@ configuration change.
.EQU  ADC_CR1_DUALMOD_0, 0<<16      @ 0000: Independent mode.
.EQU  ADC_CR1_DUALMOD_1, 1<<16      @ 0001: Combined regular simultaneous + injected simultaneous mode
.EQU  ADC_CR1_DUALMOD_2, 2<<16      @ 0010: Combined regular simultaneous + alternate trigger mode
.EQU  ADC_CR1_DUALMOD_3, 3<<16      @ 0011: Combined injected simultaneous + fast interleaved mode
.EQU  ADC_CR1_DUALMOD_4, 4<<16      @ 0100: Combined injected simultaneous + slow Interleaved mode
.EQU  ADC_CR1_DUALMOD_5, 5<<16      @ 0101: Injected simultaneous mode only
.EQU  ADC_CR1_DUALMOD_6, 6<<16      @ 0110: Regular simultaneous mode only
.EQU  ADC_CR1_DUALMOD_7, 7<<16      @ 0111: Fast interleaved mode only
.EQU  ADC_CR1_DUALMOD_8, 8<<16      @ 1000: Slow interleaved mode only
.EQU  ADC_CR1_DUALMOD_9, 9<<16      @ 1001: Alternate trigger mode only
@
.EQU  ADC_CR1_DISCNUM_N, 13                        @ Bits 15:13  DISCNUM[2:0]: Discontinuous mode channel count
.EQU  ADC_CR1_DISCNUM_M, 0b111 << 13               @ Bits 15:13  DISCNUM[2:0]: Mask
.EQU  ADC_CR1_JDISCEN, 1 << 12                     @ Bit 12 JDISCEN: Discontinuous mode on injected channels
.EQU  ADC_CR1_DISCEN , 1 << 11                     @ Bit 11 DISCEN: Discontinuous mode on regular channels
.EQU  ADC_CR1_JAUTO  , 1 << 10                     @ Bit 10 JAUTO: Automatic Injected Group conversion
.EQU  ADC_CR1_AWDSGL , 1 << 9                      @ Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
.EQU  ADC_CR1_SCAN   , 1 << 8                      @ Bit 8 SCAN: Scan mode
.EQU  ADC_CR1_JEOCIE , 1 << 7                      @ Bit 7 JEOCIE: Interrupt enable for injected channels
.EQU  ADC_CR1_AWDIE  , 1 << 6                      @ Bit 6 AWDIE: Analog watchdog interrupt enable
.EQU  ADC_CR1_EOCIE  , 1 << 5                      @ Bit 5 EOCIE: Interrupt enable for EOC
.EQU  ADC_CR1_AWDCH_N, 0                           @ Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
.EQU  ADC_CR1_AWDCH_M, 0b11111                     @ AWDCH[4:0]: Mask
.EQU  ADC_CR1_AWDCH_MIN, 0                         @ Min ADC Analog Channel
.EQU  ADC_CR1_AWDCH_MAX, 17                        @ Max ADC Analog Channel
@ Other values: reserved.
@ Note: ADC1 analog Channel16 and Channel17 are internally connected to the temperature
@ sensor and to VREFINT, respectively.
@ ADC2 analog inputs Channel16 and Channel17 are internally connected to VSS.
@ ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are
@ connected to VSS.
@.end

@.ITEM     ADC_CR2
.EQU  ADC_CR2_TSVREFE, 1 << 23                     @ Bit 23 TSVREFE: Temperature sensor and VREFINT enable
.EQU  ADC_CR2_SWSTART, 1 << 22                     @ Bit 22 SWSTART: Start conversion of regular channels
.EQU  ADC_CR2_JSWSTART, 1 << 21                    @ Bit 21 JSWSTART: Start conversion of injected channels
.EQU  ADC_CR2_EXTTRIG, 1 << 20                     @ Bit 20 EXTTRIG: External trigger conversion mode for regular channels
.EQU  ADC_CR2_EXTSEL_N, 17                         @ Bits 19:17 EXTSEL[2:0]: External event select for regular group
.EQU  ADC_CR2_EXTSEL_T1CC1, 0 << 17                @ 000: Timer 1 CC1 event
.EQU  ADC_CR2_EXTSEL_T1CC2, 1 << 17                @ 001: Timer 1 CC2 event
.EQU  ADC_CR2_EXTSEL_T1CC3, 2 << 17                @ 010: Timer 1 CC3 event
.EQU  ADC_CR2_EXTSEL_T2CC2, 3 << 17                @ 011: Timer 2 CC2 event
.EQU  ADC_CR2_EXTSEL_T3TRGO, 4 << 17               @ 100: Timer 3 TRGO event
.EQU  ADC_CR2_EXTSEL_T4CC4, 5 << 17                @ 101: Timer 4 CC4 event
.EQU  ADC_CR2_EXTSEL_EXTI11, 6 << 17               @ 110: EXTI line 11
.EQU  ADC_CR2_EXTSEL_SWSTART, 7 << 17              @ 111: SWSTART
.EQU  ADC_CR2_JEXTTRIG, 1 << 15                    @ Bit 15 JEXTTRIG: External trigger conversion mode for injected channels
.EQU  ADC_CR2_JEXTSEL_N, 12                        @ Bits 14:12 JEXTSEL[2:0]: External event select for injected group
.EQU  ADC_CR2_JEXTSEL_T1TRGO, 0 << 12              @ 000: Timer 1 TRGO event
.EQU  ADC_CR2_JEXTSEL_T1CC4, 1 << 12               @ 001: Timer 1 CC4 event
.EQU  ADC_CR2_JEXTSEL_T2TRGO, 2 << 12              @ 010: Timer 2 TRGO event
.EQU  ADC_CR2_JEXTSEL_T2CC1, 3 << 12               @ 011: Timer 2 CC1 event
.EQU  ADC_CR2_JEXTSEL_T3CC4, 4 << 12               @ 100: Timer 3 CC4 event
.EQU  ADC_CR2_JEXTSEL_T4TRGO, 5 << 12              @ 101: Timer 4 TRGO event
.EQU  ADC_CR2_JEXTSEL_EXTI15, 6 << 12              @ 110: EXTI line15
.EQU  ADC_CR2_JEXTSEL_JSWSTART, 7 << 12            @ 111: JSWSTART
.EQU  ADC_CR2_ALIGN  , 1 << 11                     @ Bit 11 ALIGN: Data alignment
.EQU  ADC_CR2_DMA    , 1 << 8                      @ Bit 8  DMA: Direct memory access mode
.EQU  ADC_CR2_RSTCAL , 1 << 3                      @ Bit 3 RSTCAL: Reset calibration
.EQU  ADC_CR2_CAL    , 1 << 2                      @ Bit 2 CAL: A/D Calibration
.EQU  ADC_CR2_COUNT  , 1 << 1                      @ Bit 1 CONT: Continuous conversion
.EQU  ADC_CR2_ADON   , 1                           @ Bit 0 ADON: A/D converter ON / OFF
@.END

@.ITEM     ADC_SMPR1 ADC_SMPR2
.EQU  ADC_SMP_1D5    , 0                           @ 000: 1.5 cycles
.EQU  ADC_SMP_7D5    , 1                           @ 001: 7.5 cycles
.EQU  ADC_SMP_13D5   , 2                           @ 010: 13.5 cycles
.EQU  ADC_SMP_28D5   , 3                           @ 011: 28.5 cycles
.EQU  ADC_SMP_41D5   , 4                           @ 100: 41.5 cycles
.EQU  ADC_SMP_55D5   , 5                           @ 101: 55.5 cycles
.EQU  ADC_SMP_71D5   , 6                           @ 110: 71.5 cycles
.EQU  ADC_SMP_239D5  , 7                           @ 111: 239.5 cycles
@.END

@.ITEM     ADC_SMPR1
.EQU  ADC_SMPR1_SMP17_N, 21                        @ Bits 23:21 SMPx[2:0]: Channel 17 Sample time selection
.EQU  ADC_SMPR1_SMP16_N, 18                        @ Bits 20:18 SMPx[2:0]: Channel 16 Sample time selection
.EQU  ADC_SMPR1_SMP15_N, 15                        @ Bits 17:15 SMPx[2:0]: Channel 15 Sample time selection
.EQU  ADC_SMPR1_SMP14_N, 12                        @ Bits 14:12 SMPx[2:0]: Channel 14 Sample time selection
.EQU  ADC_SMPR1_SMP13_N, 9                         @ Bits 11:9 SMPx[2:0]: Channel 13 Sample time selection
.EQU  ADC_SMPR1_SMP12_N, 6                         @ Bits 8:6 SMPx[2:0]: Channel 12 Sample time selection
.EQU  ADC_SMPR1_SMP11_N, 3                         @ Bits 5:3 SMPx[2:0]: Channel 11 Sample time selection
.EQU  ADC_SMPR1_SMP10_N, 0                         @ Bits 2:0 SMPx[2:0]: Channel 10 Sample time selection
@.END

@.ITEM     ADC_SMPR2
.EQU  ADC_SMPR2_SMP9_N, 27                         @ Bits 29:27 SMPx[2:0]: Channel 9 Sample time selection
.EQU  ADC_SMPR2_SMP8_N, 24                         @ Bits 26:24 SMPx[2:0]: Channel 8 Sample time selection
.EQU  ADC_SMPR2_SMP7_N, 21                         @ Bits 23:21 SMPx[2:0]: Channel 7 Sample time selection
.EQU  ADC_SMPR2_SMP6_N, 18                         @ Bits 20:18 SMPx[2:0]: Channel 6 Sample time selection
.EQU  ADC_SMPR2_SMP5_N, 15                         @ Bits 17:15 SMPx[2:0]: Channel 5 Sample time selection
.EQU  ADC_SMPR2_SMP4_N, 12                         @ Bits 14:12 SMPx[2:0]: Channel 4 Sample time selection
.EQU  ADC_SMPR2_SMP3_N, 9                          @ Bits 11:9 SMPx[2:0]: Channel 3 Sample time selection
.EQU  ADC_SMPR2_SMP2_N, 6                          @ Bits 8:6 SMPx[2:0]: Channel 2 Sample time selection
.EQU  ADC_SMPR2_SMP1_N, 3                          @ Bits 5:3 SMPx[2:0]: Channel 1 Sample time selection
.EQU  ADC_SMPR2_SMP0_N, 0                          @ Bits 2:0 SMPx[2:0]: Channel 0 Sample time selection
@.END

@.ITEM     ADC_JOFR1 ADC_JOFR2 ADC_JOFR3 ADC_JOFR4
.EQU  ADC_JOFR_M     , 0x0FFF                      @ Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
@.END

@.ITEM     ADC_HTR
.EQU  ADC_HTR_M      , 0x0FFF                      @ Bits 11:0 HT[11:0]: Analog watchdog high threshold
@.END

@.ITEM     ADC_LTR
.EQU  ADC_LTR_M      , 0x0FFF                      @ Bits 11:0 LT[11:0]: Analog watchdog low threshold
@.END

@.ITEM     ADC_SQR1
.EQU  ADC_SQR1_L_N   , 20                          @ Bits 23:20 L[3:0]: Regular channel sequence length
.EQU  ADC_SQR1_L_M   , 0xF << 20                   @ Length mask
.EQU  ADC_SQR1_SQ16_N, 15                          @ Bits 19:15 SQ16[19:15]: 16th conversion in regular sequence
.EQU  ADC_SQR1_SQ15_N, 10                          @ Bits 14:10 SQ15[14:10]: 15th conversion in regular sequence
.EQU  ADC_SQR1_SQ14_N, 5                           @ Bits 9:5 SQ14[9:5]: 14th conversion in regular sequence
.EQU  ADC_SQR1_SQ13_N, 0                           @ Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
@.END

@.ITEM     ADC_SQR2
.EQU  ADC_SQR2_SQ12_N, 25                          @ Bits 29:25 SQ12[29:25]: 12th conversion in regular sequence
.EQU  ADC_SQR2_SQ11_N, 20                          @ Bits 24:20 SQ11[24:20]: 11th conversion in regular sequence
.EQU  ADC_SQR2_SQ10_N, 15                          @ Bits 19:15 SQ10[19:15]: 10th conversion in regular sequence
.EQU  ADC_SQR2_SQ9_N , 10                          @ Bits 14:10 SQ9[14:10]: 9th conversion in regular sequence
.EQU  ADC_SQR2_SQ8_N , 5                           @ Bits 9:5 SQ8[9:5]: 8th conversion in regular sequence
.EQU  ADC_SQR2_SQ7_N , 0                           @ Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
@.END

@.ITEM     ADC_SQR3
.EQU  ADC_SQR3_SQ6_N , 25                          @ Bits 29:25 SQ6[29:25]: 6th conversion in regular sequence
.EQU  ADC_SQR3_SQ5_N , 20                          @ Bits 24:20 SQ5[24:20]: 5th conversion in regular sequence
.EQU  ADC_SQR3_SQ4_N , 15                          @ Bits 19:15 SQ4[19:15]: 4th conversion in regular sequence
.EQU  ADC_SQR3_SQ3_N , 10                          @ Bits 14:10 SQ3[14:10]: 3th conversion in regular sequence
.EQU  ADC_SQR3_SQ2_N , 5                           @ Bits 9:5 SQ2[9:5]: 2th conversion in regular sequence
.EQU  ADC_SQR3_SQ1_N , 0                           @ Bits 4:0 SQ1[4:0]: 1th conversion in regular sequence
@.END

@.ITEM     ADC_JSQR
.EQU  ADC_JSQR_JL_N  , 20                          @ Bits 21:20 JL[1:0]: Injected sequence length
.EQU  ADC_JSQR_JL_1  , 0                           @ 00: 1 conversion
.EQU  ADC_JSQR_JL_2  , 1 << 20                     @ 01: 2 conversion
.EQU  ADC_JSQR_JL_3  , 2 << 20                     @ 10: 3 conversion
.EQU  ADC_JSQR_JL_4  , 3 << 20                     @ 11: 4 conversion
.EQU  ADC_JSQR_JSQ4_N, 15                          @ Bits 19:15 JSQ4[19:15]: 4th conversion in injected sequence (when JL[1:0] = 3
.EQU  ADC_JSQR_JSQ3_N, 10                          @ Bits 14:10 JSQ3[14:10]: 3rd conversion in injected sequence (when JL[1:0] = 3)
.EQU  ADC_JSQR_JSQ2_N, 5                           @ Bits 9:5 JSQ2[9:5]: 2nd conversion in injected sequence (when JL[1:0] = 3)
.EQU  ADC_JSQR_JSQ1_N, 0                           @ Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0] = 3)
@.END


