@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы PWR                        |
@ |                     STM32F100   STM32F103                        |
@ +------------------------------------------------------------------+
@.enddesc


.include "/src/inc/base.inc"

@.item APB1PERIPH_BASE
.equ PWR_BASE            , (APB1PERIPH_BASE + 0x7000)
@.end

@.item PWR_BASE
.equ PWR_CR              , 0x00       @ Power co ntrol re gister (PWR_CR)
.equ PWR_CSR             , 0x04       @ Power control/status register (PWR_CSR)
@.end

@.item PWR_CR
.equ PWR_CR_RST_VAL      , 0x00000000 @ значение по умолчанию
.equ PWR_CR_LPDS         , 0x01       @ Bit 0 LPDS: Low-power deepsleep.
                                      @ This bit is set and cleared by software. It works together with the PDDS bit.
                                      @ 0: Voltage regulator on during Stop mode
                                      @ 1: Voltage regulator in low-power mode during Stop mode
                                      @
.equ PWR_CR_PDDS         , 0x02       @ Enter Standby mode when the CPU enters Deepsleep
                                      @ This bit is set and cleared by software. It works together with the LPDS bit.
                                      @ 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit.
                                      @ 1: Enter Standby mode when the CPU enters Deepsleep.
                                      @
.equ PWR_CR_CWUF         , 0x04       @ Bit 2 CWUF: Clear wakeup flag.
                                      @ This bit is always read as 0.
                                      @ 0: No effect
                                      @ 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
                                      @
.equ PWR_CR_CSBF         , 0x08       @ Bit 3 CSBF: Clear standby flag.
                                      @ This bit is always read as 0.
                                      @ 0: No effect
                                      @ 1: Clear the SBF Standby Flag (write).
                                      @
.equ PWR_CR_PVDE         , 0x10       @ Bit 4 PVDE: programmable voltage detector enable.
                                      @ This bit is set and cleared by software.
                                      @ 0: PVD disabled
                                      @ 1: PVD enabled
                                      @
.EQU  PWR_CR_PLS_N       , 5          @ Bits 7:5 PLS[2:0]: PVD level selection.
                                      @ These bits are written by software to select the voltage threshold detected by the
                                      @ programmable voltage detector
.EQU  PWR_CR_PLS_2D0V    , 0 << 5     @ 2.2 v
.EQU  PWR_CR_PLS_2D1V    , 1 << 5     @ 2.3 v
.equ PWR_CR_PLS_2D3V     , 2<<5       @ 2.4 v
.equ PWR_CR_PLS_2D5V     , 3<<5       @ 2.5 v
.equ PWR_CR_PLS_2D6V     , 4<<5       @ 2.6 v
.equ PWR_CR_PLS_2D7V     , 5<<5       @ 2.7 v
.equ PWR_CR_PLS_2D8V     , 6<<5       @ 2.8 v
.equ PWR_CR_PLS_2D9V     , 7<<5       @ 2.9 v
                                      @
.equ PWR_CR_DBP          , 0x01<<8    @ Bit 8 DBP: Disable backup domain write protection.
                                      @ In reset state, the RTC and backup registers are protected against parasitic write access.
                                      @ This bit must be set to enable write access to these registers.
                                      @ 0: Access to RTC and Backup registers disabled
                                      @ 1: Access to RTC and Backup registers enabled
                                      @ Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
@.end

@.item PWR_CSR
.EQU  PWR_CSR_RST_VAL    , 0x00000000 @ значение по умолчанию
.EQU  PWR_CSR_EWUP       , 0x01 << 8  @ Bit 8 EWUP: Enable WKUP pin
                                      @ This bit is set and cleared by software.
                                      @ 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
                                      @ the device from Standby mode.
                                      @ 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
                                      @ configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
                                      @ Note: This bit is reset by a system Reset.
                                      @
.equ PWR_CSR_PVDO        , 0x01<<2    @ Bit 2 PVDO: PVD output
                                      @ This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
                                      @ 0: VDD/VDDA is higher than the PVD threshold selected with the PLS[2:0] bits.
                                      @ 1: VDD/VDDA is lower than the PVD threshold selected with the PLS[2:0] bits.
                                      @ Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
                                      @ Standby or reset until the PVDE bit is set.
                                      @
.equ PWR_CSR_SBF         , 0x01<<1    @ Bit 1 SBF: Standby flag
                                      @ This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)
                                      @ or by setting the CSBF bit in the Power control register (PWR_CR)
                                      @ 0: Device has not been in Standby mode
                                      @ 1: Device has been in Standby mode
                                      @
.equ PWR_CSR_WUF         , 0x01       @ Bit 0 WUF: Wakeup flag
                                      @ This bit is set by hardware and cleared by hardware, by a system reset or by setting the
                                      @ CWUF bit in the Power control register (PWR_CR)
                                      @ 0: No wakeup event occurred
                                      @ 1: A wakeup event was received from the WKUP pin or from the RTC alarm
                                      @ Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
                                      @ EWUP bit) when the WKUP pin level is already high.
@.end

