@.CHARSET CP1251

@.ITEM     SDIO SDIO_BASE
.EQU  SDIO_POWER    , 0x00    @ SDIO power control register (SDIO_POWER)
.EQU  SDIO_CLKCR    , 0x04    @ SDIO clock control register (SDIO_CLKCR)
.EQU  SDIO_ARG      , 0x08    @ SDIO argument register (SDIO_ARG)
.EQU  SDIO_CMD      , 0x0C    @ SDIO command register (SDIO_CMD)
.EQU  SDIO_RESPCMD  , 0x10    @ SDIO command response register (SDIO_RESPCMD)
.EQU  SDIO_RESP1    , 0x14    @ SDIO response 1..4 register (SDIO_RESPx)
.EQU  SDIO_RESP2    , 0x18    @ SDIO response 1..4 register (SDIO_RESPx)
.EQU  SDIO_RESP3    , 0x1C    @ SDIO response 1..4 register (SDIO_RESPx)
.EQU  SDIO_RESP4    , 0x20    @ SDIO response 1..4 register (SDIO_RESPx)
.EQU  SDIO_DTIMER   , 0x24    @ SDIO data timer register (SDIO_DTIMER)
.EQU  SDIO_DLEN     , 0x28    @ SDIO data length register (SDIO_DLEN)
.EQU  SDIO_DCTRL    , 0x2C    @ SDIO data control register (SDIO_DCTRL)
.EQU  SDIO_DCOUNT   , 0x30    @ SDIO data counter register (SDIO_DCOUNT)
.EQU  SDIO_STA      , 0x34    @ SDIO status register (SDIO_STA)
.EQU  SDIO_ICR      , 0x38    @ SDIO interrupt clear register (SDIO_ICR)
.EQU  SDIO_MASK     , 0x3C    @ SDIO mask register (SDIO_MASK)
.EQU  SDIO_FIFOCNT  , 0x48    @ SDIO FIFO counter register (SDIO_FIFOCNT)
.EQU  SDIO_FIFO     , 0x80    @ SDIO data FIFO register (SDIO_FIFO)
@.END

@.ITEM     SDIO_POWER
.EQU  SDIO_POWER_PWRCTRL_N, 0    @ [1:0] PWRCTRL: Power supply control bits.
                                 @ These bits are used to define the current functional state of the card clock:
                                 @ 00: Power-off: the clock to card is stopped.
                                 @ 01: Reserved
                                 @ 10: Reserved power-up
                                 @ 11: Power-on: the card is clocked.
@.END

@.ITEM SDIO_CLKCR
.EQU  SDIO_CLKCR_HWFC_EN, 1 << 14    @ Bit 14 HWFC_EN: HW Flow Control enable
                                 @ 0b: HW Flow Control is disabled
                                 @ 1b: HW Flow Control is enabled
                                 @ When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt
                                 @ signals, see SDIO Status register definition in Section 22.9.11.
.EQU  SDIO_CLKCR_NEGEDGE, 1 << 13    @ Bit 13 NEGEDGE:SDIO_CK dephasing selection bit
                                 @ 0b: SDIO_CK generated on the rising edge of the master clock SDIOCLK
                                 @ 1b: SDIO_CK generated on the falling edge of the master clock SDIOCLK
.EQU  SDIO_CLKCR_WIDBUS_N, 11    @ Bits 12:11 WIDBUS: Wide bus mode enable bit
.EQU  SDIO_CLKCR_WIDBUS_D0, 0    @ 00: Default bus mode: SDIO_D0 used
.EQU  SDIO_CLKCR_WIDBUS_D4, 1    @ 01: 4-wide bus mode: SDIO_D[3:0] used
.EQU  SDIO_CLKCR_WIDBUS_D8, 2    @ 10: 8-wide bus mode: SDIO_D[7:0] used
.EQU  SDIO_CLKCR_BYPASS, 1 << 10    @Bit 10 BYPASS: Clock divider bypass enable bit
                                    @ 0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the
                                    @    SDIO_CK output signal.
                                    @ 1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal.
.EQU  SDIO_CLKCR_PWRSAV, 1 << 9    @ Bit 9 PWRSAV: Power saving configuration bit
                                   @ For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting
                                   @ PWRSAV:
                                   @ 0: SDIO_CK clock is always enabled
                                   @ 1. SDIO_CK is only enabled when the bus is active
.EQU  SDIO_CLKCR_CLKEN, 1 << 8    @ Bit 8 CLKEN: Clock enable bit
                                  @ 0: SDIO_CK is disabled
                                  @ 1: SDIO_CK is enabled
.EQU  SDIO_CLKCR_CLKDIV_N, 0    @ Bits 7:0 CLKDIV: Clock divide factor
                                @ This field defines the divide factor between the input clock (SDIOCLK) and the output clock
                                @ (SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].
@ Note: While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK
@ frequency must be less than 400 kHz.
@ The clock frequency can be changed to the maximum card bus frequency when relative
@ card addresses are assigned to all cards.
@ At least seven HCLK clock periods are needed between two write accesses to this register.
@ SDIO_CK can also be stopped during the read wait interval for SD I/O cards: in this case the
@SDIO_CLKCR register does not control SDIO_CK.
@.END

@.ITEM SDIO_CMD
.EQU  SDIO_CMD_ATACMD, 1 << 14   @ Bit 14 ATACMD: CE-ATA command If ATACMD is set, the CPSM transfers CMD61.
.EQU  SDIO_CMD_nIEN , 1 << 13    @ Bit 13 nIEN: not Interrupt Enable if this bit is 0, interrupts in the CE-ATA device are enabled.
.EQU  SDIO_CMD_ENCMDcompl, 1 << 12    @ Bit 12 ENCMDcompl: Enable CMD completion If this bit is set, the command completion signal is enabled.
.EQU  SDIO_CMD_SDIOsuspend, 1 << 11    @ Bit 11 SDIOSuspend: SD I/O suspend command If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card).
.EQU  SDIO_CMD_CPSMEN, 1 << 10    @ Bit 10 CPSMEN: Command path state machine (CPSM) Enable bit If this bit is set, the CPSM is enabled.
.EQU  SDIO_CMD_WAITPEND, 1 << 9    @ Bit 9 WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal). If this bit is set, the CPSM waits for the end of data transfer before it starts sending a command.
.EQU  SDIO_CMD_WAITINT, 1 << 8    @ Bit 8 WAITINT: CPSM waits for interrupt request If this bit is set, the CPSM disables command timeout and waits for an interrupt request.
.EQU SDIO_CMD_WAITRESP_N, 6 @ Bits 7:6 WAITRESP: Wait for response bits
@ They are used to configure whether the CPSM is to wait for a response, and if yes, which
@ kind of response.
.EQU  SDIO_CMD_WAITRESP_0, 0    @ 00: No response, expect CMDSENT flag
.EQU  SDIO_CMD_WAITRESP_1, 1    @ 01: Short response, expect CMDREND or CCRCFAIL flag
.EQU  SDIO_CMD_WAITRESP_2, 2    @ 10: No response, expect CMDSENT flag
.EQU  SDIO_CMD_WAITRESP_3, 3    @ 11: Long response, expect CMDREND or CCRCFAIL flag
.EQU  SDIO_CMD_CMDINDEX_N, 0    @ Bit 5:0 CMDINDEX: Command index
                                @ The command index is sent to the card as part of a command message.
@.END

@.ITEM SDIO_DCTRL
.EQU  SDIO_DCTRL_SDIOEN, 1 << 11    @ Bit 11 SDIOEN: SD I/O enable functions If this bit is set, the DPSM performs an SD I/O-card-specific operation.
.EQU  SDIO_DCTRL_RWMOD, 1 << 10    @ Bit 10 RWMOD: Read wait mode
                                   @ 0: Read Wait control stopping SDIO_D2
                                   @ 1: Read Wait control using SDIO_CK
.EQU  SDIO_DCTRL_RWSTOP, 1 << 9    @ Bit 9 RWSTOP: Read wait stop
                                   @ 0: Read wait in progress if RWSTART bit is set
                                   @ 1: Enable for read wait stop if RWSTART bit is set
.EQU  SDIO_DCTRL_RWSTART, 1 << 8   @ Bit 8 RWSTART: Read wait start If this bit is set, read wait operation starts.
.EQU  SDIO_DCTRL_DBLOCKSIZE_N, 4    @ Bits 7:4 DBLOCKSIZE: Data block size
                                    @ Define the data block length when the block data transfer mode is selected:
                                    @ 0000: (0 decimal) lock length = 20 = 1 byte
                                    @ 0001: (1 decimal) lock length = 21 = 2 bytes
                                    @ 0010: (2 decimal) lock length = 22 = 4 bytes
                                    @ 0011: (3 decimal) lock length = 23 = 8 bytes
                                    @ 0100: (4 decimal) lock length = 24 = 16 bytes
                                    @ 0101: (5 decimal) lock length = 25 = 32 bytes
                                    @ 0110: (6 decimal) lock length = 26 = 64 bytes
                                    @ 0111: (7 decimal) lock length = 27 = 128 bytes
                                    @ 1000: (8 decimal) lock length = 28 = 256 bytes
                                    @ 1001: (9 decimal) lock length = 29 = 512 bytes
                                    @ 1010: (10 decimal) lock length = 210 = 1024 bytes
                                    @ 1011: (11 decimal) lock length = 211 = 2048 bytes
                                    @ 1100: (12 decimal) lock length = 212 = 4096 bytes
                                    @ 1101: (13 decimal) lock length = 213 = 8192 bytes
                                    @ 1110: (14 decimal) lock length = 214 = 16384 bytes
                                    @ 1111: (15 decimal) reserved
.EQU  SDIO_DCTRL_DMAEN, 1 << 3    @ Bit 3 DMAEN: DMA enable bit 0: DMA disabled. 1: DMA enabled.
.EQU  SDIO_DCTRL_DTMODE, 1 << 2    @  Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
                                   @ 0: Block data transfer
                                   @ 1: Stream or SDIO multibyte data transfer on STM32F10xxx XL-density devices.
                                   @ Stream data transfer on STM32F10xxx high-density devices.
.EQU  SDIO_DCTRL_DTDIR, 1 << 1    @ Bit 1 DTDIR: Data transfer direction selection
                                  @ 0: From controller to card.
                                  @ 1: From card to controller.
.EQU  SDIO_DCTRL_DTEN, 1      @ [0] DTEN: Data transfer enabled bit
                              @ Data transfer starts if 1b is written to the DTEN bit. Depending on the direction bit, DTDIR,
                              @ the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at
                              @ the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data
                              @ transfer but the SDIO_DCTRL must be updated to enable a new data transfer
@.END

@.ITEM SDIO_STA
.EQU  SDIO_STA_CEATAEND, 1 << 23    @ Bit 23 CEATAEND: CE-ATA command completion signal received for CMD61
.EQU  SDIO_STA_SDIOIT, 1 << 22    @ Bit 22 SDIOIT: SDIO interrupt received
.EQU  SDIO_STA_RXDAVL, 1 << 21    @ Bit 21 RXDAVL: Data available in receive FIFO
.EQU  SDIO_STA_TXDAVL, 1 << 20    @ Bit 20 TXDAVL: Data available in transmit FIFO
.EQU  SDIO_STA_RXFIFOE, 1 << 19    @ Bit 19 RXFIFOE: Receive FIFO empty
.EQU  SDIO_STA_TXFIFOE, 1 << 18    @ Bit 18 TXFIFOE: Transmit FIFO empty
                                   @ When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO
                                   @ contains 2 words.
.EQU  SDIO_STA_RXFIFOF, 1 << 17    @ Bit 17 RXFIFOF: Receive FIFO full
                                   @ When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the
                                   @ FIFO is full.
.EQU  SDIO_STA_TXFIFOF, 1 << 16    @ Bit 16 TXFIFOF: Transmit FIFO full
.EQU  SDIO_STA_RXFIFOHF, 1 << 15    @ Bit 15 RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO
.EQU  SDIO_STA_TXFIFOHE, 1 << 14    @ Bit 14 TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into the FIFO
.EQU  SDIO_STA_RXACT, 1 << 13    @ Bit 13 RXACT: Data receive in progress
.EQU  SDIO_STA_TXACT, 1 << 12    @ Bit 12 TXACT: Data transmit in progress
.EQU  SDIO_STA_CMDACT, 1 << 11    @ Bit 11 CMDACT: Command transfer in progress
.EQU  SDIO_STA_DBCKEND, 1 << 10    @ Bit 10 DBCKEND: Data block sent/received (CRC check passed)
.EQU  SDIO_STA_STBITERR, 1 << 9    @ Bit 9 STBITERR: Start bit not detected on all data signals in wide bus mode
.EQU  SDIO_STA_DATAEND, 1 << 8    @ Bit 8 DATAEND: Data end (data counter, SDIDCOUNT, is zero)
.EQU  SDIO_STA_CMDSENT, 1 << 7    @ Bit 7 CMDSENT: Command sent (no response required)
.EQU  SDIO_STA_CMDREND, 1 << 6    @ Bit 6 CMDREND: Command response received (CRC check passed)
.EQU  SDIO_STA_RXOVERR, 1 << 5    @  Bit 5 RXOVERR: Received FIFO overrun error
.EQU  SDIO_STA_TXUNDERR, 1 << 4    @ Bit 4 TXUNDERR: Transmit FIFO underrun error
.EQU  SDIO_STA_DTIMEOUT, 1 << 3    @ Bit 3 DTIMEOUT: Data timeout
.EQU  SDIO_STA_CTIMEOUT, 1 << 2    @ Bit 2 CTIMEOUT: Command response timeout
                                   @ The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.
.EQU  SDIO_STA_DCRFAIL, 1 << 1    @ Bit 1 DCRCFAIL: Data block sent/received (CRC check failed)
.EQU  SDIO_STA_CCRCFAIL, 1    @ Bit 0 CCRCFAIL: Command response received (CRC check failed)
@.END

@.item     SDIO_ICR
.equ  SDIO_ICR_CEATAENDC , 1 << 23    @Bit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable
.equ  SDIO_ICR_SDIOITC   , 1 << 22    @Bit 22 SDIOITIE : SDIO mode interrupt received interrupt enable
.equ  SDIO_ICR_DBCKENDC  , 1 << 10    @Bit 10 DBCKENDIE : Data block end interrupt enable
.equ  SDIO_ICR_STBITERRC , 1 << 9    @Bit 9 STBITERRIE: Start bit error interrupt enable
.equ  SDIO_ICR_DATAENDC  , 1 << 8    @Bit 8 DATAENDIE: Data end interrupt enable
.equ  SDIO_ICR_CMDSENTC  , 1 << 7    @Bit 7 CMDSENTIE: Command sent interrupt enable
.equ  SDIO_ICR_CMDRENDC  , 1 << 6    @Bit 6 CMDRENDIE: Command response received interrupt enable
.equ  SDIO_ICR_RXOVERRC  , 1 << 5    @Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable
.equ  SDIO_ICR_TXUNDERRC , 1 << 4    @Bit 4 TXUNDERRIE: Tx FIFO underrun error interrupt enable
.equ SDIO_ICR_DTIMEOUTC, 0x00000008 @Bit 3 DTIMEOUTIE: Data timeout interrupt enable
.equ SDIO_ICR_CTIMEOUTC, 0x00000004 @Bit 2 CTIMEOUTIE: Command timeout interrupt enable
.equ SDIO_ICR_DCRCFAILC, 0x00000002 @Bit 1 DCRCFAILIE: Data CRC fail interrupt enable
.equ SDIO_ICR_CCRCFAILC, 0x00000001 @Bit 0 CCRCFAILIE: Command CRC fail interrupt enable
@.end

@.item     SDIO_MASK
.equ  SDIO_MASK_CEATAENDIE, 1 << 23    @Bit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable
.equ  SDIO_MASK_SDIOITIE , 1 << 22    @Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable
.equ  SDIO_MASK_RXDAVLIE , 1 << 21    @Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable
.equ  SDIO_MASK_TXDAVLIE , 1 << 20    @Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable
.equ  SDIO_MASK_RXFIFOEIE, 1 << 19    @Bit 19 RXFIFOEIE: Rx FIFO empty interrupt enable
.equ  SDIO_MASK_TXFIFOEIE, 1 << 18    @Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable
.equ  SDIO_MASK_RXFIFOFIE, 1 << 17    @Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable
.equ  SDIO_MASK_TXFIFOFIE, 1 << 16    @Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable
.equ  SDIO_MASK_RXFIFOHFIE, 1 << 15    @Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable
.equ  SDIO_MASK_TXFIFOHEIE, 1 << 14    @Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable
.equ  SDIO_MASK_RXACTIE  , 1 << 13    @Bit 13 RXACTIE: Data receive acting interrupt enable
.equ  SDIO_MASK_TXACTIE  , 1 << 12    @Bit 12 TXACTIE: Data transmit acting interrupt enable
.equ  SDIO_MASK_CMDACTIE , 1 << 11    @Bit 11 CMDACTIE: Command acting interrupt enable
.equ  SDIO_MASK_DBCKENDIE, 1 << 10    @Bit 10 DBCKENDIE: Data block end interrupt enable
.equ  SDIO_MASK_STBITERRIE, 1 << 9    @Bit 9 STBITERRIE: Start bit error interrupt enable
.equ  SDIO_MASK_DATAENDIE, 1 << 8    @Bit 8 DATAENDIE: Data end interrupt enable
.equ  SDIO_MASK_CMDSENTIE, 1 << 7    @Bit 7 CMDSENTIE: Command sent interrupt enable
.equ  SDIO_MASK_CMDRENDIE, 1 << 6    @Bit 6 CMDRENDIE: Command response received interrupt enable
.equ  SDIO_MASK_RXOVERRIE, 1 << 5    @Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable
.equ  SDIO_MASK_TXUNDERRIE, 1 << 4    @Bit 4 TXUNDERRIE : Tx FIFO underrun error interrupt enable
.equ  SDIO_MASK_DTIMEOUTIE, 1 << 3    @Bit 3 DTIMEOUTIE: Data timeout interrupt enable
.equ  SDIO_MASK_CTIMEOUTIE, 1 << 2    @Bit 2 CTIMEOUTIE: Command timeout interrupt enable
.equ  SDIO_MASK_DCRCFAILIE, 1 << 1    @Bit 1 DCRCFAILIE: Data CRC fail interrupt enable
.equ  SDIO_MASK_CCRCFAILIE, 0x00000001    @Bit 0 CCRCFAILIE: Command CRC fail interrupt enable
@.end




