@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  TIM2_BASE      , APB1PERIPH_BASE
.EQU  TIM2           , PERIPH_BASE + TIM2_BASE

@.ITEM     TIM2 TIM2_BASE
.EQU  TIM2T5_CR1       , 0x00                        @ TIM2T5 control register 1 (TIMx_CR1)
.EQU  TIM2T5_CR2       , 0x04                        @ TIM2T5 control register 2 (TIMx_CR2)
.EQU  TIM2T5_SMCR      , 0x08                        @ TIM2T5 slave mode control register (TIMx_SMCR)
.EQU  TIM2T5_DIER      , 0X0C                        @ TIM2T5 DMA/interrupt enable register (TIMx_DIER)
.EQU  TIM2T5_SR        , 0X10                        @ TIM2T5 status register (TIMx_SR)
.EQU  TIM2T5_EGR       , 0X14                        @ TIM2T5 event generation register (TIMx_EGR)
.EQU  TIM2T5_CCMR1     , 0X18                        @ TIM2T5 capture/compare mode register 1 (TIMx_CCMR1)
.EQU  TIM2T5_CCMR2     , 0X1C                        @ TIM2T5 capture/compare mode register 2 (TIMx_CCMR2)
.EQU  TIM2T5_CCER      , 0X20                        @ TIM2T5 capture/compare enable register (TIMx_CCER)
.EQU  TIM2T5_CNT       , 0X24                        @ TIM2T5 counter ( TIMx_CNT)
.EQU  TIM2T5_PSC       , 0X28                        @ TIM2T5 prescaler ( TIMx_PSC)
.EQU  TIM2T5_ARR       , 0X2C                        @ TIM2T5 auto-reload register (TIMx_ARR)
.EQU  TIM2T5_CCR1      , 0X34                        @ TIM2T5 capture/compare register 1 (TIMx_CCR1)
.EQU  TIM2T5_CCR2      , 0X38                        @ TIM2T5 capture/compare register 2 (TIMx_CCR2)
.EQU  TIM2T5_CCR3      , 0X3C                        @ TIM2T5 capture/compare register 3 (TIMx_CCR3)
.EQU  TIM2T5_CCR4      , 0X40                        @ TIM2T5 capture/compare register 4 (TIMx_CCR4)
.EQU  TIM2T5_DCR       , 0X48                        @ TIM2T5 DMA control register (TIMx_DCR)
.EQU  TIM2T5_DMAR      , 0X4C                        @ TIM2T5 DMA address for full transfer (TIMx_DMAR)


@.ITEM     TIM2T5_CR1
.EQU  TIM2T5_CR1_CKD_N , 8                           @ Bits 9:8 CKD[1:0]: Clock division
.EQU  TIM2T5_CR1_CKD_1TCK, 0                         @ 00: tDTS=tCK_INT
.EQU  TIM2T5_CR1_CKD_2TCK, 1 << 8                    @ 01: tDTS=2*tCK_INT
.EQU  TIM2T5_CR1_CKD_4TCK, 2 << 8                    @ 10: tDTS=4*tCK_INT
.EQU  TIM2T5_CR1_APRE  , 1 << 7                      @ Bit 7 ARPE: Auto-reload preload enable
.EQU  TIM2T5_CR1_CMS_N , 5                           @ Bits 6:5 CMS[1:0]: Center-aligned mode selection
.EQU  TIM2T5_CR1_CMS_EDGEALIGN, 0                    @ 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
.EQU  TIM2T5_CR1_CMS_CENTALIGN1, 1 << 5              @ 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
.EQU  TIM2T5_CR1_CMS_CENTALIGN2, 2 << 5              @ 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
.EQU  TIM2T5_CR1_CMS_CENTALIGN3, 3 << 5              @ 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
.EQU  TIM2T5_CR1_DIR   , 1 << 4                      @ Bit 4 DIR: Direction (Counter used as downcounter)
.EQU  TIM2T5_CR1_OPM   , 1 << 3                      @ Bit 3 OPM: One pulse mode
.EQU  TIM2T5_CR1_URS   , 1 << 2                      @ Bit 2 URS: Update request source
.EQU  TIM2T5_CR1_UDIS  , 1 << 1                      @ Bit 1 UDIS: Update disable
.EQU  TIM2T5_CR1_CEN   , 1                           @ Bit 0 CEN: Counter enable

@.ITEM     TIM2T5_CR2
.EQU  TIM2T5_CR2_TI1S      , 1 << 7                      @ Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input; 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
.EQU  TIM2T5_CR2_MMS_N     , 4                           @ Bits 6:4 MMS[2:0]: Master mode selection
.EQU  TIM2T5_CR2_MMS_RESET , 0                           @ 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
.EQU  TIM2T5_CR2_MMS_ENABLE, 1 << 4                      @ 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
.EQU  TIM2T5_CR2_MMS_UPDATE, 2 << 4                      @ 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
.EQU  TIM2T5_CR2_MMS_COMPPULSE, 3 << 4                   @ 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
.EQU  TIM2T5_CR2_MMS_COMP_OC1REF, 4 << 4                 @ 100: Compare - OC1REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_MMS_COMP_OC2REF, 5 << 4                 @ 101: Compare - OC2REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_MMS_COMP_OC3REF, 6 << 4                 @ 110: Compare - OC3REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_MMS_COMP_OC4REF, 7 << 4                 @ 111: Compare - OC4REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_CCDS, 1 << 3                      @ Bit 3 CCDS: Capture/compare DMA selection; 0: CCx DMA request sent when CCx event occurs; 1: CCx DMA requests sent when update event occurs

@.ITEM     TIM2T5_SMCR
.EQU  TIM2T5_SMCR_ETP  , 1 << 15                     @ Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations; 0: ETR is non-inverted, active at high level or rising edge; 1: ETR is inverted, active at low level or falling edge
.EQU  TIM2T5_SMCR_ECE  , 1 << 14                     @ Bit 14 ECE: External clock enable This bit enables External clock mode 2.; 0: External clock mode 2 disabled; 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
.EQU  TIM2T5_SMCR_ETPS_N, 12                         @ Bits 13:12 ETPS[1:0]: External trigger prescaler
.EQU  TIM2T5_SMCR_ETPS_NOPRESC, 0                    @ 00: Prescaler OFF
.EQU  TIM2T5_SMCR_ETPS_DIV2, 1 << 12                 @ 01: ETRP frequency divided by 2
.EQU  TIM2T5_SMCR_ETPS_DIV4, 2 << 12                 @ 10: ETRP frequency divided by 4
.EQU  TIM2T5_SMCR_ETPS_DIV8, 3 << 12                 @ 11: ETRP frequency divided by 8
.EQU  TIM2T5_SMCR_ETF_N, 8                           @ Bits 11:8 ETF[3:0]: External trigger filter
.EQU  TIM2T5_SMCR_ETF_NOFCKLT, 0                     @ 0000: No filter, sampling is done at fDTS
.EQU  TIM2T5_SMCR_ETF_FCKN2, 1 << 8                  @ 0001: fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_SMCR_ETF_FCKN4, 2 << 8                  @ 0010: fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_SMCR_ETF_FCKN8, 3 << 8                  @ 0011: fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_SMCR_ETF_DTS2N6, 4 << 8                 @ 0100: fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_SMCR_ETF_DTS2N8, 5 << 8                 @ 0101: fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_SMCR_ETF_DTS4N6, 6 << 8                 @ 0110: fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_SMCR_ETF_DTS4N8, 7 << 8                 @ 0111: fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_SMCR_ETF_DTS8N6, 8 << 8                 @ 1000: fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_SMCR_ETF_DTS8N8, 9 << 8                 @ 1001: fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_SMCR_ETF_DTS16N5, 10 << 8               @ 1010: fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_SMCR_ETF_DTS16N6, 11 << 8               @ 1011: fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_SMCR_ETF_DTS16N8, 12 << 8               @ 1100: fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_SMCR_ETF_DTS32N5, 13 << 8               @ 1101: fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_SMCR_ETF_DTS32N6, 14 << 8               @ 1110: fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_SMCR_ETF_DTS32N8, 15 << 8               @ 1111: fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_SMCR_MSM  , 1 << 7                      @ Bit 7 MSM: Master/slave mode
.EQU  TIM2T5_SMCR_TS_N , 1 << 4                      @ Bits 6:4 TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter.
.EQU  TIM2T5_SMCR_TS_ITR0, 0                         @ 000: Internal Trigger 0 (ITR0)
.EQU  TIM2T5_SMCR_TS_ITR1, 1 << 4                    @ 001: Internal Trigger 1 (ITR1)
.EQU  TIM2T5_SMCR_TS_ITR2, 2 << 4                    @ 010: Internal Trigger 2 (ITR2)
.EQU  TIM2T5_SMCR_TS_ITR3, 3 << 4                    @ 011: Internal Trigger 3 (ITR3)
.EQU  TIM2T5_SMCR_TS_TI1F_ED, 4 << 4                 @ 100: TI1 Edge Detector (TI1F_ED)
.EQU  TIM2T5_SMCR_TS_TI1FP1, 5 << 4                  @ 101: Filtered Timer Input 1 (TI1FP1
.EQU  TIM2T5_SMCR_TS_TI2FP2, 6 << 4                  @ 110: Filtered Timer Input 2 (TI2FP2)
.EQU  TIM2T5_SMCR_TS_ETRF, 7 << 4                    @ 111: External Trigger input (ETRF)
.EQU  TIM2T5_SMCR_OCCS, 1 << 3                     @ Bit 3 OCCS: OCREF clear selection
.EQU  TIM2T5_SMCR_SMS_N, 0                           @ Bits 2:0 SMS: Slave mode selection
.EQU  TIM2T5_SMCR_SMS_SLD, 0                         @ 000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock
.EQU  TIM2T5_SMCR_SMS_ENC1, 1                        @ 001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level
.EQU  TIM2T5_SMCR_SMS_ENC2, 2                        @ 010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
.EQU  TIM2T5_SMCR_SMS_ENC3, 3                        @ 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
.EQU  TIM2T5_SMCR_SMS_RST, 4                         @ 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
.EQU  TIM2T5_SMCR_SMS_GATED, 5                       @ 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
.EQU  TIM2T5_SMCR_SMS_TRIG, 6                        @ 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
.EQU  TIM2T5_SMCR_SMS_EXTCLK, 7                      @ 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

@.ITEM     TIM2T5_DIER
.EQU  TIM2T5_DIER_TDE  , 1 << 14                     @ Bit 14 TDE: Trigger DMA request enable
.EQU  TIM2T5_DIER_CC4DE, 1 << 12                     @ Bit 12 CC4DE: Capture/Compare 4 DMA request enable
.EQU  TIM2T5_DIER_CC3DE, 1 << 11                     @ Bit 11 CC3DE: Capture/Compare 3 DMA request enable
.EQU  TIM2T5_DIER_CC2DE, 1 << 10                     @ Bit 10 CC2DE: Capture/Compare 2 DMA request enable
.EQU  TIM2T5_DIER_CC1DE, 1 << 9                      @ Bit 9 CC1DE: Capture/Compare 1 DMA request enable
.EQU  TIM2T5_DIER_UDE  , 1 << 8                      @ Bit 8 UDE: Update DMA request enable
.EQU  TIM2T5_DIER_TIE  , 1 << 6                      @ Bit 6 TIE: Trigger interrupt enable
.EQU  TIM2T5_DIER_CC4IE, 1 << 4                      @ Bit 4 CC4IE: Capture/Compare 4 interrupt enable
.EQU  TIM2T5_DIER_CC3IE, 1 << 3                      @ Bit 3 CC3IE: Capture/Compare 3 interrupt enable
.EQU  TIM2T5_DIER_CC2IE, 1 << 2                      @ Bit 2 CC2IE: Capture/Compare 2 interrupt enable
.EQU  TIM2T5_DIER_CC1IE, 1 << 1                      @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
.EQU  TIM2T5_DIER_UIE  , 1 << 0                      @ Bit 0 UIE: Update interrupt enable

@.ITEM     TIM2T5_SR
.EQU  TIM2T5_SR_CC4OF  , 1 << 12                     @ Bit 12 CC4OF: Capture/Compare 4 overcapture flag
.EQU  TIM2T5_SR_CC3OF  , 1 << 11                     @ Bit 11 CC3OF: Capture/Compare 3 overcapture flag
.EQU  TIM2T5_SR_CC2OF  , 1 << 10                     @ Bit 10 CC2OF: Capture/Compare 2 overcapture flag
.EQU  TIM2T5_SR_CC1OF  , 1 << 9                      @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
.EQU  TIM2T5_SR_TIF    , 1 << 6                      @ Bit 6 TIF: Trigger interrupt flag
.EQU  TIM2T5_SR_CC4IF  , 1 << 4                      @ Bit 4 CC4IF: Capture/Compare 4 interrupt flag
.EQU  TIM2T5_SR_CC3IF  , 1 << 3                      @ Bit 3 CC3IF: Capture/Compare 3 interrupt flag
.EQU  TIM2T5_SR_CC2IF  , 1 << 2                      @ Bit 2 CC2IF: Capture/Compare 2 interrupt flag
.EQU  TIM2T5_SR_CC1IF  , 1 << 1                      @ Bit 1 CC1IF: Capture/Compare 1 interrupt flag
.EQU  TIM2T5_SR_UIF    , 1 << 0                      @ Bit 0 UIF: Update interrupt flag

@.ITEM     TIM2T5_EGR
.EQU  TIM2T5_EGR_TG    , 1 << 6                      @ Bit 6 TG: Trigger generation
.EQU  TIM2T5_EGR_CC4G  , 1 << 4                      @ Bit 4 CC4G: Capture/Compare 4 generation
.EQU  TIM2T5_EGR_CC3G  , 1 << 3                      @ Bit 3 CC3G: Capture/Compare 3 generation
.EQU  TIM2T5_EGR_CC2G  , 1 << 2                      @ Bit 2 CC2G: Capture/Compare 2 generation
.EQU  TIM2T5_EGR_CC1G  , 1 << 1                      @ Bit 1 CC1G: Capture/Compare 1 generation
.EQU  TIM2T5_EGR_UG    , 1 << 0                      @ Bit 0 UG: Update generation

@.ITEM     TIM2T5_CCMR1
.EQU  TIM2T5_CCMR1_OC2CE, 1 << 15                    @ Bit 15 OC2CE: Output Compare 2 clear enable
.EQU  TIM2T5_CCMR1_OCxM_FROZ, 0                      @ 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
.EQU  TIM2T5_CCMR1_OCxM_SETCH1, 1                    @ 001: Set channel to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR1_OCxM_RSTCH1, 2                    @ 010: Set channel to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR1_OCxM_TGLCH1, 3                    @ 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
.EQU  TIM2T5_CCMR1_OCxM_FORCELOW, 4                  @ 100: Force inactive level - OC1REF is forced low
.EQU  TIM2T5_CCMR1_OCxM_FORCEHIGH, 5                 @ 101: Force active level - OC1REF is forced high
.EQU  TIM2T5_CCMR1_OCxM_PWM1, 6                      @ 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
.EQU  TIM2T5_CCMR1_OCxM_PWM2, 7                      @ 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1  else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.
.EQU  TIM2T5_CCMR1_OC2M_N, 12                        @ Bits 14:12 OC2M[2:0]: Output Compare 2 mode
.EQU  TIM2T5_CCMR1_OC2PE, 1 << 11                    @ Bit 11 OC2PE: Output Compare 2 preload enable
.EQU  TIM2T5_CCMR1_OC2FE, 1 << 10                    @ Bit 10 OC2FE: Output Compare 2 fast enable
.EQU  TIM2T5_CCMR1_CC2S_N, 8                         @ Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input
.EQU  TIM2T5_CCMR1_CC2S_CC2OUT, 0                    @ 00: CC2 channel is configured as output
.EQU  TIM2T5_CCMR1_CC2S_IC2_TO_TI2, 1 << 8           @ 01: CC2 channel is configured as input, IC2 is mapped on TI2
.EQU  TIM2T5_CCMR1_CC2S_IC2_TO_TI1, 2 << 8           @ 10: CC2 channel is configured as input, IC2 is mapped on TI1
.EQU  TIM2T5_CCMR1_CC2S_IC2_TO_TRC, 3 << 8           @ 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
.EQU  TIM2T5_CCMR1_OC1CE, 1 << 7                     @ Bit 7 OC1CE: Output Compare 1 clear enable
.EQU  TIM2T5_CCMR1_OC1M_N, 4                         @ Bits 6:4 OC1M: Output Compare 1 mode
.EQU  TIM2T5_CCMR1_OC1PE, 1 << 3                     @ Bit 3 OC1PE: Output Compare 1 preload enable
.EQU  TIM2T5_CCMR1_OC1FE, 1 << 2                     @ Bit 2 OC1FE: Output Compare 1 fast enable
.EQU  TIM2T5_CCMR1_CC1S_N, 0                         @ Bits 1:0 CC1S: Capture/Compare 1 selection
.EQU  TIM2T5_CCMR1_CC1S_CC1OUT, 0                    @ 00: CC1 channel is configured as output
.EQU  TIM2T5_CCMR1_CC1S_IC1_TO_TI1, 1                @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM2T5_CCMR1_CC1S_IC1_TO_TI2, 2                @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM2T5_CCMR1_CC1S_IC1_TO_TRC, 3                @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
.EQU  TIM2T5_CCMR1_IC2F_N, 12                        @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
.EQU  TIM2T5_CCMR1_ICxF_OFCKLT, 0                    @ 0000: No filter, sampling is done at fDTS
.EQU  TIM2T5_CCMR1_ICxF_CKN2, 1                      @ 0001: fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_CCMR1_ICxF_CKN4, 2                      @ 0010: fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_CCMR1_ICxF_CKN8, 3                      @ 0011: fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_CCMR1_ICxF_TS2N6, 4                     @ 0100: fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_CCMR1_ICxF_TS2N8, 5                     @ 0101: fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_CCMR1_ICxF_TS4N6, 6                     @ 0110: fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_CCMR1_ICxF_TS4N8, 7                     @ 0111: fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_CCMR1_ICxF_TS8N6, 8                     @ 1000: fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_CCMR1_ICxF_TS8N8, 9                     @ 1001: fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_CCMR1_ICxF_TS16N5, 10                   @ 1010: fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_CCMR1_ICxF_TS16N6, 11                   @ 1011: fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_CCMR1_ICxF_TS16N8, 12                   @ 1100: fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_CCMR1_ICxF_TS32N5, 13                   @ 1101: fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_CCMR1_ICxF_TS32N6, 14                   @ 1110: fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_CCMR1_ICxF_TS32N8, 15                   @ 1111: fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_CCMR1_IC2PSC_N, 10                      @ Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
.EQU  TIM2T5_CCMR1_ICxPSC_1, 0                       @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM2T5_CCMR1_ICxPSC_2, 1                       @ 01: capture is done once every 2 events
.EQU  TIM2T5_CCMR1_ICxPSC_4, 2                       @ 10: capture is done once every 4 events
.EQU  TIM2T5_CCMR1_ICxPSC_8, 3                       @ 11: capture is done once every 8 events
.EQU  TIM2T5_CCMR1_IÑ1F_N, 4                         @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
.EQU  TIM2T5_CCMR1_IC1PSC_N, 2                       @ Bits 3:2 IC1PSC: Input capture 1 prescaler

@.ITEM TIM2T5_CCMR2
.EQU  TIM2T5_CCMR2_OC4CE, 1 << 15                    @ Bit 15 OC4CE: Output compare 4 clear enable
.EQU  TIM2T5_CCMR2_OC4M_N, 12                        @ Bits 14:12 OC4M: Output compare 4 mode
.EQU  TIM2T5_CCMR2_OCxM_FROZ, 0                      @ 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
.EQU  TIM2T5_CCMR2_OCxM_SETCH1, 1                    @ 001: Set channel  to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR2_OCxM_RSTCH1, 2                    @ 010: Set channel  to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR2_OCxM_TGLCH1, 3                    @ 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
.EQU  TIM2T5_CCMR2_OCxM_FORCELOW, 4                  @ 100: Force inactive level - OC1REF is forced low
.EQU  TIM2T5_CCMR2_OCxM_FORCEHIGH, 5                 @ 101: Force active level - OC1REF is forced high
.EQU  TIM2T5_CCMR2_OCxM_PWM1, 6                      @ 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
.EQU  TIM2T5_CCMR2_OCxM_PWM2, 7                      @ 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1  else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.
.EQU  TIM2T5_CCMR2_OC4PE, 1 << 11                    @ Bit 11 OC4PE: Output compare 4 preload enable
.EQU  TIM2T5_CCMR2_OC4FE, 1 << 10                    @ Bit 10 OC4FE: Output compare 4 fast enable
.EQU  TIM2T5_CCMR2_CC4S_N, 8                         @ Bits 9:8 CC4S: Capture/Compare 4 selection
.EQU  TIM2T5_CCMR2_CC4S_CC4OUT, 0                    @ 00: CC4 channel is configured as output
.EQU  TIM2T5_CCMR2_CC4S_IC4_TO_TI4, 1 << 8           @ 01: CC4 channel is configured as input, IC4 is mapped on TI4
.EQU  TIM2T5_CCMR2_CC4S_IC4_TO_TI3, 2 << 8           @ 10: CC4 channel is configured as input, IC4 is mapped on TI3
.EQU  TIM2T5_CCMR2_CC4S_IC4_TO_TRC, 3 << 8           @ 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
.EQU  TIM2T5_CCMR2_OC3CE, 1 << 7                     @ Bit 7 OC3CE: Output compare 3 clear enable
.EQU  TIM2T5_CCMR2_OC3M_N, 4                         @ Bits 6:4 OC3M: Output compare 3 mode
.EQU  TIM2T5_CCMR2_OC3PE, 1 << 3                     @ Bit 3 OC3PE: Output compare 3 preload enable
.EQU  TIM2T5_CCMR2_OC3FE, 1 << 2                     @ Bit 2 OC3FE: Output compare 3 fast enable
.EQU  TIM2T5_CCMR2_CC3S_N, 0                         @ Bits 1:0 CC3S: Capture/Compare 3 selection
.EQU  TIM2T5_CCMR2_CC3S_CC3OUT, 0                    @ 00: CC3 channel is configured as output
.EQU  TIM2T5_CCMR2_CC3S_IC3_TO_TI3, 1                @ 01: CC3 channel is configured as input, IC3 is mapped on TI3
.EQU  TIM2T5_CCMR2_CC3S_IC3_TO_TI4, 2                @ 10: CC3 channel is configured as input, IC3 is mapped on TI4
.EQU  TIM2T5_CCMR2_CC3S_IC3_TO_TRC, 3                @ 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
.EQU  TIM2T5_CCMR2_IC4F_N, 12                        @ Bits 15:12 IC4F: Input capture 4 filter
.EQU  TIM2T5_CCMR2_ICxF_OFCKLT, 0                    @ 0000: No filter, sampling is done at fDTS
.EQU  TIM2T5_CCMR2_ICxF_CKN2, 1                      @ 0001: fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_CCMR2_ICxF_CKN4, 2                      @ 0010: fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_CCMR2_ICxF_CKN8, 3                      @ 0011: fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_CCMR2_ICxF_TS2N6, 4                     @ 0100: fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_CCMR2_ICxF_TS2N8, 5                     @ 0101: fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_CCMR2_ICxF_TS4N6, 6                     @ 0110: fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_CCMR2_ICxF_TS4N8, 7                     @ 0111: fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_CCMR2_ICxF_TS8N6, 8                     @ 1000: fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_CCMR2_ICxF_TS8N8, 9                     @ 1001: fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_CCMR2_ICxF_TS16N5, 10                   @ 1010: fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_CCMR2_ICxF_TS16N6, 11                   @ 1011: fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_CCMR2_ICxF_TS16N8, 12                   @ 1100: fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_CCMR2_ICxF_TS32N5, 13                   @ 1101: fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_CCMR2_ICxF_TS32N6, 14                   @ 1110: fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_CCMR2_ICxF_TS32N8, 15                   @ 1111: fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_CCMR2_IC4PSC_N, 10                      @ Bits 11:10 IC4PSC: Input capture 4 prescaler
.EQU  TIM2T5_CCMR2_ICxPSC_1, 0                       @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM2T5_CCMR2_ICxPSC_2, 1                       @ 01: capture is done once every 2 events
.EQU  TIM2T5_CCMR2_ICxPSC_4, 2                       @ 10: capture is done once every 4 events
.EQU  TIM2T5_CCMR2_ICxPSC_8, 3                       @ 11: capture is done once every 8 events
.EQU  TIM2T5_CCMR2_IÑ3F_N, 4                         @ Bits 7:4 IC3F[3:0]: Input capture 1 filter
.EQU  TIM2T5_CCMR2_IC3PSC_N, 2                       @ Bits 3:2 IC3PSC: Input capture 1 prescaler

@.ITEM     TIM2T5_CCER
.EQU  TIM2T5_CCER_CC4P , 1 << 13                     @ Bit 13 CC4P: Capture/Compare 4 output polarity
.EQU  TIM2T5_CCER_CC4E , 1 << 12                     @ Bit 12 CC4E: Capture/Compare 4 output enable
.EQU  TIM2T5_CCER_CC3P , 1 << 9                      @ Bit 9 CC3P: Capture/Compare 3 output polarity
.EQU  TIM2T5_CCER_CC3E , 1 << 8                      @ Bit 8 CC3E: Capture/Compare 3 output enable
.EQU  TIM2T5_CCER_CC2P , 1 << 5                      @ Bit 5 CC2P: Capture/Compare 2 output polarity
.EQU  TIM2T5_CCER_CC2E , 1 << 4                      @ Bit 4 CC2E: Capture/Compare 2 output enable
.EQU  TIM2T5_CCER_CC1P , 1 << 1                      @ Bit 1 CC1P: Capture/Compare 1 output polarity
.EQU  TIM2T5_CCER_CC1E , 1 << 0                      @ Bit 0 CC1E: Capture/Compare 1 output enable

@.ITEM     TIM2T5_DCR
.EQU  TIM2T5_DCR_DBL_N , 8                           @ Bits 12:8 DBL[4:0]: DMA burst length
.EQU  TIM2T5_DCR_DBL_MIN, 0                          @ 1 transfer
.EQU  TIM2T5_DCR_DBL_MAX, 18                         @ 18 transfers
.EQU  TIM2T5_DCR_DBA_N , 0                           @ Bits 4:0 DBA[4:0]: DMA base address
.EQU  TIM2T5_DCR_DBA_M , 0x1F                        @ DBA Mask


