@.CHARSET =CP1251 ( Cyrillic )
@GNU AS

@ +---------------------------------------------------------------+
@ |                      Определения AES                          |
@ |                          STM32L100                            |
@ +---------------------------------------------------------------+


.include "/src/inc/base.inc"

@.ITEM     AHBPERIPH_BASE
.EQU  AES_BASE      , AHBPERIPH_BASE + 0x40000
.EQU  AES           , PERIPH_BASE + AES_BASE
@.END

@.ITEM     AES AES_BASE
.EQU  AES_CR        , 0x00       @ AES control register (AES_CR)
.EQU  AES_SR        , 0x04       @ AES status register (AES_SR)
.EQU  AES_DINR      , 0x08       @ AES data input register (AES_DINR)
.EQU  AES_DOUTR     , 0X0C       @ AES data output register (AES_DOUTR)
.EQU  AES_KEYR0     , 0X010      @ AES key register 0(AES_KEYR0) (LSB: key [31:0])
.EQU  AES_KEYR1     , 0X014      @ AES key register 1 (AES_KEYR1) (Key[63:32])
.EQU  AES_KEYR2     , 0X018      @ AES key register 2 (AES_KEYR2) (Key [95:64])
.EQU  AES_KEYR3     , 0X01C      @ AES key register 3 (AES_KEYR3) (MSB: key[127:96])
.EQU  AES_IVR0      , 0X020      @ AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0])
.EQU  AES_IVR1      , 0X024      @ AES initialization vector register 1 (AES_IVR1) (IVR[63:32])
.EQU  AES_IVR2      , 0X028      @ AES initialization vector register 2 (AES_IVR2) (IVR[95:64])
.EQU  AES_IVR3      , 0X02C      @ AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96])
@.END

@.ITEM AES_CR
.EQU  AES_CR_DMAOUTEN_N, 12      @ Bit 12 DMAOUTEN: Enable DMA management of data output phase
                                 @ 0: DMA (during data output phase) disabled
.EQU  AES_CR_DMAOUTEN, 1 << 12   @ 1: DMA (during data output phase) enabled
                                 @ If the DMAOUTEN bit is set, DMA requests are generated for the output data phase in mode 1, 3 or
                                 @ 4. This bit has no effect in mode 2 (Key derivation).
.EQU  AES_CR_DMAINEN_N, 11       @ Bit 11 DMAINEN: Enable DMA management of data input phase
                                 @ 0: DMA (during data input phase) disabled
.EQU  AES_CR_DMAINEN, 1<<11      @ 1: DMA (during data input phase) enabled
                                 @ If the DMAINEN bit is set, DMA requests are generated for the data input phase in mode 1, 3 or 4.
                                 @ This bit has no action in mode 2 (Key Derivation).
.EQU  AES_CR_ERRIE_N, 10         @ Bit 10 ERRIE: Error interrupt enable
                                 @ An interrupt is generated if at least one of the both flags RDERR or WRERR is set.
                                 @ 0: Error interrupt disabled
.EQU  AES_CR_ERRIE, 1<<10        @ 1: Error interrupt enabled
.EQU  AES_CR_CCFIE_N, 9          @ Bit 9 CCFIE: CCF flag interrupt enable
                                 @ An interrupt is generated if the CCF flag is set.
                                 @ 0: CCF interrupt disabled
.EQU  AES_CR_CCFIE  , 1 << 9     @ 1: CCF interrupt enabled
.EQU  AES_CR_ERRC_N , 8          @ Bit 8 ERRC: Error clear
.EQU  AES_CR_ERRC   , 1 << 8     @ Writing 1 to this bit clears the RDERR and WRERR flags.
                                 @ This bit is always read low.
.EQU  AES_CR_CCFC_N , 7          @ Bit 7 CCFC: Computation Complete Flag Clear
.EQU  AES_CR_CCFC   , 1 << 7     @ Writing 1 to this bit clears the CCF flag.
                                 @ This bit is always read low.
.EQU  AES_CR_CHMOD_N, 5          @ Bits 6:5 CHMOD[1:0]: AES chaining mode
.EQU  AES_CR_CHMOD_EBC, 0        @ 00: Electronic codebook (EBC)
.EQU  AES_CR_CHMOD_CBC, 1<<5     @ 01: Cipher-Block Chaining (CBC)
.EQU  AES_CR_CHMOD_CTR, 2<<5     @ 10: Counter Mode (CTR)
                                 @ 11: Reserved.
                                 @ The AES chaining mode must only be changed while the AES is disabled. Writing these bits while
                                 @ the AES is enabled is forbidden to avoid unpredictable AES behavior.
.EQU  AES_CR_MODE_N , 3          @ Bits 4:3 MODE[1:0]: AES operating mode
.EQU  AES_CR_MODE_ENC, 0         @ 00: Mode 1: Encryption
.EQU  AES_CR_MODE_KEY, 1<<3      @ 01: Mode 2: Key derivation
.EQU  AES_CR_MODE_DEC, 2<<3      @ 10: Mode 3: Decryption
.EQU  AES_CR_MODE_KEYDEC, 3<<3   @ 11: Mode 4: Key derivation + decryption
                                 @ The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is
                                 @ enabled is forbidden to avoid unpredictable AES behavior.
                                 @ Mode 4 is forbidden if CTR mode is selected. It is forced to Mode 3 if the software, nevertheless,
                                 @ attempts to set mode 4 for this CTR mode configuration.
.EQU  AES_CR_DATATYPE_N, 1       @ Bits 2:1 DATATYPE[1:0]: Data type selection (for data in and data out to/from the cryptographic block)
.EQU  AES_CR_DATATYPE_32, 0      @ 00: 32-bit data. No swapping.
.EQU  AES_CR_DATATYPE_16, 1<<1   @ 01: 16-bit data or half-word. In the word, each half-word is swapped. For example, if one of the four
                                 @ 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic
                                 @ block is 0x56AB7643
.EQU  AES_CR_DATATYPE_8, 2<<1    @ 10: 8-bit data or bytes. In the word, all the bytes are swapped. For example, if one of the four 32-bit
                                 @ data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is
                                 @ 0xAB564376.
.EQU  AES_CR_DATATYPE_1, 3<<1    @ 11: Bit data. In the word all the bits are swapped. For example, if one of the four 32-bit data written in
                                 @ the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0xD56AC26E
                                 @ The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is
                                 @ enabled is forbidden to avoid unpredictable AES behavior.
.EQU  AES_CR_EN_N, 0             @ Bits 0 EN: AES enable
                                 @ 0: AES disable
.EQU  AES_CR_EN, 1               @ 1: AES enable
                                 @ The AES can be re-initialized at any moment by resetting this bit: the AES is then ready to start
                                 @ processing a new block when EN is set.
                                 @ This bit is cleared by hardware when the AES computation is finished in mode 2 (Key derivation)
@.END

@.ITEM     AES_SR
.EQU  AES_SR_WRERR_N, 2          @ Bit 2 WRERR: Write error flag
                                 @ This bit is set by hardware when an unexpected write operation to the AES_DINR register is
                                 @ detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has
                                 @ been previously set in the AES_CR register. This flag has no impact on the AES which continues
                                 @ running if even if WERR is set.
                                 @ It is cleared by software by setting the ERRC bit in the AES_CR register.
                                 @ 0: No write error detected
.EQU  AES_SR_WRERR  , 1 << 2     @ 1: Write error detected
.EQU  AES_SR_RDERR_N, 1          @ Bit 1 RDERR: Read error flag
                                 @ This bit is set by hardware when an unexpected read operation from the AES_DOUTR register is
                                 @ detected (during computation or data input phase). An interrupt is generated if the ERRIE bit has
                                 @ been previously set in the AES_CR register.This flag has no impact on the AES which continues
                                 @ running if even if RDERR is set.
                                 @ It is cleared by software by setting the ERRC bit i in the AES_CR register.
                                 @ 0: No read error detected
.EQU  AES_SR_RDERR  , 1 << 1     @ 1: Read error detected
.EQU  AES_SR_CCF_N  , 0          @ Bit 0 CCF: Computation complete flag
                                 @ This bit is set by hardware when the computation is complete. An interrupt is generated if the CCFIE
                                 @ bit has been previously set in the AES_CR register.
                                 @ It is cleared by software by setting the CCFC bit in the AES_CR register.
                                 @ 0: Computation complete
.EQU  AES_SR_CCF  , 1            @ 1: Computation is not complete
                           @ Note: This bit is significant only when DMAOUTEN = 0. It may stay high when DMA_EN = 1.
@.END

