
@.ITEM I2C1_BASE I2C1 I2C2_BASE I2C2
.EQU I2C_CR1, 0x00                      @ Control register 1
.EQU I2C_CR2, 0x04                      @ Control register 2
.EQU I2C_OAR1, 0x08                     @ Own address 1 register
.EQU I2C_OAR2, 0x0C                     @ Own address 2 register
.EQU I2C_TIMINGR, 0x10                  @ Timing register
.EQU I2C_TIMEOUTR, 0x14                  @ Timeout register
.EQU I2C_ISR, 0x18                      @ Interrupt and status register
.EQU I2C_ICR, 0x1C                      @ Interrupt clear register
.EQU I2C_PECR, 0x20                     @ PEC register
.EQU I2C_RXDR, 0x24                     @ Receive data register
.EQU I2C_TXDR, 0x28                     @ Transmit data register
@.END

@.ITEM I2C_CR1
.EQU I2C_CR1_PECEN, 1<<23               @ PEC enable
                                        @ 0: PEC calculation disabled
                                        @ 1: PEC calculation enabled
.EQU I2C_CR1_ALERTEN, 1<<22             @ SMBus alert enable
.EQU I2C_CR1_SMBDEN, 1<<21              @ SMBus Device Default address enable
.EQU I2C_CR1_SMBHEN, 1<<20              @ SMBus Host address enable
.EQU I2C_CR1_GCEN, 1<<19                @ General call enable
.EQU I2C_CR1_NOSTRETCH, 1<<17           @ Clock stretching disable
.EQU I2C_CR1_SBC, 1<<16                 @ Slave byte control
.EQU I2C_CR1_RXDMAEN, 1<<15             @ DMA reception requests enable
.EQU I2C_CR1_TXDMAEN, 1<<14             @ DMA transmission requests enable
.EQU I2C_CR1_ANFOFF, 1<<12              @ Analog noise filter OFF
.EQU I2C_CR1_DNF_N, 8                   @ DNF[3:0] Digital noise filter
.EQU I2C_CR1_DNF0, 0x00<<8              @ Digital filter disabled
.EQU I2C_CR1_DNF1, 0x01<<8              @ Digital_filter enabled and filtering capability up to 1 tI2Cclk
.EQU I2C_CR1_DNF2, 0x02<<8              @ Digital_filter enabled and filtering capability up to 2 tI2Cclk
.EQU I2C_CR1_DNF3, 0x03<<8              @ Digital_filter enabled and filtering capability up to 3 tI2Cclk
.EQU I2C_CR1_DNF4, 0x04<<8              @ Digital_filter enabled and filtering capability up to 4 tI2Cclk
.EQU I2C_CR1_DNF5, 0x05<<8              @ Digital_filter enabled and filtering capability up to 5 tI2Cclk
.EQU I2C_CR1_DNF6, 0x06<<8              @ Digital_filter enabled and filtering capability up to 6 tI2Cclk
.EQU I2C_CR1_DNF7, 0x07<<8              @ Digital_filter enabled and filtering capability up to 7 tI2Cclk
.EQU I2C_CR1_DNF8, 0x08<<8              @ Digital_filter enabled and filtering capability up to 8 tI2Cclk
.EQU I2C_CR1_DNF9, 0x09<<8              @ Digital_filter enabled and filtering capability up to 9 tI2Cclk
.EQU I2C_CR1_DNF10, 0x0A<<8              @ Digital_filter enabled and filtering capability up to 10 tI2Cclk
.EQU I2C_CR1_DNF11, 0x0B<<8              @ Digital_filter enabled and filtering capability up to 11 tI2Cclk
.EQU I2C_CR1_DNF12, 0x0C<<8              @ Digital_filter enabled and filtering capability up to 12 tI2Cclk
.EQU I2C_CR1_DNF13, 0x0D<<8              @ Digital_filter enabled and filtering capability up to 13 tI2Cclk
.EQU I2C_CR1_DNF14, 0x0E<<8              @ Digital_filter enabled and filtering capability up to 14 tI2Cclk
.EQU I2C_CR1_DNF15, 0x0F<<8              @ Digital_filter enabled and filtering capability up to 15 tI2Cclk
.EQU I2C_CR1_ERRIE, 1<<7                @ Error interrupts enable
.EQU I2C_CR1_TCIE, 1<<6                 @ Transfer Complite interrupt enable
.EQU I2C_CR1_STOPIE, 1<<5               @ STOP detection Interrupt enable
.EQU I2C_CR1_NACKIE, 1<<4               @ Not acknowledge received Interrupt enable
.EQU I2C_CR1_ADDRIE, 1<<3               @ Address match Interrupt enable (slave only)
.EQU I2C_CR1_RXIE, 1<<2                 @ RX Interrupt enable
.EQU I2C_CR1_TXIE, 1<<1                 @ TX Interrupt enable
.EQU I2C_CR1_PE, 1<<0                   @ Peripheral enable
@.END

@.ITEM I2C_CR2
.EQU I2C_CR2_PECBYTE, 1<<26             @ Packet error checking byte
.EQU I2C_CR2_AUTOEND, 1<<25             @ Automatic end mode (master mode)
.EQU I2C_CR2_RELOAD, 1<<24              @ NBYTES reload mode
.EQU I2C_CR2_NBYTES_N, 16               @ NBYTES[7:0] Numder of bytes
.EQU I2C_CR2_NACK, 1<<15                @ NACK generation (slave mode)
.EQU I2C_CR2_STOP, 1<<14                @ Stop generation (master mode)
.EQU I2C_CR2_START, 1<<13               @ Start generation
.EQU I2C_CR2_HEAD10R, 1<<12             @ 10bit address header only read direction (master receiver mode)
.EQU I2C_CR2_ADD10, 1<<11               @ 10bit addressing mode (master mode)
.EQU I2C_CR2_RD_WRN, 1<<10              @ Transfer direction (master mode)
.EQU I2C_CR2_SADDH_N, 8                  @ SADD[9:8] Slave address bit 9:8 (master mode)
.EQU I2C_CR2_SADDL_N, 1                  @ SADD[7:1] Slave address bit 7:1 (master mode)
.EQU I2C_CR2_SADD0, 1<<0                @ Slave address bit 0 (master mode)
@.END

@.ITEM I2C_OAR1
.EQU I2C_OAR1_OA1EN, 1<<15              @ Own Address 1 enable
.EQU I2C_OAR1_OA1MODE, 1<<10            @ Own Address 1 10-bit mode
.EQU I2C_OAR1_OA1H_N, 8                 @ Interface address OA[9:8]
.EQU I2C_OAR1_OA1L_N, 1                 @ Interface address OA[7:1]
.EQU I2C_OAR1_OA10, 1<<0                @ Interface address OA[0]
@.END

@.ITEM I2C_OAR2
.EQU I2C_OAR2_OA2EN, 1<<15              @ Own Address 2 enable
.EQU I2C_OAR2_OA2MSK_N, 8               @ Own Address 2 masks
.EQU I2C_OAR2_OA2MSK0, 0x00<<8          @ 000: no mask
.EQU I2C_OAR2_OA2MSK1, 0x01<<8          @ 001: OA2[1] is masked and don`t care. Only OA2[7:2] are compared
.EQU I2C_OAR2_OA2MSK2, 0x02<<8          @ 001: OA2[2:1] is masked and don`t care. Only OA2[7:3] are compared
.EQU I2C_OAR2_OA2MSK3, 0x03<<8          @ 001: OA2[3:1] is masked and don`t care. Only OA2[7:4] are compared
.EQU I2C_OAR2_OA2MSK4, 0x04<<8          @ 001: OA2[4:1] is masked and don`t care. Only OA2[7:5] are compared
.EQU I2C_OAR2_OA2MSK5, 0x05<<8          @ 001: OA2[5:1] is masked and don`t care. Only OA2[7:6] are compared
.EQU I2C_OAR2_OA2MSK6, 0x06<<8          @ 001: OA2[6:1] is masked and don`t care. Only OA2[7] are compared
.EQU I2C_OAR2_OA2MSK7, 0x07<<8          @ 001: OA2[7:1] is masked and don`t care. No comparison is done, and all 7-b received
.EQU I2C_OAR2_OA2_N, 1                  @ OA2[7:1] interface address
@.END

@.ITEM I2C_TIMINGR
.EQU I2C_TIMINGR_PRESC_N, 28            @ PRESC[3:0] Timing prescaler
.EQU I2C_TIMINGR_SCLDEL_N, 20           @ SCLDEL[3:0] Data setup time
.EQU I2C_TIMINGR_SDADEL_N, 16           @ SDADEL[3:0] Data hold time
.EQU I2C_TIMINGR_SCLH_N, 8              @ SCLH[7:0] SCL high period (master mode)
.EQU I2C_TIMINGR_SCLL_N, 0              @ SCLL[7:0] SCL low period (master mode)
@.END

@.ITEM I2C_TIMEOUTR
.EQU I2C_TIMEOUTR_TEXTEN, 1<<31         @ Extended clock timeout enable
.EQU I2C_TIMEOUTR_TIMEOUTB_N, 16        @ TIMEOUTB[11:0] Bus timeout B
.EQU I2C_TIMEOUTR_TIMEOUTEN, 1<<15      @ Clock timeout enable
.EQU I2C_TIMEOUTR_TIDLE, 1<<12          @ Idle clock timeout detection
.EQU I2C_TIMEOUTR_TIMEOUTA_N, 0         @ TIMEOUTA[11:0] Bus timeout A
@.END

@.ITEM I2C_ISR
.EQU I2C_ISR_ADDCODE_N, 17              @ ADDCODE[6:0] Address match code (Slave Mide)
.EQU I2C_ISR_DIR, 1<<16                 @ Tranfer direction (Slave mode)
.EQU I2C_ISR_BUSY, 1<<15                @ Bus Busy
.EQU I2C_ISR_ALERT, 1<<13               @ SMBus alert
.EQU I2C_ISR_TIMEOUT, 1<<12             @ Timeout or tlow detection flag
.EQU I2C_ISR_PECERR, 1<<11              @ PEC Error reception flag
.EQU I2C_ISR_OVR, 1<<10                 @ Overrun/Underrun flag (slave mode)
.EQU I2C_ISR_ARLO, 1<<9                 @ Arbitration lost flag
.EQU I2C_ISR_BERR, 1<<8                 @ Bus error flag
.EQU I2C_ISR_TCR, 1<<7                  @ Transfer Complete Reload flag
.EQU I2C_ISR_TC, 1<<6                   @ Transfer Complete flag (master mode)
.EQU I2C_ISR_STOPF, 1<<5                @ Stop detection flag
.EQU I2C_ISR_NACKF, 1<<4                @ Not Acknowledge received flag
.EQU I2C_ISR_ADDR, 1<<3                 @ Address matched (slave mode)
.EQU I2C_ISR_RXNE, 1<<2                 @ Receive data register not empty (receivers)
.EQU I2C_ISR_TXIS, 1<<1                 @ Transmit interrupt status (transmitters)
.EQU I2C_ISR_TXE,   1<<0                @ Transmit data register empty (transmitters)
@.END

@.ITEM I2C_ICR
.EQU I2C_ICR_ALERTCF, 1<<13             @ Alert flag clear
.EQU I2C_ICR_TIMOUTCF, 1<<12            @ Timeout detection flag clear
.EQU I2C_ICR_PECCF, 1<<11               @ PEC Error flag clear
.EQU I2C_ICR_OVRCF, 1<<10               @ Overrun/Underrun flag clear
.EQU I2C_ICR_ARLOCF, 1<<9               @ Arbitration Lost flag clear
.EQU I2C_ICR_BERRCF, 1<<8               @ Bus error flag clear
.EQU I2C_ICR_STOPCF, 1<<5               @ Stop detection flag clear
.EQU I2C_ICR_NACKCF, 1<<4               @ Not Acknowledge flag clear
.EQU I2C_ICR_ADDRCF, 1<<3               @ Address matched flag clear
@.END

@.ITEM I2C_PECR
.EQU I2C_PECR_PEC_M, 0x000000FF         @ Packet error checking register
@.END

@.ITEM I2C_RXDR
.EQU I2C_RXDR_RXDATA_M, 0x000000FF      @ 8bit receive data
@.END

@.ITEM I2C_TXDR
.EQU I2C_TXDR_TXDATA_M, 0x000000FF      @ 8bit transmit data
@.END





