@.CharSet CP1251
@GNU AS
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Константы SPI / I2C                          |
@ |                         STM32F42x                                |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.item APB2PERIPH_BASE
.equ SPI                           , (APB2PERIPH_BASE + 0x3000)

@.item SPI
.equ SPI1_BASE                     , (APB2PERIPH_BASE + 0x3000)
.equ SPI2_BASE                     , (APB1PERIPH_BASE + 0x3800)
.equ SPI3_BASE                     , (APB1PERIPH_BASE + 0x3C00)
.equ SPI4_BASE                     , (APB2PERIPH_BASE + 0x3400)
.equ SPI5_BASE                     , (APB2PERIPH_BASE + 0x5000)
.equ SPI6_BASE                     , (APB2PERIPH_BASE + 0x5400)
.equ SPI1                          , PERIPH_BASE+SPI1_BASE
.equ SPI2                          , PERIPH_BASE+SPI2_BASE
.equ SPI3                          , PERIPH_BASE+SPI3_BASE
.equ SPI4                          , PERIPH_BASE+SPI4_BASE
.equ SPI5                          , PERIPH_BASE+SPI5_BASE
.equ SPI6                          , PERIPH_BASE+SPI6_BASE
@.end

@.item     SPI1_BASE SPI2_BASE SPI3_BASE SPI4_BASE SPI5_BASE SPI6_BASE
.equ  SPI_CR1            , 0x00       @ SPI control register 1 (SPI_CR1)
.equ  SPI_CR2            , 0x04       @ SPI control register 2 (SPI_CR2)
.equ  SPI_SR             , 0x08       @ SPI status register (SPI_SR)
.equ  SPI_DR             , 0x0C       @ SPI data register (SPI_DR)
.equ  SPI_CRCPR          , 0x10       @ SPI CRC polynomial register (SPI_CRCPR)
.equ  SPI_SPI_RXCRCR     , 0x14       @ SPI RX CRC register (SPI_RXCRCR)
.equ  SPI_SPI_TXCRCR     , 0x18       @ SPI TX CRC register (SPI_TXCRCR)
.equ  SPI_I2SCFGR        , 0x1C       @ SPI_I2S configuration register
.equ  SPI_I2SPR          , 0x20       @ SPI_I2S prescaler register
@.end

@.item     SPI_CR1
.equ  SPI_CR1_CPHA       , 0x0001
.equ  SPI_CR1_CPHA_N     , 0          @ Bit 0 CPHA: Clock phase
.equ  SPI_CR1_CPOL       , 0x0002
.equ  SPI_CR1_CPOL_N     , 1          @ Bit1 CPOL: Clock polarity
.equ  SPI_CR1_MSTR       , 0x0004
.equ  SPI_CR1_MSTR_N     , 2          @ Bit 2 MSTR: Master selection
.equ  SPI_CR1_BR_N       , 3          @  Bits 5:3 BR[2:0]: Baud rate control
.equ  SPI_CR1_BR_DIV_2   , 0x00 << 3
.equ  SPI_CR1_BR_DIV_4   , 0x01 << 3
.equ  SPI_CR1_BR_DIV_8   , 0x02 << 3
.equ  SPI_CR1_BR_DIV_16  , 0x03 << 3
.equ  SPI_CR1_BR_DIV_32  , 0x04 << 3
.equ  SPI_CR1_BR_DIV_64  , 0x05 << 3
.equ  SPI_CR1_BR_DIV_128 , 0x06 << 3
.equ  SPI_CR1_BR_DIV_256 , 0x07 << 3
.equ  SPI_CR1_SPE_N      , 6          @ Bit 6 SPE: SPI enable
.equ  SPI_CR1_SPE        , 0x0040
.equ  SPI_CR1_LSBFIRST_N , 7          @ Bit 7 LSBFIRST: Frame format
.equ  SPI_CR1_LSBFIRST_LSB, 0x0080
.equ  SPI_CR1_SSI_N      , 8          @ Bit 8 SSI: Internal slave select
.equ  SPI_CR1_SSI        , 0x0100
.equ  SPI_CR1_SSM_N      , 9          @ Bit 9 SSM: Software slave management
.equ  SPI_CR1_SSM        , 0x0200
.equ  SPI_CR1_RXONLY_N   , 10         @ Bit 10 RXONLY
.equ  SPI_CR1_RXONLY_OUT_DISABLED, 0x0400
.equ  SPI_CR1_DFF_N      , 11         @ Bit 11 DFF: Data frame format
.equ  SPI_CR1_DFF_16BIT  , 0x0800
.equ  SPI_CR1_CRCNEXT_N  , 12         @  Bit 12 CRCNEXT: CRC transfer next
.equ  SPI_CR1_CRCNEXT_NEXT, 0x1000
.equ  SPI_CR1_CRCEN_N    , 13         @ Bit 13 CRCEN: Hardware CRC calculation enable
.equ  SPI_CR1_CRCEN_ENABLED, 0x2000
.equ  SPI_CR1_BIDIOE_N   , 14         @ Bit 14 BIDIOE: Output enable in bidirectional mode
.equ  SPI_CR1_BIDIOE     , 0x4000
.equ  SPI_CR1_BIDIMODE_N , 15         @ Bit 15 BIDIMODE: Bidirectional data mode enable
.equ  SPI_CR1_BIDIMODE   , 0x8000
@.end

@.item SPI_CR2
.equ  SPI_CR2_RXDMAEN_N              , 0     @ Bit 0 RXDMAEN: Rx buffer DMA enable
.equ  SPI_CR2_TXDMAEN_N              , 1     @ Bit 1 TXDMAEN: Tx buffer DMA enable
.equ  SPI_CR2_SSOE_N                 ,2      @ Bit 2 SSOE: SS output enable
.equ  SPI_CR2_FRF_N                  ,4      @ Bit 4 FRF: Frame format
.equ  SPI_CR2_ERRIE_N                , 5     @ Bit 5 ERRIE: Error interrupt enabled
.equ  SPI_CR2_RXNEIE_N               , 6     @ Bit 6 RXNEIE: RX buffer not empty interrupt enable
.equ  SPI_CR2_TXEIE_N                , 7     @ Bit 7 TXEIE: Tx buffer empty interrupt enable
@.end

@.item     SPI_SR
.equ  SPI_SR_RXNE_N      , 0          @ Bit 0 RXNE: Receive buffer not empty
.equ  SPI_SR_TXE_N       , 1          @ Bit 1 TXE: Transmit buffer empty
.equ  SPI_SR_CHSIDE_N    , 2          @ Bit 2 CHSIDE: Channel side
.equ  SPI_SR_UDR_N       , 3          @ Bit 3 UDR: Underrun flag
.equ  SPI_SR_CRCERR_N    , 4          @ Bit 4 CRCERR: CRC error flag
.equ  SPI_SR_MODF_N      , 5          @ Bit 5 MODF: Mode fault
.equ  SPI_SR_OVR_N       , 6          @ Bit 6 OVR: Overrun flag
.equ  SPI_BSY_N          , 7          @ Bit 7 BSY: Busy flag
.equ  SPI_FRE_N          , 8          @ Bit 8 FRE: Frame format error
@.end

@.item     SPI_DR
.equ  SPI_DR_N           , 0          @ Bit 0,     Bits 15:0
.equ  SPI_DR_DR_M          , 0xFFFF     @ Bits 15:0 DR[15:0]: Data register
@.end

@.item     SPI_CRCPR
.equ  SPI_CRCPR_CRCPOLY_N, 0          @ Bits 15:0 CRCPOLY[15:0]: CRC polynomial register
.equ  SPI_CRCPR_CRCPOLY_M, 0xFFFF     @CRC polynomial register
@.end
@.item     SPI_RXCRCR
.equ  SPI_RXCRCR_RXCRC_N , 0          @ Bits 15:0 RXCRC[15:0]: Rx CRC register
.equ  SPI_RXCRCR_RXCRC_M , 0xFFFF     @Rx CRC Register
@.end

@.item     SPI_TXCRCR
.equ  SPI_TXCRCR_TXCRC_N , 0          @ Bits 15:0 TXCRC[15:0]: Tx CRC register
.equ  SPI_TXCRCR_TXCRC_M , 0xFFFF     @Tx CRC Register
@.end

@.item     SPI_I2SCFGR
.equ  SPI_I2SCFGR_I2SMOD_N, 11        @ Bit 11 I2SMOD: I2S mode selection
.equ  SPI_I2SCFGR_I2SE_N , 10         @ Bit 10 I2SE: I2S Enable
.equ  SPI_I2SCFGR_I2SCFG_N, 8         @ Bits 9:8 I2SCFG: I2S configuration mode
.equ  SPI_I2SCFGR_PCMSYNC_N, 7        @ Bit 7 PCMSYNC: PCM frame synchronization
.equ  SPI_I2SCFGR_I2SSTD_N, 4         @ Bits 5:4 I2SSTD: I2S standard selection
.equ  SPI_I2SCFGR_CKPOL_N, 3          @ Bit 3 CKPOL: Steady state clock polarity
.equ  SPI_I2SCFGR_DATLEN_N, 1         @ Bits 2:1 DATLEN: Data length to be transferred
.equ  SPI_I2SCFGR_CHLEN_N, 0          @ Bit 0 CHLEN: Channel length (number of bits per audio channel)
@.end

@.item     SPI_I2SPR
.equ  SPI_I2SPR_I2SDIV_N , 0          @ Bits 7:0 I2SDIV: I2S Linear prescaler
.equ  SPI_I2SPR_ODD_N    , 8          @ Bit 8 ODD: Odd factor for the prescaler
.equ  SPI_I2SPR_MCKOE_N  , 9          @ Bit 9 MCKOE: Master clock output enable
@.end


@ маппинг SPI 1
@+------+--------+-------+-------+--------+--------+
@|          AF5  |  NSS  |  SCK  |  MISO  |  MOSI  |
@+---------------+-------+-------+--------+--------+
@| GPIOA         |  PA4  |  PA5  |  PA6   |  PA7   |
@|               |  PA15 |       |        |        |
@+---------------+-------+-------+--------+--------+
@| GPIOB         |       |  PB3  |  PB4   |  PB5   |
@+---------------+-------+-------+--------+--------+

@ маппинг SPI 2
@+------+--------+-------+-------+--------+--------+
@|          AF5  |  NSS  |  SCK  |  MISO  |  MOSI  |
@+---------------+-------+-------+--------+--------+
@| GPIOB         |  PB9  |  PB10 |  PB14  |  PB15  |
@|               |  PB12 |  PB13 |        |        |
@+---------------+-------+-------+--------+--------+
@| GPIOC         |       |       |  PC2   |  PC3   |
@+---------------+-------+-------+--------+--------+
@| GPIOI         |  PI0  |  PI1  |  PI2   |  PI3   |
@+---------------+-------+-------+--------+--------+


