@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     มเ็๎โ๛ๅ ๊๎ํ๑๒เํ๒๛ TIM2 - TIM5                |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  TIM2_BASE          , APB1PERIPH_BASE + 0
.EQU  TIM3_BASE          , APB1PERIPH_BASE + 0x400
.EQU  TIM4_BASE          , APB1PERIPH_BASE + 0x800
.EQU  TIM5_BASE          , APB1PERIPH_BASE + 0xC00
.EQU  TIM2               , PERIPH_BASE + APB1PERIPH_BASE + 0
.EQU  TIM3               , PERIPH_BASE + APB1PERIPH_BASE + 0x400
.EQU  TIM4               , PERIPH_BASE + APB1PERIPH_BASE + 0x800
.EQU  TIM5               , PERIPH_BASE + APB1PERIPH_BASE + 0xC00
@.END

@.ITEM     TIM2_BASE TIM3_BASE TIM4_BASE TIM5_BASE TIM2 TIM3 TIM4 TIM5
.EQU  TIM2T5_CR1         , 0x00     @ TIMx control register 1 (TIMx_CR1)
.EQU  TIM2T5_CR2         , 0x04     @ TIMx control register 2 (TIMx_CR2)
.EQU  TIM2T5_SMCR        , 0x08     @ TIMx slave mode control register (TIMx_SMCR)
.EQU  TIM2T5_DIER        , 0x0C     @ TIMx DMA/Interrupt enable register (TIMx_DIER)
.EQU  TIM2T5_SR          , 0x10     @ TIMx status register (TIMx_SR)
.EQU  TIM2T5_EGR         , 0x14     @ TIMx event generation register (TIMx_EGR)
.EQU  TIM2T5_CCMR1       , 0x18     @ TIMx capture/compare mode register 1 (TIMx_CCMR1)
.EQU  TIM2T5_CCMR2       , 0x1C     @ TIMx capture/compare mode register 2 (TIMx_CCMR2)
.EQU  TIM2T5_CCER        , 0x20     @ TIMx capture/compare enable register (TIMx_CCER)
.EQU  TIM2T5_CNT         , 0x24     @ TIMx counter ( TIMx_CNT)
.EQU  TIM2T5_PSC         , 0x28     @ TIMx prescaler ( TIMx_PSC)
.EQU  TIM2T5_ARR         , 0x2C     @ TIMx auto-reload register (TIMx_ARR)
.EQU  TIM2T5_CCR1        , 0x34     @ TIMx capture/compare register 1 (TIMx_CCR1)
.EQU  TIM2T5_CCR2        , 0x38     @ TIMx capture/compare register 2 (TIMx_CCR2)
.EQU  TIM2T5_CCR3        , 0x3C     @ TIMx capture/compare register 3 (TIMx_CCR3)
.EQU  TIM2T5_CCR4        , 0x40     @ TIMx capture/compare register 4 (TIMx_CCR4)
.EQU  TIM2T5_DCR         , 0x48     @ TIMx DMA control register (TIMx_DCR)
.EQU  TIM2T5_DMAR        , 0x4C     @ TIMx DMA address for full transfer (TIMx_DMAR)
.EQU  TIM2_OR            , 0x50     @ TIM2 option register (TIM2_OR)
.EQU  TIM5_OR            , 0x50     @ TIM5 option register (TIM5_OR)
@.END

@.ITEM     TIM2T5_CR1
.EQU  TIM2T5_CR1_CKD_N   , 8          @ Bits 9:8 CKD: Clock division
                                      @ This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
                                      @ sampling clock used by the digital filters (ETR, TIx),
.EQU  TIM2T5_CR1_CKD_1   , 0          @ 00: tDTS = tCK_INT
.EQU  TIM2T5_CR1_CKD_2   , 1 << 8     @ 01: tDTS = 2 x tCK_INT
.EQU  TIM2T5_CR1_CKD_4   , 2 << 8     @ 10: tDTS = 4 x tCK_INT
.EQU  TIM2T5_CR1_APRE    , 1 << 7     @ Bit 7 ARPE: Auto-reload preload enable
                                      @ 0: TIMx_ARR register is not buffered
                                      @ 1: TIMx_ARR register is buffered
.EQU  TIM2T5_CR1_CMS_N   , 5          @ Bits 6:5 CMS: Center-aligned mode selection
.EQU  TIM2T5_CR1_CMS_EDGE, 0          @ 00: Edge-aligned mode. The counter counts up or down depending on the direction bit
                                      @ (DIR)
.EQU  TIM2T5_CR1_CMS_CENT1, 1 << 5    @ 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
                                      @ interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
                                      @ only when the counter is counting down.
.EQU  TIM2T5_CR1_CMS_CENT2, 2 << 5    @ 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
                                      @ interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
                                      @ only when the counter is counting up.
.EQU  TIM2T5_CR1_CMS_CENT3, 3 << 5    @ 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
                                      @ interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
                                      @ both when the counter is counting up or down.
                                      @ Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
                                      @ the counter is enabled (CEN=1)
.EQU  TIM2T5_CR1_DIR     , 1 << 4     @ Bit 4 DIR: Direction
                                      @ 0: Counter used as upcounter
                                      @ 1: Counter used as downcounter
                                      @ Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
                                      @ mode.
.EQU  TIM2T5_CR1_OPM     , 1 << 3     @ Bit 3 OPM: One-pulse mode
                                      @ 0: Counter is not stopped at update event
                                      @ 1: Counter stops counting at the next update event (clearing the bit CEN)
.EQU  TIM2T5_CR1_URS     , 1 << 2     @ Bit 2 URS: Update request source
                                      @ This bit is set and cleared by software to select the UEV event sources.
                                      @ 0: Any of the following events generate an update interrupt or DMA request if enabled.
                                      @ These events can be:
                                      @  Counter overflow/underflow
                                      @  Setting the UG bit
                                      @  Update generation through the slave mode controller
                                      @ 1: Only counter overflow/underflow generates an update interrupt or DMA request if
                                      @ enabled.
.EQU  TIM2T5_CR1_UDIS    , 1 << 1     @ Bit 1 UDIS: Update disable
                                      @ This bit is set and cleared by software to enable/disable UEV event generation.
                                      @ 0: UEV enabled. The Update (UEV) event is generated by one of the following events:
                                      @  Counter overflow/underflow
                                      @  Setting the UG bit
                                      @  Update generation through the slave mode controller
                                      @ Buffered registers are then loaded with their preload values.
                                      @ 1: UEV disabled. The Update event is not generated, shadow registers keep their value
                                      @ (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
                                      @ set or if a hardware reset is received from the slave mode controller.
.EQU  TIM2T5_CR1_CEN     , 1          @ Bit 0 CEN: Counter enable
                                      @ 0: Counter disabled
                                      @ 1: Counter enabled
                                @ Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
                                      @ previously set by software. However trigger mode can set the CEN bit automatically by
                                      @ hardware.
                                      @ CEN is cleared automatically in one-pulse mode, when an update event occurs.
@.END

@.ITEM     TIM2T5_CR2
.EQU  TIM2T5_CR2_TI1S    , 1 << 7     @ Bit 7 TI1S: TI1 selection
                                      @ 0: The TIMx_CH1 pin is connected to TI1 input
                                      @ 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
.EQU  TIM2T5_CR2_MMS_N   , 1 << 4     @ Bits 6:4 MMS[2:0]: Master mode selection
                                      @ These bits allow to select the information to be sent in master mode to slave timers for
                                      @ synchronization (TRGO). The combination is as follows:
.EQU  TIM2T5_CR2_MMS_RST , 0          @ 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
                                      @ reset is generated by the trigger input (slave mode controller configured in reset mode) then
                                      @ the signal on TRGO is delayed compared to the actual reset.
.EQU  TIM2T5_CR2_MMS_ENB , 1 << 4     @ 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
                                      @ useful to start several timers at the same time or to control a window in which a slave timer is
                                      @ enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
                                      @ and the trigger input when configured in gated mode.
                                      @ When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
                                      @ except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
                                      @ register)
.EQU  TIM2T5_CR2_MMS_UPD , 2 << 4     @ 010: Update - The update event is selected as trigger output (TRGO). For instance a master
                                      @ timer can then be used as a prescaler for a slave timer.
.EQU  TIM2T5_CR2_MMS_COMP, 3 << 4     @ 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
                                      @ set (even if it was already high), as soon as a capture or a compare match occurred.
                                      @ (TRGO)
.EQU  TIM2T5_CR2_MMS_OC1REF, 4 << 4   @ 100: Compare - OC1REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_MMS_OC2REF, 5 << 4   @ 101: Compare - OC2REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_MMS_OC3REF, 6 << 4   @ 110: Compare - OC3REF signal is used as trigger output (TRGO)
.EQU  TIM2T5_CR2_MMS_OC4REF, 7 << 4   @ 111: Compare - OC4REF signal is used as trigger output (TRGO)
                                      @ Note: The clock of the slave timer and ADC must be enabled prior to receiving events from
                                      @ the master timer, and must not be changed on-the-fly while triggers are received from
                                      @ the master timer.
.EQU  TIM2T5_CR2_CCDS    , 1 << 3     @ Bit 3 CCDS: Capture/compare DMA selection
                                      @ 0: CCx DMA request sent when CCx event occurs
                                      @ 1: CCx DMA requests sent when update event occurs
@.END

@.ITEM     TIM2T5_SMCR
.EQU  TIM2T5_SMCR_ETR    , 1 << 15    @ Bit 15 ETP: External trigger polarity
                                      @ This bit selects whether ETR or ETR is used for trigger operations
                                      @ 0: ETR is noninverted, active at high level or rising edge
                                      @ 1: ETR is inverted, active at low level or falling edge
.EQU  TIM2T5_SMCR_ECE    , 1 << 14    @ Bit 14 ECE: External clock enable
                                      @ This bit enables External clock mode 2.
                                      @ 0: External clock mode 2 disabled
                                      @ 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
                                      @ signal.
                                      @ 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
                                      @ connected to ETRF (SMS=111 and TS=111).
                                      @ 2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
                                      @ reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
                                      @ ETRF in this case (TS bits must not be 111).
                                      @ 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
                                      @ external clock input is ETRF.
.EQU  TIM2T5_SMCR_ETPS_N , 12         @ Bits 13:12 ETPS: External trigger prescaler
                                      @ External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
                                      @ prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
                                      @ clocks.
.EQU  TIM2T5_SMCR_ETPS_OFF, 0         @ 00: Prescaler OFF
.EQU  TIM2T5_SMCR_ETPS_DIV2, 1 << 12  @ 01: ETRP frequency divided by 2
.EQU  TIM2T5_SMCR_ETPS_DIV4, 2 << 12  @ 10: ETRP frequency divided by 4
.EQU  TIM2T5_SMCR_ETPS_DIV8, 3 << 12  @ 11: ETRP frequency divided by 8
.EQU  TIM2T5_SMCR_ETF_N  , 8          @ Bits 11:8 ETF[3:0]: External trigger filter
                                      @ This bit-field then defines the frequency used to sample ETRP signal and the length of the
                                      @ digital filter applied to ETRP. The digital filter is made of an event counter in which N
                                      @ consecutive events are needed to validate a transition on the output:
.EQU  TIM2T5_SMCR_ETF_NOF, 0          @ 0000: No filter, sampling is done at fDT
.EQU  TIM2T5_SMCR_ETF_N2 , 1 << 8      @ 0001:   fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_SMCR_ETF_N4 , 2 << 8      @ 0010:   fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_SMCR_ETF_N8 , 3 << 8      @ 0011:   fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_SMCR_ETF_2N6, 4 << 8      @ 0100:   fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_SMCR_ETF_2N8, 5 << 8      @ 0101:   fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_SMCR_ETF_4N6, 6 << 8      @ 0110:   fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_SMCR_ETF_4N8, 7 << 8      @ 0111:   fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_SMCR_ETF_8N6, 8 << 8      @ 1000:   fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_SMCR_ETF_8N8, 9 << 8      @ 1001:   fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_SMCR_ETF_16N5, 10 << 8    @ 1010:   fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_SMCR_ETF_16N6, 11 << 8    @ 1011:   fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_SMCR_ETF_16N8, 12 << 8    @ 1100:   fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_SMCR_ETF_32N5, 13 << 8    @ 1101:   fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_SMCR_ETF_32N6, 14 << 8    @ 1110:   fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_SMCR_ETF_32N8, 15 << 8    @ 1111:   fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_SMCR_MSM    , 1 << 7      @ Bit 7 MSM: Master/Slave mode
                                       @ 0: No action
                                       @ 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
                                       @ synchronization between the current timer and its slaves (through TRGO). It is useful if we
                                       @ want to synchronize several timers on a single external event.
.EQU  TIM2T5_SMCR_TS_N   , 4           @ Bits 6:4 TS: Trigger selection
                                       @ This bit-field selects the trigger input to be used to synchronize the counter.
.EQU  TIM2T5_SMCR_TS_ITR0, 0           @ 000: Internal Trigger 0 (ITR0).
.EQU  TIM2T5_SMCR_TS_ITR1, 1 << 4      @ 001: Internal Trigger 1 (ITR1).
.EQU  TIM2T5_SMCR_TS_ITR2, 2 << 4      @ 010: Internal Trigger 2 (ITR2).
.EQU  TIM2T5_SMCR_TS_ITR3, 3 << 4      @ 011: Internal Trigger 3 (ITR3).
.EQU  TIM2T5_SMCR_TS_TI1F_ED, 4 << 4   @ 100: TI1 Edge Detector (TI1F_ED)
.EQU  TIM2T5_SMCR_TS_TI1FP1, 5 << 4    @ 101: Filtered Timer Input 1 (TI1FP1)
.EQU  TIM2T5_SMCR_TS_TI2FP2, 6 << 4    @ 110: Filtered Timer Input 2 (TI2FP2)
.EQU  TIM2T5_SMCR_TS_ETRF, 7 << 4      @ 111: External Trigger input (ETRF)
                                       @ See Table 54: TIMx internal trigger connection on page 358 for more details on ITRx
                                       @ meaning for each Timer.
                                       @ Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
                                       @ avoid wrong edge detections at the transition.
@
@         Table 54. TIMx internal trigger connection (stm32f401\stm32f411)
@ Slave TIM     ITR0        ITR1        ITR2        ITR3
@            (TS = 000)  (TS = 001)  (TS = 010)  (TS = 011)
@  TIM2      TIM1_TRGO       -       TIM3_TRGO   TIM4_TRGO
@  TIM3      TIM1_TRGO   TIM2_TRGO   TIM5_TRGO   TIM4_TRGO
@  TIM4      TIM1_TRGO   TIM2_TRGO   TIM3_TRGO       -
@  TIM5      TIM2_TRGO   TIM3_TRGO   TIM4_TRGO       -
@
.EQU  TIM2T5_SMCR_SMS_N     , 0        @ Bits 2:0 SMS: Slave mode selection
                                       @ When external signals are selected the active edge of the trigger signal (TRGI) is linked to
                                       @ the polarity selected on the external input (see Input Control register and Control Register
                                       @ description.
.EQU  TIM2T5_SMCR_SMS_SMD   , 0        @ 000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
                                       @ clock.
.EQU  TIM2T5_SMCR_SMS_ENCM1 , 1        @ 001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2
                                       @ level.
.EQU  TIM2T5_SMCR_SMS_ENCM2 , 2        @ 010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1
                                       @ level.
.EQU  TIM2T5_SMCR_SMS_ENCM3 , 3        @ 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
                                       @ depending on the level of the other input.
.EQU  TIM2T5_SMCR_SMS_RSTM  , 4        @ 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
                                       @ and generates an update of the registers.
.EQU  TIM2T5_SMCR_SMS_GTDM  , 5        @ 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
                                       @ counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
                                       @ the counter are controlled.
.EQU  TIM2T5_SMCR_SMS_TRGM, 6          @ 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
                                       @ reset). Only the start of the counter is controlled.
.EQU  TIM2T5_SMCR_SMS_EXTCLK, 7        @ 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
                                 @ Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
                                       @ Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
                                       @ checks the level of the trigger signal.
                                       @ The clock of the slave timer must be enabled prior to receiving events from the master
                                       @ timer, and must not be changed on-the-fly while triggers are received from the master
                                       @ timer.
@.END

@         Table 98. TIMx internal trigger connection
@ Slave TIM     ITR0        ITR1        ITR2        ITR3
@            (TS = 000)  (TS = 001)  (TS = 010)  (TS = 011)
@  TIM2      TIM1_TRGO   TIM8_TRGO   TIM3_TRGO   TIM4_TRGO
@  TIM3      TIM1_TRGO   TIM2_TRGO   TIM5_TRGO   TIM4_TRGO
@  TIM4      TIM1_TRGO   TIM2_TRGO   TIM3_TRGO   TIM8_TRGO
@  TIM5      TIM2_TRGO   TIM3_TRGO   TIM4_TRGO   TIM8_TRGO

@.ITEM     TIM2T5_DIER
.EQU  TIM2T5_DIER_TDE       , 1 << 14  @ Bit 14 TDE: Trigger DMA request enable
                                       @ 0: Trigger DMA request disabled.
                                       @ 1: Trigger DMA request enabled.
.EQU  TIM2T5_DIER_CC4DE     , 1 << 12  @ Bit 12 CC4DE: Capture/Compare 4 DMA request enable
                                       @ 0: CC4 DMA request disabled.
                                       @ 1: CC4 DMA request enabled.
.EQU  TIM2T5_DIER_CC3DE     , 1 << 11  @ Bit 11 CC3DE: Capture/Compare 3 DMA request enable
                                       @ 0: CC3 DMA request disabled.
                                       @ 1: CC3 DMA request enabled.
.EQU  TIM2T5_DIER_CC2DE     , 1 << 10  @ Bit 10 CC2DE: Capture/Compare 2 DMA request enable
                                       @ 0: CC2 DMA request disabled.
                                       @ 1: CC2 DMA request enabled.
.EQU  TIM2T5_DIER_CC1DE     , 1 << 9   @ Bit 9 CC1DE: Capture/Compare 1 DMA request enable
                                       @ 0: CC1 DMA request disabled.
                                       @ 1: CC1 DMA request enabled.
.EQU  TIM2T5_DIER_UDE       , 1 << 8   @ Bit 8 UDE: Update DMA request enable
                                       @ 0: Update DMA request disabled.
                                       @ 1: Update DMA request enabled.
.EQU  TIM2T5_DIER_TIE       , 1 << 6   @ Bit 6 TIE: Trigger interrupt enable
                                       @ 0: Trigger interrupt disabled.
                                       @ 1: Trigger interrupt enabled.
.EQU  TIM2T5_DIER_CC4IE     , 1 << 4   @ Bit 4 CC4IE: Capture/Compare 4 interrupt enable
                                       @ 0: CC4 interrupt disabled.
                                       @ 1: CC4 interrupt enabled.
.EQU  TIM2T5_DIER_CC3IE     , 1 << 3   @ Bit 3 CC3IE: Capture/Compare 3 interrupt enable
                                       @ 0: CC3 interrupt disabled.
                                       @ 1: CC3 interrupt enabled.
.EQU  TIM2T5_DIER_CC2IE     , 1 << 2   @ Bit 2 CC2IE: Capture/Compare 2 interrupt enable
                                       @ 0: CC2 interrupt disabled
                                       @ 1: CC2 interrupt enabled
.EQU  TIM2T5_DIER_CC1IE     , 1 << 1   @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
                                       @ 0: CC1 interrupt disabled
                                       @ 1: CC1 interrupt enabled
.EQU  TIM2T5_DIER_UIE       , 1        @ Bit 0 UIE: Update interrupt enable
                                       @ 0: Update interrupt disabled
                                       @ 1: Update interrupt enabled
@.END

@.ITEM     TIM2T5_SR
.EQU  TIM2T5_SR_CC4OF, 1 << 12         @ Bit 12 CC4OF: Capture/Compare 4 overcapture flag
                                       @ refer to CC1OF description
.EQU  TIM2T5_SR_CC3OF, 1 << 11         @ Bit 11 CC3OF: Capture/Compare 3 overcapture flag
                                       @ refer to CC1OF description
.EQU  TIM2T5_SR_CC2OF, 1 << 10         @ Bit 10 CC2OF: Capture/compare 2 overcapture flag
                                       @ refer to CC1OF description
.EQU  TIM2T5_SR_CC1OF, 1 << 9          @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
                                       @ This flag is set by hardware only when the corresponding channel is configured in input
                                       @ capture mode. It is cleared by software by writing it to 0.
                                       @ 0: No overcapture has been detected
                                       @ 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
                                       @ already set
.EQU  TIM2T5_SR_TIF , 1 << 6           @ Bit 6 TIF: Trigger interrupt flag
                                       @ This flag is set by hardware on trigger event (active edge detected on TRGI input when the
                                       @ slave mode controller is enabled in all modes but gated mode. It is set when the counter
                                       @ starts or stops when gated mode is selected. It is cleared by software.
                                       @ 0: No trigger event occurred
                                       @ 1: Trigger interrupt pending
.EQU  TIM2T5_SR_CC4IF, 1 << 4          @ Bit 4 CC4IF: Capture/Compare 4 interrupt flag
                                       @ refer to CC1IF description
.EQU  TIM2T5_SR_CC3IF, 1 << 3          @ Bit 3 CC3IF: Capture/Compare 3 interrupt flag
                                       @ refer to CC1IF description
.EQU  TIM2T5_SR_CC2IF, 1 << 2          @ Bit 2 CC2IF: Capture/Compare 2 interrupt flag
                                       @ refer to CC1IF description
.EQU  TIM2T5_SR_CC1IF, 1 << 1          @ Bit 1 CC1IF: Capture/compare 1 interrupt flag
                                       @ If channel CC1 is configured as output:
                                       @ This flag is set by hardware when the counter matches the compare value, with some
                                       @ exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
                                       @ description). It is cleared by software.
                                       @ 0: No match
                                       @ 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
                                       @ When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
                                       @ goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow
                                       @ (in downcounting mode)
                                       @ If channel CC1 is configured as input:
                                       @ This bit is set by hardware on a capture. It is cleared by software or by reading the
                                       @ TIMx_CCR1 register.
                                       @ 0: No input capture occurred
                                       @ 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
                                       @ on IC1 which matches the selected polarity)
.EQU  TIM2T5_SR_UIF , 1                @ Bit 0 UIF: Update interrupt flag
                                       @ This bit is set by hardware on an update event. It is cleared by software.
                                       @ 0: No update occurred.
                                       @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                       @ At overflow or underflow (for TIM2 to TIM5) and if UDIS=0 in the TIMx_CR1 register.
                                       @ When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
                                       @ and UDIS=0 in the TIMx_CR1 register.
                                       @ When CNT is reinitialized by a trigger event (refer to the synchro control register description),
                                       @ if URS=0 and UDIS=0 in the TIMx_CR1 register.
.EQU  TIM2T5_SR_UIF_N, 0
@.END

@.ITEM     TIM2T5_EGR
.EQU  TIM2T5_EGR_TG         , 1 << 6   @ Bit 6 TG: Trigger generation
                                       @ This bit is set by software in order to generate an event, it is automatically cleared by
                                       @ hardware.
                                       @ 0: No action
                                       @ 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
                                       @ enabled.
.EQU  TIM2T5_EGR_CC4G       , 1 << 4   @ Bit 4 CC4G: Capture/compare 4 generation
                                       @ refer to CC1G description
.EQU  TIM2T5_EGR_CC3G       , 1 << 3   @ Bit 3 CC3G: Capture/compare 3 generation
                                       @ refer to CC1G description
.EQU  TIM2T5_EGR_CC2G       , 1 << 2   @ Bit 2 CC2G: Capture/compare 2 generation
                                       @ refer to CC1G description
.EQU  TIM2T5_EGR_CC1G       , 1 << 1   @ Bit 1 CC1G: Capture/compare 1 generation
                                       @ This bit is set by software in order to generate an event, it is automatically cleared by
                                       @ hardware.
                                       @ 0: No action
                                       @ 1: A capture/compare event is generated on channel 1:
                                       @ If channel CC1 is configured as output:
                                       @ CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
                                       @ If channel CC1 is configured as input:
                                       @ The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
                                       @ the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
                                       @ CC1IF flag was already high.
.EQU  TIM2T5_EGR_UG         , 1        @ Bit 0 UG: Update generation
                                       @ This bit can be set by software, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
                                       @ counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
                                       @ the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
                                       @ value (TIMx_ARR) if DIR=1 (downcounting).
@.END

@.ITEM     TIM2T5_CCMR1
.EQU  TIM2T5_CCMR1_OUTPUT_COMPARE_MODE, 0
.EQU  TIM2T5_CCMR1_INPUT_CAPTURE_MODE, 0
.EQU  TIM2T5_CCMR1_CC2S_N, 8          @ Capture/Compare 2 selection
.EQU  TIM2T5_CCMR1_CC2S_OUT, 0        @ CC2 channel is configured as output
.EQU  TIM2T5_CCMR1_CC2S_TI2, 1 << 8    @ CC2 channel is configured as input, IC4 is mapped on TI4
.EQU  TIM2T5_CCMR1_CC2S_TI1, 2 << 8    @ CC2 channel is configured as input, IC4 is mapped on TI3
.EQU  TIM2T5_CCMR1_CC2S_TRC, 3 << 8    @ CC2 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
.EQU  TIM2T5_CCMR1_CC1S_N, 0
.EQU  TIM2T5_CCMR1_CC1S_OUT, 0        @ CC1 channel is configured as output
.EQU  TIM2T5_CCMR1_CC1S_TI3, 1        @ CC1 channel is configured as input, IC3 is mapped on TI3
.EQU  TIM2T5_CCMR1_CC1S_TI4, 2        @ CC1 channel is configured as input, IC3 is mapped on TI4
.EQU  TIM2T5_CCMR1_CC1S_TRC, 3        @ CC1 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
@.END

@.ITEM     TIM2T5_CCMR1_OUTPUT_COMPARE_MODE
.EQU  TIM2T5_CCMR1_OC2CE , 1 << 15    @ Output compare 2 clear enable
.EQU  TIM2T5_CCMR1_OC2M_N, 12         @ Output compare 2 mode
.EQU  TIM2T5_CCMR1_OC2M_FROZEN, 0     @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter     TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM2T5_CCMR1_OC2M_ACT, 1 << 12    @ Set channel 2 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR1_OC2M_INACT, 2 << 12    @ Set channel 2 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR1_OC2M_TOGGLE, 3 << 12    @ Toggle - OC2REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM2T5_CCMR1_OC2M_FORSEINACT, 4 << 12    @ Force inactive level - OC2REF is forced low.
.EQU  TIM2T5_CCMR1_OC2M_FORSEACT, 5 << 12    @ Force active level - OC2REF is forced high.
.EQU  TIM2T5_CCMR1_OC2M_PWM1, 6 << 12    @  PWM mode 1 - In upcounting, channel 2 is active as long as TIMx_CNT<TIMx_CCR1  else        inactive. In downcounting, channel 1 is inactive ( OC1REF = 0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM2T5_CCMR1_OC2M_PWM2, 7 << 12    @ PWM mode 2 - In upcounting, channel 2 is inactive as long as TIMx_CNT<TIMx_CCR1 else        active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM2T5_CCMR1_OC2PE , 1 << 11    @ Output compare 2 preload enable
.EQU  TIM2T5_CCMR1_OC2FE , 1 << 10    @ Output compare 2 fast enable
.EQU  TIM2T5_CCMR1_OC1CE , 1 << 7     @ Output compare 1 clear enable
.EQU  TIM2T5_CCMR1_OC1M_N, 4          @  Output compare 1 mode
.EQU  TIM2T5_CCMR1_OC1M_FROZEN, 0           @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter
                                            @ TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM2T5_CCMR1_OC1M_ACT, 1 << 4         @ Set channel 1 to active level on match. OC1REF signal is forced high when the counter
                                            @ TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR1_OC1M_INACT, 2 << 4       @ Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter
                                            @ TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR1_OC1M_TOGGLE, 3 << 4      @ Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM2T5_CCMR1_OC1M_FORSEINACT, 4 << 4  @ Force inactive level - OC1REF is forced low.
.EQU  TIM2T5_CCMR1_OC1M_FORSEACT, 5 << 4    @ Force active level - OC1REF is forced high.
.EQU  TIM2T5_CCMR1_OC1M_PWM1, 6 << 4        @ PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else
                                            @ inactive. In downcounting, channel 1 is inactive ( OC1REF = 0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM2T5_CCMR1_OC1M_PWM2, 7 << 4        @ PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else
                                            @  active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM2T5_CCMR1_OC1PE , 1 << 3           @ Output compare 1 preload enable
.EQU  TIM2T5_CCMR1_OC1FE , 1 << 2           @ Output compare 1 fast enable
@.END

@.ITEM     TIM2T5_CCMR1_INPUT_CAPTURE_MODE
.EQU  TIM2T5_CCMR1_IC2F_N, 12         @ Input capture 2 filter
.EQU  TIM2T5_CCMR1_IC2F_NOF, 0        @ No filter, sampling is done at fDTS
.EQU  TIM2T5_CCMR1_IC2F_N2, 1 << 12    @ fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_CCMR1_IC2F_N4, 2 << 12    @ fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_CCMR1_IC2F_N8, 3 << 12    @ fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_CCMR1_IC2F_2N6, 4 << 12    @ fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_CCMR1_IC2F_2N8, 5 << 12    @ fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_CCMR1_IC2F_4N6, 6 << 12    @ fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_CCMR1_IC2F_4N8, 7 << 12    @ fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_CCMR1_IC2F_8N6, 8 << 12    @ fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_CCMR1_IC2F_8N8, 9 << 12    @ fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_CCMR1_IC2F_16N5, 10 << 12    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_CCMR1_IC2F_16N6, 11 << 12    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_CCMR1_IC2F_16N8, 12 << 12    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_CCMR1_IC2F_32N5, 13 << 12    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_CCMR1_IC2F_32N6, 14 << 12    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_CCMR1_IC2F_32N8, 15 << 12    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_CCMR1_IC2PSC_N, 8        @ Input capture 2 prescaler
.EQU  TIM2T5_CCMR1_IC2PSC_1, 0        @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM2T5_CCMR1_IC2PSC_2, 1 << 8    @ capture is done once every 2 events
.EQU  TIM2T5_CCMR1_IC2PSC_4, 2 << 8    @ capture is done once every 4 events
.EQU  TIM2T5_CCMR1_IC2PSC_8, 3 << 8    @ capture is done once every 8 events
.EQU  TIM2T5_CCMR1_IC1F_N, 4          @ Input capture 1 filter
.EQU  TIM2T5_CCMR1_IC1F_NOF, 0        @ No filter, sampling is done at fDTS
.EQU  TIM2T5_CCMR1_IC1F_N2, 1 << 4    @ fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_CCMR1_IC1F_N4, 2 << 4    @ fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_CCMR1_IC1F_N8, 3 << 4    @ fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_CCMR1_IC1F_2N6, 4 << 4    @ fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_CCMR1_IC1F_2N8, 5 << 4    @ fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_CCMR1_IC1F_4N6, 6 << 4    @ fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_CCMR1_IC1F_4N8, 7 << 4    @ fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_CCMR1_IC1F_8N6, 8 << 4    @ fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_CCMR1_IC1F_8N8, 9 << 4    @ fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_CCMR1_IC1F_16N5, 10 << 4    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_CCMR1_IC1F_16N6, 11 << 4    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_CCMR1_IC1F_16N8, 12 << 4    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_CCMR1_IC1F_32N5, 13 << 4    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_CCMR1_IC1F_32N6, 14 << 4    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_CCMR1_IC1F_32N8, 15 << 4    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_CCMR1_IC1PSC_N, 2        @ Input capture 3 prescaler
.EQU  TIM2T5_CCMR1_IC1PSC_1, 0        @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM2T5_CCMR1_IC1PSC_2, 1 << 2    @ capture is done once every 2 events
.EQU  TIM2T5_CCMR1_IC1PSC_4, 2 << 2    @ capture is done once every 4 events
.EQU  TIM2T5_CCMR1_IC1PSC_8, 3 << 2    @ capture is done once every 8 events
@.END

@.ITEM     TIM2T5_CCMR2
.EQU  TIM2T5_CCMR2_OUTPUT_COMPARE_MODE, 0
.EQU  TIM2T5_CCMR2_INPUT_CAPTURE_MODE, 0
.EQU  TIM2T5_CCMR2_CC4S_N, 8          @ Capture/Compare 4 selection
.EQU  TIM2T5_CCMR2_CC4S_OUT, 0        @ CC4 channel is configured as output
.EQU  TIM2T5_CCMR2_CC4S_TI2, 1 << 8    @ CC4 channel is configured as input, IC4 is mapped on TI4
.EQU  TIM2T5_CCMR2_CC4S_TI1, 2 << 8    @  CC4 channel is configured as input, IC4 is mapped on TI3
.EQU  TIM2T5_CCMR2_CC4S_TRC, 3 << 8    @ CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
.EQU  TIM2T5_CCMR2_CC3S_N, 0
.EQU  TIM2T5_CCMR2_CC3S_OUT, 0        @ CC3 channel is configured as output
.EQU  TIM2T5_CCMR2_CC3S_TI3, 1        @ CC3 channel is configured as input, IC3 is mapped on TI3
.EQU  TIM2T5_CCMR2_CC3S_TI4, 2        @ CC3 channel is configured as input, IC3 is mapped on TI4
.EQU  TIM2T5_CCMR2_CC3S_TRC, 3        @ CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
@.END

@.ITEM TIM2T5_CCMR2_OUTPUT_COMPARE_MODE
.EQU  TIM2T5_CCMR2_OC4CE , 1 << 15    @ Output compare 4 clear enable
.EQU  TIM2T5_CCMR2_OC4M_N, 12         @ Output compare 4 mode
.EQU  TIM2T5_CCMR2_OC4M_FROZEN, 0     @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter     TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM2T5_CCMR2_OC4M_ACT, 1 << 12    @ Set channel 4 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR2_OC4M_INACT, 2 << 12    @ Set channel 4 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR2_OC4M_TOGGLE, 3 << 12    @ Toggle - OC4REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM2T5_CCMR2_OC4M_FORSEINACT, 4 << 12    @ Force inactive level - OC4REF is forced low.
.EQU  TIM2T5_CCMR2_OC4M_FORSEACT, 5 << 12    @ Force active level - OC4REF is forced high.
.EQU  TIM2T5_CCMR2_OC4M_PWM1, 6 << 12    @  PWM mode 1 - In upcounting, channel 4 is active as long as TIMx_CNT<TIMx_CCR1  else        inactive. In downcounting, channel 1 is inactive ( OC1REF = 0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM2T5_CCMR2_OC4M_PWM2, 7 << 12    @ PWM mode 2 - In upcounting, channel 4 is inactive as long as TIMx_CNT<TIMx_CCR1 else        active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM2T5_CCMR2_OC4PE , 1 << 11    @ Output compare 4 preload enable
.EQU  TIM2T5_CCMR2_OC4FE , 1 << 10    @ Output compare 4 fast enable
.EQU  TIM2T5_CCMR2_OC3CE , 1 << 7     @ Output compare 3 clear enable
.EQU  TIM2T5_CCMR2_OC3M_N, 4          @  Output compare 3 mode
.EQU  TIM2T5_CCMR2_OC3M_FROZEN, 0     @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter     TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM2T5_CCMR2_OC3M_ACT, 1 << 4    @ Set channel 3 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR2_OC3M_INACT, 2 << 4    @ Set channel 3 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM2T5_CCMR2_OC3M_TOGGLE, 3 << 4    @ Toggle - OC3REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM2T5_CCMR2_OC3M_FORSEINACT, 4 << 4    @ Force inactive level - OC3REF is forced low.
.EQU  TIM2T5_CCMR2_OC3M_FORSEACT, 5 << 4    @ Force active level - OC3REF is forced high.
.EQU  TIM2T5_CCMR2_OC3M_PWM1, 6 << 4    @  PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNT<TIMx_CCR1  else        inactive. In downcounting, channel 1 is inactive ( OC1REF = 0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM2T5_CCMR2_OC3M_PWM2, 7 << 4    @ PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNT<TIMx_CCR1 else        active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM2T5_CCMR2_OC3PE , 1 << 3     @ Output compare 3 preload enable
.EQU  TIM2T5_CCMR2_OC3FE , 1 << 2     @ Output compare 3 fast enable
@.END

@.ITEM TIM2T5_CCMR2_INPUT_CAPTURE_MODE
.EQU  TIM2T5_CCMR2_IC4F_N, 12         @ Input capture 4 filter
.EQU  TIM2T5_CCMR2_IC4F_NOF, 0        @ No filter, sampling is done at fDTS
.EQU  TIM2T5_CCMR2_IC4F_N2, 1 << 12    @ fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_CCMR2_IC4F_N4, 2 << 12    @ fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_CCMR2_IC4F_N8, 3 << 12    @ fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_CCMR2_IC4F_2N6, 4 << 12    @ fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_CCMR2_IC4F_2N8, 5 << 12    @ fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_CCMR2_IC4F_4N6, 6 << 12    @ fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_CCMR2_IC4F_4N8, 7 << 12    @ fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_CCMR2_IC4F_8N6, 8 << 12    @ fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_CCMR2_IC4F_8N8, 9 << 12    @ fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_CCMR2_IC4F_16N5, 10 << 12    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_CCMR2_IC4F_16N6, 11 << 12    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_CCMR2_IC4F_16N8, 12 << 12    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_CCMR2_IC4F_32N5, 13 << 12    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_CCMR2_IC4F_32N6, 14 << 12    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_CCMR2_IC4F_32N8, 15 << 12    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_CCMR2_IC4PSC_N, 2        @ Input capture 4 prescaler
.EQU  TIM2T5_CCMR2_IC4PSC_1, 0        @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM2T5_CCMR2_IC4PSC_2, 1 << 2    @ capture is done once every 2 events
.EQU  TIM2T5_CCMR2_IC4PSC_4, 2 << 2    @ capture is done once every 4 events
.EQU  TIM2T5_CCMR2_IC4PSC_8, 3 << 2    @ capture is done once every 8 events
.EQU  TIM2T5_CCMR2_IC3F_N, 4          @ Input capture 3 filter
.EQU  TIM2T5_CCMR2_IC3F_NOF, 0        @ No filter, sampling is done at fDTS
.EQU  TIM2T5_CCMR2_IC3F_N2, 1 << 4    @ fSAMPLING=fCK_INT, N=2
.EQU  TIM2T5_CCMR2_IC3F_N4, 2 << 4    @ fSAMPLING=fCK_INT, N=4
.EQU  TIM2T5_CCMR2_IC3F_N8, 3 << 4    @ fSAMPLING=fCK_INT, N=8
.EQU  TIM2T5_CCMR2_IC3F_2N6, 4 << 4    @ fSAMPLING=fDTS/2, N=6
.EQU  TIM2T5_CCMR2_IC3F_2N8, 5 << 4    @ fSAMPLING=fDTS/2, N=8
.EQU  TIM2T5_CCMR2_IC3F_4N6, 6 << 4    @ fSAMPLING=fDTS/4, N=6
.EQU  TIM2T5_CCMR2_IC3F_4N8, 7 << 4    @ fSAMPLING=fDTS/4, N=8
.EQU  TIM2T5_CCMR2_IC3F_8N6, 8 << 4    @ fSAMPLING=fDTS/8, N=6
.EQU  TIM2T5_CCMR2_IC3F_8N8, 9 << 4    @ fSAMPLING=fDTS/8, N=8
.EQU  TIM2T5_CCMR2_IC3F_16N5, 10 << 4    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM2T5_CCMR2_IC3F_16N6, 11 << 4    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM2T5_CCMR2_IC3F_16N8, 12 << 4    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM2T5_CCMR2_IC3F_32N5, 13 << 4    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM2T5_CCMR2_IC3F_32N6, 14 << 4    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM2T5_CCMR2_IC3F_32N8, 15 << 4    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM2T5_CCMR2_IC3PSC_N, 2        @ Input capture 3 prescaler
.EQU  TIM2T5_CCMR2_IC3PSC_1, 0        @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM2T5_CCMR2_IC3PSC_2, 1 << 2    @ capture is done once every 2 events
.EQU  TIM2T5_CCMR2_IC3PSC_4, 2 << 2    @ capture is done once every 4 events
.EQU  TIM2T5_CCMR2_IC3PSC_8, 3 << 2    @ capture is done once every 8 events
@.END

@.ITEM TIM2T5_CCER
.EQU  TIM2T5_CCER_CC4NP  , 1 << 15    @ Bit 15 CC4NP: Capture/Compare 4 output Polarity.
                                      @ Refer to CC1NP description
.EQU  TIM2T5_CCER_CC4P   , 1 << 13    @ Bit 13 CC4P: Capture/Compare 4 output Polarity.
                                      @ refer to CC1P description
.EQU  TIM2T5_CCER_CC4E   , 1 << 12    @ Bit 12 CC4E: Capture/Compare 4 output enable.
                                      @ refer to CC1E description
.EQU  TIM2T5_CCER_CC3NP  , 1 << 11    @ Bit 11 CC3NP: Capture/Compare 3 output Polarity.
                                      @ refer to CC1NP description
.EQU  TIM2T5_CCER_CC3P   , 1 << 9     @ Bit 9 CC3P: Capture/Compare 3 output Polarity.
                                      @ refer to CC1P description
.EQU  TIM2T5_CCER_CC3E   , 1 << 8     @ Bit 8 CC3E: Capture/Compare 3 output enable.
                                      @ refer to CC1E description
.EQU  TIM2T5_CCER_CC2NP  , 1 << 7     @ Bit 7 CC2NP: Capture/Compare 2 output Polarity.
                                      @ refer to CC1NP description
.EQU  TIM2T5_CCER_CC2P   , 1 << 5     @ Bit 5 CC2P: Capture/Compare 2 output Polarity.
                                      @ refer to CC1P description
.EQU  TIM2T5_CCER_CC2E   , 1 << 4     @ Bit 4 CC2E: Capture/Compare 2 output enable.
                                      @ refer to CC1E description
.EQU  TIM2T5_CCER_CC1NP  , 1 << 3     @ Bit 3 CC1NP: Capture/Compare 1 output Polarity.
                                      @ CC1 channel configured as output:
                                      @ CC1NP must be kept cleared in this case.
                                      @ CC1 channel configured as input:
                                      @ This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
                                      @ description.
.EQU  TIM2T5_CCER_CC1P   , 1 << 1     @ Bit 1 CC1P: Capture/Compare 1 output Polarity.
                                      @ CC1 channel configured as output:
                                      @ 0: OC1 active high
                                      @ 1: OC1 active low
                                      @ CC1 channel configured as input:
                                      @ CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
                                      @ 00: noninverted/rising edge
                                      @ Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
                                      @ mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
                                      @ 01: inverted/falling edge
                                      @ Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
                                      @ mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
                                      @ 10: reserved, do not use this configuration.
                                      @ 11: noninverted/both edges
                                      @ Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
                                      @ clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
                                      @ must not be used for encoder mode.
.EQU  TIM2T5_CCER_CC1E   , 1 << 0     @ Bit 0 CC1E: Capture/Compare 1 output enable.
                                      @ CC1 channel configured as output:
                                      @ 0: Off - OC1 is not active
                                      @ 1: On - OC1 signal is output on the corresponding output pin
                                      @ CC1 channel configured as input:
                                      @ This bit determines if a capture of the counter value can actually be done into the input
                                      @ capture/compare register 1 (TIMx_CCR1) or not.
                                      @ 0: Capture disabled
                                      @ 1: Capture enabled
@.END

@.ITEM     TIM2T5_DCR
.EQU  TIM2T5_DCR_DBL_N   , 8          @ Bits 12:8 DBL[4:0]: DMA burst length
                                      @ This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
                                      @ when a read or a write access is done to the TIMx_DMAR address).
.EQU  TIM2T5_DCR_1TR     , 0          @ 1 transfer
.EQU  TIM2T5_DCR_2TR     , 1 << 8     @ 2 transfers
.EQU  TIM2T5_DCR_3TR     , 2 << 8     @ ..
.EQU  TIM2T5_DCR_4TR     , 3 << 8     @ ..
.EQU  TIM2T5_DCR_5TR     , 4 << 8     @ ..
.EQU  TIM2T5_DCR_6TR     , 5 << 8     @ ..
.EQU  TIM2T5_DCR_7TR     , 6 << 8     @ ..
.EQU  TIM2T5_DCR_8TR     , 7 << 8     @ ..
.EQU  TIM2T5_DCR_9TR     , 8 << 8     @ ..
.EQU  TIM2T5_DCR_10TR    , 9 << 8     @ ..
.EQU  TIM2T5_DCR_11TR    , 10 << 8    @ ..
.EQU  TIM2T5_DCR_12TR    , 11 << 8    @ ..
.EQU  TIM2T5_DCR_13TR    , 12 << 8    @ ..
.EQU  TIM2T5_DCR_14TR    , 13 << 8    @ ..
.EQU  TIM2T5_DCR_15TR    , 14 << 8    @ ..
.EQU  TIM2T5_DCR_16TR    , 15 << 8    @ ..
.EQU  TIM2T5_DCR_17TR    , 16 << 8    @ ..
.EQU  TIM2T5_DCR_18TR    , 17 << 8    @ 18 tranfers
.EQU  TIM2T5_DCR_DBA_N   , 0          @ Bits 4:0 DBA[4:0]: DMA base address
                                      @ This 5-bit vector defines the base-address for DMA transfers (when read/write access are
                                      @ done through the TIMx_DMAR address). DBA is defined as an offset starting from the
                                      @ address of the TIMx_CR1 register.
                             @ Example:
                                      @ 00000: TIMx_CR1,
                                      @ 00001: TIMx_CR2,
                                      @ 00010: TIMx_SMCR,
                                      @ ...
                             @ Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
                                      @ case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
@.END

@.ITEM     TIM2_OR
.EQU  TIM2_OR_ITR1_RMP_N , 10         @ Bits 11:10 ITR1_RMP: Internal trigger 1 remap
                                      @ Set and cleared by software.
.EQU  TIM2_OR_ITR1_RMP_RES, 0                @ 00: Reserved
.EQU  TIM2_OR_ITR1_RMP_PTR_TO_ITR1, 1 << 10  @ 01: PTP trigger output is connected to TIM2_ITR1
.EQU  TIM2_OR_ITR1_RMP_FS_TO_ITR1, 2 << 10   @ 10: OTG FS SOF is connected to the TIM2_ITR1 input
.EQU  TIM2_OR_ITR1_RMP_HS_TO_ITR1, 3 << 10   @ 11: OTG HS SOF is connected to the TIM2_ITR1 input
@.END

@.ITEM     TIM5_OR
.EQU  TIM5_OR_TI4_RMP_N  , 6          @ Bits 7:6 TI4_RMP: Timer Input 4 remap
                                      @ Set and cleared by software.
.EQU  TIM5_OR_TI4_RMP_TRGOUT, 0       @ 00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table
                                      @ in the datasheets.
.EQU  TIM5_OR_TI4_RMP_LSI_TO_CH4, 1 << 6  @ 01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes
.EQU  TIM5_OR_TI4_RMP_LSE_TO_CH4, 2 << 6  @ 10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes
.EQU  TIM5_OR_TI4_RMP_RTC_TO_CH4, 3 << 6  @ 11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes.
                                          @ Wakeup interrupt should be enabled.
@.END


