@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                       Константы Flash control                    |
@ |                             STM32F303                            |
@ +------------------------------------------------------------------+
@.ENDDESC

.INCLUDE       "/src/inc/base.inc"

@ базовые константы микроконтроллера

@.ITEM     AHB1PERIPH_BASE
.EQU  FLASH_R_BASE            , ( AHB1PERIPH_BASE + 0x2000 )
.EQU  FLASH_R                 , PERIPH_BASE + FLASH_R_BASE  @ 0x4002 2000
@.END

@.ITEM     FLASH_R_BASE   FLASH_R
.EQU  FLASH_ACR               , 0x00               @ Flash access control register (FLASH_ACR)
.EQU  FLASH_KEYR              , 0x04               @ Flash key register (FLASH_KEYR)
.EQU  FLASH_OPTKEYR           , 0x08               @ Flash option key register (FLASH_OPTKEYR)
.EQU  FLASH_SR                , 0x0C               @ Flash st atus re gister (FLASH_SR)
.EQU  FLASH_CR                , 0x10               @ Flash control register (FLASH_CR)
.EQU  FLASH_AR                , 0x14               @ Flash address register (FLASH_AR)
.EQU  FLASH_OBR               , 0x1C               @ Option byte register (FLASH_OBR)
.EQU  FLASH_WRPR              , 0x20               @
@.END

@.ITEM     FLASH_ACR
.EQU  FLASH_ACR_LATENCY_N     , 0                  @ Bits 2:0 LATENCY[2:0]: These bits represent the ratio of the CPU clock period to the Flash memory access time.
.EQU  FLASH_ACR_LATENCY_0     , 0
.EQU  FLASH_ACR_LATENCY_1     , 1
.EQU  FLASH_ACR_LATENCY_2     , 2
.EQU  FLASH_ACR_LATENCY_3     , 3
.EQU  FLASH_ACR_LATENCY_4     , 4
.EQU  FLASH_ACR_LATENCY_5     , 5
.EQU  FLASH_ACR_LATENCY_6     , 6
.EQU  FLASH_ACR_LATENCY_7     , 7
.EQU  FLASH_ACR_HLFCYA_N      , 3                  @ Bit 3 HLFCYA: Flash half cycle access enable
.EQU  FLASH_ACR_HLFCYA        , 1 << 3
.EQU  FLASH_ACR_PRFTBE_N      , 4                  @ Bit 4 PRFTBE: Prefetch buffer enable
.EQU  FLASH_ACR_PRFTBE        , 1 << 4
.EQU  FLASH_ACR_PRFTBS_N      , 5                  @ Bit 5 PRFTBS: Prefetch buffer status
.EQU  FLASH_ACR_PRFTBS        , 1 << 5
@.END

@.ITEM     FLASH_KEYR
.EQU  FLASH_KEYR_FKEYR_N      , 0                  @ Bits 31:0 FKEYR: Flash key
.EQU  FLASH_KEYR_FKEYR_M      , ( 0xFFFFFFFF << 0 )
.EQU  FLASH_KEY1_N            , 0                  @ Unlocking the Flash memory  c.68/1141   RM0316
.EQU  FLASH_KEY1_M            , ( 0x45670123 << 0 )    @ Write KEY1 = 0x45670123
.EQU  FLASH_KEY1              , 0x45670123         @ FPEC Key1
.EQU  FLASH_KEY2_N            , 0
.EQU  FLASH_KEY2_M            , ( 0xCDEF89AB << 0 )    @ Write KEY2 = 0xCDEF89AB
.EQU  FLASH_KEY2              , 0xCDEF89AB         @ FPEC Key2
@.END

@.ITEM     FLASH_OPTKEYR
.EQU  FLASH_OPTKEYR_OPTKEYR_N , 0                  @ Bits 31:0 OPTKEYR: Option byte key
.EQU  FLASH_OPTKEYR_OPTKEYR_M , ( 0xFFFFFFFF << 0 )
.EQU  FLASH_OPTKEYR_OPTKEYR   , 0xFFFFFFFF         @  Option Byte Key */
.EQU  FLASH_OPTKEY1           , 0x45670123         @ Option Byte Key1
.EQU  FLASH_OPTKEY2           , 0xCDEF89AB         @ Option Byte Key2
@.END

@.ITEM     FLASH_SR
.EQU  FLASH_SR_BSY_N          , 0                  @ Bit 0 BSY: Busy
.EQU  FLASH_SR_BSY            , 1
.EQU  FLASH_SR_PGERR_N        , 2                  @ Bit 2 PGERR: Programming error
.EQU  FLASH_SR_PGERR          , 1 << 2
.EQU  FLASH_SR_WRPRTERR_N     , 4                  @ Bit 4 WRPRTERR: Write protection error
.EQU  FLASH_SR_WRPRTERR       , 1 << 4
.EQU  FLASH_SR_EOP_N          , 5                  @ Bit 5 EOP: End of operation
.EQU  FLASH_SR_EOP            , 1 << 5
@.END

@.ITEM     FLASH_CR
.EQU  FLASH_CR_Reset_Value    , 0x00000080         @ Значение регистра по умолчанию
.EQU  FLASH_CR_PG_N           , 0                  @ Bit 0 PG: Programming
.EQU  FLASH_CR_PG             , 1
.EQU  FLASH_CR_PER_N          , 1                  @ Bit 1 PER: Page erase
.EQU  FLASH_CR_PER            , 1 << 1
.EQU  FLASH_CR_MER_N          , 2                  @ Bit 2 MER: Mass Erase
.EQU  FLASH_CR_MER            , 1 << 2
.EQU  FLASH_CR_OPTPG_N        , 4                  @ Bit 4 OPTPG: Option byte programming
.EQU  FLASH_CR_OPTPG          , 1 << 4
.EQU  FLASH_CR_OPTER_N        , 5                  @ Bit 5 OPTER: Option byte erase
.EQU  FLASH_CR_OPTER          , 1 << 5
.EQU  FLASH_CR_STRT_N         , 6                  @ Bit 6 STRT: Start
.EQU  FLASH_CR_STRT           , 1 << 6
.EQU  FLASH_CR_LOCK_N         , 7                  @ Bit 7 LOCK: Lock
.EQU  FLASH_CR_LOCK           , 1 << 7
.EQU  FLASH_CR_OPTWRE_N       , 9                  @ Bit 9 OPTWRE: Option bytes write enable
.EQU  FLASH_CR_OPTWRE         , 1 << 9
.EQU  FLASH_CR_ERRIE_N        , 10                 @ Bit 10 ERRIE: Error interrupt enable
.EQU  FLASH_CR_ERRIE          , 1 << 10
.EQU  FLASH_CR_EOPIE_N        , 12                 @ Bit 12 EOPIE: End of operation interrupt enable
.EQU  FLASH_CR_EOPIE          , 1 << 12
.EQU  FLASH_CR_OBL_LAUNCH_N   , 13                 @ Bit 13 OBL_LAUNCH: Force option byte loading
.EQU  FLASH_CR_OBL_LAUNCH     , 1 << 13
@.END

@.ITEM     FLASH_AR
.EQU  FLASH_AR_FAR_N          , 0                  @ Bits 31:0 FAR: Flash Address
.EQU  FLASH_AR_FAR_M          , ( 0xFFFFFFFF << 0 )
.EQU  FLASH_AR_FAR            , 0xFFFFFFFF         @ Flash Address


@.ITEM     FLASH_OBR
.EQU  FLASH_OBR_OPTERR_N      , 0                  @ Bit 0 OPTERR: Option byte Load error
.EQU  FLASH_OBR_OPTERR        , 1
.EQU  FLASH_OBR_RDPRT_N       , 1                  @ Bit 2:1 RDPRT[1:0]: Read protection Level status
.EQU  FLASH_OBR_RDPRT_0       , 0x00 << 1          @ Read protection Level 0 is enabled (ST production set up)
.EQU  FLASH_OBR_RDPRT_1       , 1 << 1             @ Read protection Level 1 is enabled
.EQU  FLASH_OBR_RDPRT_2       , 2 << 1             @ Reserved
.EQU  FLASH_OBR_RDPRT_3       , 3 << 1             @ Read protection Level 2 is enabled
.EQU  FLASH_OBR_WDG_SW_N      , 8
.EQU  FLASH_OBR_WDG_SW        , 1 << 8             @ Bit 8: WDG_SW
.EQU  FLASH_OBR_nRST_STOP_N   , 9
.EQU  FLASH_OBR_nRST_STOP     , 1 << 9             @ Bit 9: nRST_STOP
.EQU  FLASH_OBR_nRST_STDBY_N  , 10
.EQU  FLASH_OBR_nRST_STDBY    , 1 << 10            @ Bit 10: nRST_STDBY
.EQU  FLASH_OBR_nBOOT1_N      , 12
.EQU  FLASH_OBR_nBOOT1        , 1 << 12            @ Bit 12: nBOOT1
.EQU  FLASH_OBR_VDDA_MONITOR_N, 13
.EQU  FLASH_OBR_VDDA_MONITOR  , 1 << 13            @ Bit 13: VDDA_MONITOR
.EQU  FLASH_OBR_SRAM_PE_N     , 14
.EQU  FLASH_OBR_SRAM_PE       , 1 << 14            @ Bit 14: SRAM_PE
.EQU  FLASH_OBR_DATA0_N       , 16                 @ Bits 23:16 Data0
.EQU  FLASH_OBR_DATA1_N       , 24                 @ Bits 31:24 Data1
@.END

@.ITEM     FLASH_OBR
.EQU  FLASH_WRPR_WRP_N        , 0                  @ Bits 31:0 WRP: Write protect
.EQU  FLASH_WRPR_WRP_M        , ( 0xFFFFFFFF << 0 )
.EQU  FLASH_WRPR_WRP          , 0xFFFFFFFF         @ This register contains the write-protection option bytes loaded by the OBL.               /*!< Write Protect */
@.END

