@.CHARSET CP1251

@ +----------------------------------------------------------+
@ |                   Определения WWDG (Глава 20)           |
@ |                     STM32F0x0                            |
@ +----------------------------------------------------------+

.INCLUDE "/src/inc/base.inc"

@.ITEM  APBPERIPH_BASE
.EQU  WWDG_BASE           , APBPERIPH_BASE + 0x2C00
.EQU  WWDG                , PERIPH_BASE + WWDG_BASE
@.END

@.ITEM WWDG WWDG_BASE
.EQU WWDG_CR, 0x00                      @ Control register
.EQU WWDG_CFR, 0x04                     @ Configuration register
.EQU WWDG_SR, 0x08                      @ Status register
@.END

@.ITEM WWDG_CR
.EQU WWDG_CR_WDGA, 1<<7                 @ Activation bit
.EQU WWDG_CR_T_N, 0                     @ T[6:0]: 7-bit counter (MSB to LSB)
@.END

@.ITEM WWDG_CFR
.EQU WWDG_CFR_EWI, 1<<9                 @ Early wakeup interrupt
.EQU WWDG_CFR_WDGTB_N, 7                @ WDGTB[1:0]: Timer base
.EQU WWDG_CFR_WDGTB0, 0X00<<7           @ 00: CK Counter Clock (PCLK div 4096) div 1
.EQU WWDG_CFR_WDGTB1, 0X01<<7           @ 01: CK Counter Clock (PCLK div 4096) div 2
.EQU WWDG_CFR_WDGTB2, 0X02<<7           @ 10: CK Counter Clock (PCLK div 4096) div 4
.EQU WWDG_CFR_WDGTB3, 0X03<<7           @ 11: CK Counter Clock (PCLK div 4096) div 8
.EQU WWDG_CFR_W_N, 0                    @ W[6:0]: 7-bit window value
@.END

@.ITEM WWDG_SR
.EQU WWDG_SR_EWIF, 1<<0                 @ EWIF: Early wakeup interrupt flag
@.END




