@GNU AS
@.CharSet=CP1251 (Cyrillic)

@.desc type=module
@ +------------------------------------------------------------------+
@ |                Определения Memory Protection Unit                |
@ |                            CORTEX-M4                             |
@ +------------------------------------------------------------------+
@.enddesc

.include    "/src/inc/base.inc"

@.item MPU_BASE
.equ MPU_TYPER      , 0x000 @ (R)  MPU Type Register
.equ MPU_CTRL       , 0x004 @ (R/W)  MPU Control Register
.equ MPU_RNR        , 0x008 @ (R/W)  MPU Region RNRber Register
.equ MPU_RBAR       , 0x00C @ (R/W)  MPU Region Base Address Register
.equ MPU_RASR       , 0x010 @ (R/W)  MPU Region Attribute and Size Register
.equ MPU_RBAR_A1    , 0x014 @ (R/W)  MPU Alias 1 Region Base Address Register
.equ MPU_RASR_A1    , 0x018 @ (R/W)  MPU Alias 1 Region Attribute and Size Register
.equ MPU_RBAR_A2    , 0x01C @ (R/W)  MPU Alias 2 Region Base Address Register
.equ MPU_RASR_A2    , 0x020 @ (R/W)  MPU Alias 2 Region Attribute and Size Register
.equ MPU_RBAR_A3    , 0x024 @ (R/W)  MPU Alias 3 Region Base Address Register
.equ MPU_RASR_A3    , 0x028 @ (R/W)  MPU Alias 3 Region Attribute and Size Register
@.end


.equ MPU_TYPE_RALIASES   , 4


@.item MPU_TYPER
.equ MPU_TYPER_ResetValue , 0                           @ Значение после сброса
.equ MPU_TYPER_IREGION_N  , 16
.equ MPU_TYPER_IREGION_M  , 0xFF << MPU_TYPE_IREGION_N  @ IREGION[7:0]: Number of MPU instruction regions.
.equ MPU_TYPER_DREGION_N  , 8
.equ MPU_TYPER_DREGION_M  , 0xFF << MPU_TYPE_DREGION_N  @ DREGION[7:0]: Number of MPU data regions. 0 - MPU not present
.equ MPU_TYPER_SEPARATE_N , 0
.equ MPU_TYPER_SEPARATE   , 1 << MPU_TYPE_SEPARATE_N    @ SEPARATE: Separate flag.
@.end

@.item MPU_CTRL
.equ MPU_CTRL_ResetValue      , 0
.equ MPU_CTRL_PRIVDEFENA_N    , 2
.equ MPU_CTRL_PRIVDEFENA      , 1 << MPU_CTRL_PRIVDEFENA_N  @ Enable priviliged software access to default memory map.
.equ MPU_CTRL_HFNMIENA_N      , 1
.equ MPU_CTRL_HFNMIENA        , 1 << MPU_CTRL_HFNMIENA_N    @ Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
.equ MPU_CTRL_ENABLE_N        , 0
.equ MPU_CTRL_ENABLE          , 1 << MPU_CTRL_ENABLE_N      @ Enables the MPU
@.end


@.item MPU_RNR
.equ MPU_RNR_ResetValue       , 0
.equ MPU_RNR_REGION_N         , 0
.equ MPU_RNR_REGION_M         , 0xFF << MPU_RNR_REGION_N   @ MPU region
@.end


@.item MPU_RBAR
.equ MPU_RBAR_ResetValue , 0
.equ MPU_RBAR_ADDR_N     , 5
.equ MPU_RBAR_ADDR_M     , 0x7FFFFFF << MPU_RBAR_ADDR_N @ Region base address field
.equ MPU_RBAR_VALID_N    , 4
.equ MPU_RBAR_VALID      , 1 << MPU_RBAR_VALID_N        @ MPU region number valid
.equ MPU_RBAR_REGION_N   , 0
.equ MPU_RBAR_REGION_M   , 0xF << MPU_RBAR_REGION_N     @ MPU region field
@.end


@.item MPU_RASR
.equ MPU_RASR_ATTRS_N    , 16
.equ MPU_RASR_ATTRS_M    , 0xFFFF << MPU_RASR_ATTRS_N
.equ MPU_RASR_XN_N       , 28
.equ MPU_RASR_XN         , 1 << MPU_RASR_XN_N   @ Instruction access disable bit:
.equ MPU_RASR_AP_N       , 24
.equ MPU_RASR_AP_M       , 0x7 << MPU_RASR_AP_N @ Access permission
.equ MPU_RASR_TEX_N      , 19
.equ MPU_RASR_TEX_M      , 0x7 << MPU_RASR_TEX_N @ TEX[2:0]: memory attribute
.equ MPU_RASR_S_N        , 18
.equ MPU_RASR_S          , 1 << MPU_RASR_S_N     @ Shareable memory attribute
.equ MPU_RASR_C_N        , 17
.equ MPU_RASR_C          , 1 << MPU_RASR_C_N     @ C: memory attribute
.equ MPU_RASR_B_N        , 16
.equ MPU_RASR_B          , 1 << MPU_RASR_B_N     @ B: memory attribute
.equ MPU_RASR_SRD_N      , 8
.equ MPU_RASR_SRD_M      , 0xFF << MPU_RASR_SRD_N @ Subregion disable bits.
.equ MPU_RASR_SIZE_N     , 1
.equ MPU_RASR_SIZE_M     , 0x1F << MPU_RASR_SIZE_N @ Size of the MPU protection region.
.equ MPU_RASR_ENABLE_N   , 0
.equ MPU_RASR_ENABLE     , 1 << MPU_RASR_ENABLE_N  @ Region enable bit
@.end


@.item MPU_RBAR_A1
.equ MPU_RBAR_A1_ResetValue , 0
.equ MPU_RBAR_A1_ADDR_N     , 5
.equ MPU_RBAR_A1_ADDR_M     , 0x7FFFFFF << MPU_RBAR_A1_ADDR_N @ Region base address field
.equ MPU_RBAR_A1_VALID_N    , 4
.equ MPU_RBAR_A1_VALID      , 1 << MPU_RBAR_A1_VALID_N        @ MPU region number valid
.equ MPU_RBAR_A1_REGION_N   , 0
.equ MPU_RBAR_A1_REGION_M   , 0xF << MPU_RBAR_A1_REGION_N     @ MPU region field
@.end


@.item MPU_RASR_A1
.equ MPU_RASR_A1_ATTRS_N    , 16
.equ MPU_RASR_A1_ATTRS_M    , 0xFFFF << MPU_RASR_A1_ATTRS_N
.equ MPU_RASR_A1_XN_N       , 28
.equ MPU_RASR_A1_XN         , 1 << MPU_RASR_A1_XN_N   @ Instruction access disable bit:
.equ MPU_RASR_A1_AP_N       , 24
.equ MPU_RASR_A1_AP_M       , 0x7 << MPU_RASR_A1_AP_N @ Access permission
.equ MPU_RASR_A1_TEX_N      , 19
.equ MPU_RASR_A1_TEX_M      , 0x7 << MPU_RASR_A1_TEX_N @ TEX[2:0]: memory attribute
.equ MPU_RASR_A1_S_N        , 18
.equ MPU_RASR_A1_S          , 1 << MPU_RASR_A1_S_N     @ Shareable memory attribute
.equ MPU_RASR_A1_C_N        , 17
.equ MPU_RASR_A1_C          , 1 << MPU_RASR_A1_C_N     @ C: memory attribute
.equ MPU_RASR_A1_B_N        , 16
.equ MPU_RASR_A1_B          , 1 << MPU_RASR_A1_B_N     @ B: memory attribute
.equ MPU_RASR_A1_SRD_N      , 8
.equ MPU_RASR_A1_SRD_M      , 0xFF << MPU_RASR_A1_SRD_N @ Subregion disable bits.
.equ MPU_RASR_A1_SIZE_N     , 1
.equ MPU_RASR_A1_SIZE_M     , 0x1F << MPU_RASR_A1_SIZE_N @ Size of the MPU protection region.
.equ MPU_RASR_A1_ENABLE_N   , 0
.equ MPU_RASR_A1_ENABLE     , 1 << MPU_RASR_A1_ENABLE_N  @ Region enable bit
@.end

@.item MPU_RBAR_A2
.equ MPU_RBAR_A2_ResetValue , 0
.equ MPU_RBAR_A2_ADDR_N     , 5
.equ MPU_RBAR_A2_ADDR_M     , 0x7FFFFFF << MPU_RBAR_A2_ADDR_N @ Region base address field
.equ MPU_RBAR_A2_VALID_N    , 4
.equ MPU_RBAR_A2_VALID      , 1 << MPU_RBAR_A2_VALID_N        @ MPU region number valid
.equ MPU_RBAR_A2_REGION_N   , 0
.equ MPU_RBAR_A2_REGION_M   , 0xF << MPU_RBAR_A2_REGION_N     @ MPU region field
@.end


@.item MPU_RASR_A2
.equ MPU_RASR_A2_ATTRS_N    , 16
.equ MPU_RASR_A2_ATTRS_M    , 0xFFFF << MPU_RASR_A2_ATTRS_N
.equ MPU_RASR_A2_XN_N       , 28
.equ MPU_RASR_A2_XN         , 1 << MPU_RASR_A2_XN_N   @ Instruction access disable bit:
.equ MPU_RASR_A2_AP_N       , 24
.equ MPU_RASR_A2_AP_M       , 0x7 << MPU_RASR_A2_AP_N @ Access permission
.equ MPU_RASR_A2_TEX_N      , 19
.equ MPU_RASR_A2_TEX_M      , 0x7 << MPU_RASR_A2_TEX_N @ TEX[2:0]: memory attribute
.equ MPU_RASR_A2_S_N        , 18
.equ MPU_RASR_A2_S          , 1 << MPU_RASR_A2_S_N     @ Shareable memory attribute
.equ MPU_RASR_A2_C_N        , 17
.equ MPU_RASR_A2_C          , 1 << MPU_RASR_A2_C_N     @ C: memory attribute
.equ MPU_RASR_A2_B_N        , 16
.equ MPU_RASR_A2_B          , 1 << MPU_RASR_A2_B_N     @ B: memory attribute
.equ MPU_RASR_A2_SRD_N      , 8
.equ MPU_RASR_A2_SRD_M      , 0xFF << MPU_RASR_A2_SRD_N @ Subregion disable bits.
.equ MPU_RASR_A2_SIZE_N     , 1
.equ MPU_RASR_A2_SIZE_M     , 0x1F << MPU_RASR_A2_SIZE_N @ Size of the MPU protection region.
.equ MPU_RASR_A2_ENABLE_N   , 0
.equ MPU_RASR_A2_ENABLE     , 1 << MPU_RASR_A2_ENABLE_N  @ Region enable bit
@.end

@.item MPU_RBAR_A3
.equ MPU_RBAR_A3_ResetValue , 0
.equ MPU_RBAR_A3_ADDR_N     , 5
.equ MPU_RBAR_A3_ADDR_M     , 0x7FFFFFF << MPU_RBAR_A3_ADDR_N @ Region base address field
.equ MPU_RBAR_A3_VALID_N    , 4
.equ MPU_RBAR_A3_VALID      , 1 << MPU_RBAR_A3_VALID_N        @ MPU region number valid
.equ MPU_RBAR_A3_REGION_N   , 0
.equ MPU_RBAR_A3_REGION_M   , 0xF << MPU_RBAR_A3_REGION_N     @ MPU region field
@.end


@.item MPU_RASR_A3
.equ MPU_RASR_A3_ATTRS_N    , 16
.equ MPU_RASR_A3_ATTRS_M    , 0xFFFF << MPU_RASR_A3_ATTRS_N
.equ MPU_RASR_A3_XN_N       , 28
.equ MPU_RASR_A3_XN         , 1 << MPU_RASR_A3_XN_N   @ Instruction access disable bit:
.equ MPU_RASR_A3_AP_N       , 24
.equ MPU_RASR_A3_AP_M       , 0x7 << MPU_RASR_A3_AP_N @ Access permission
.equ MPU_RASR_A3_TEX_N      , 19
.equ MPU_RASR_A3_TEX_M      , 0x7 << MPU_RASR_A3_TEX_N @ TEX[2:0]: memory attribute
.equ MPU_RASR_A3_S_N        , 18
.equ MPU_RASR_A3_S          , 1 << MPU_RASR_A3_S_N     @ Shareable memory attribute
.equ MPU_RASR_A3_C_N        , 17
.equ MPU_RASR_A3_C          , 1 << MPU_RASR_A3_C_N     @ C: memory attribute
.equ MPU_RASR_A3_B_N        , 16
.equ MPU_RASR_A3_B          , 1 << MPU_RASR_A3_B_N     @ B: memory attribute
.equ MPU_RASR_A3_SRD_N      , 8
.equ MPU_RASR_A3_SRD_M      , 0xFF << MPU_RASR_A3_SRD_N @ Subregion disable bits.
.equ MPU_RASR_A3_SIZE_N     , 1
.equ MPU_RASR_A3_SIZE_M     , 0x1F << MPU_RASR_A3_SIZE_N @ Size of the MPU protection region.
.equ MPU_RASR_A3_ENABLE_N   , 0
.equ MPU_RASR_A3_ENABLE     , 1 << MPU_RASR_A3_ENABLE_N  @ Region enable bit
@.end





