@.CHARSET CP1251


@.ITEM USART1 USART2 USART3 USART4 USART5 USART6 USART1_BASE USART2_BASE USART3_BASE USART4_BASE USART5_BASE USART6_BASE
.EQU USART_CR1, 0x00                              @ Control register 1
.EQU USART_CR2, 0x04                              @ Control register 2
.EQU USART_CR3, 0x08                              @ Control register 3
.EQU USART_BRR, 0x0C                              @ Baud rate register
.EQU USART_RTOR, 0x14                             @ Receiver timeout register
.EQU USART_RQR, 0x18                              @ Request register
.EQU USART_ISR, 0x1C                              @ Interrupt and status register
.EQU USART_ICR, 0x20                              @ Interrupt flag clear register
.EQU USART_RDR, 0x24                              @ Receive data register
.EQU USART_TDR, 0x28                              @ Transmit data register
@.END

@.ITEM USART_CR1
.EQU USART_CR1_M1, 1<<28                          @ Word length
.EQU USART_CR1_RTOIE, 1<<26                       @ Receiver timeout interrupt enable
.EQU USART_CR1_DEAT_N, 21                         @ Driver Enable assertion time
.EQU USART_CR1_DEDT_N, 16                         @ Driver Enable de-assertion time
.EQU USART_CR1_OVER8, 1<<15                       @ Oversampling mode
.EQU USART_CR1_CMIE, 1<<14                        @ Character match interrupt enable
.EQU USART_CR1_MME, 1<<13                         @ Mute mode enable
.EQU USART_CR1_M0, 1<<12                          @ Word length
.EQU USART_CR1_WAKE, 1<11                         @ Receiver wakeup method
.EQU USART_CR1_PCE, 1<<10                         @ Parity control enable
.EQU USART_CR1_PS, 1<<9                           @ Parity selection
.EQU USART_CR1_PEIE, 1<<8                         @ PE interrupt enable
.EQU USART_CR1_TXEIE, 1<<7                        @ interrupt enable
.EQU USART_CR1_TCIE, 1<<6                         @ Transmission complete interrupt enable
.EQU USART_CR1_RXNEIE, 1<<5                       @ RXNE interrupt enable
.EQU USART_CR1_IDLEIE, 1<<4                       @ IDLE interrupt enable
.EQU USART_CR1_TE, 1<<3                           @ Transmitter enable
.EQU USART_CR1_RE, 1<<2                           @ Receiver enable
.EQU USART_CR1_UE, 1<<0                           @ USART enable
@.END

@.ITEM USART_CR2
.EQU USART_CR2_ADD_N, 24                          @ Address of the USART node
.EQU USART_CR2_RTOEN, 1<<23                       @ Receiver timeout enable
.EQU USART_CR2_ABRMOD_N, 21                       @ Auto baud rate mode
.EQU USART_CR2_ABRMOD0, 0x00<<21                  @ 00: Measurement of the start bit is used to detect the baud rate.
.EQU USART_CR2_ABRMOD1, 0x01<<21                  @ 01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx)
.EQU USART_CR2_ABRMOD2, 0x02<<21                  @ 10: 0x7F frame detection.
.EQU USART_CR2_ABRMOD3, 0x03<<21                  @ 11: 0x55 frame detection
.EQU USART_CR2_ABREN, 1<<20                       @ Auto baud rate enable
.EQU USART_CR2_MSBFIRST, 1<<19                    @ Most significant bit first
.EQU USART_CR2_DATAINV, 1<<18                     @ Binary data inversion
.EQU USART_CR2_TXINV, 1<<17                       @ TX pin active level inversion
.EQU USART_CR2_RXINV, 1<<16                       @ RX pin active level inversion
.EQU USART_CR2_SWAP, 1<<15                        @ Swap TX/RX pins
.EQU USART_CR2_STOP_N, 12                         @ STOP bits
.EQU USART_CR2_STOP0,0x00<<12                     @ 00: 1 stop bit
.EQU USART_CR2_STOP1,0x01<<12                     @ 01: Reserved
.EQU USART_CR2_STOP2,0x02<<12                     @ 10: 2 stop bits
.EQU USART_CR2_STOP3,0x03<<12                     @ 11: Reserved
.EQU USART_CR2_CLKEN, 1<<11                       @ Clock enable
.EQU USART_CR2_CPOL, 1<<10                        @ Clock polarity
.EQU USART_CR2_CPHA, 1<<9                         @ Clock phase
.EQU USART_CR2_LBCL, 1<<8                         @ Last bit clock pulse
.EQU USART_CR2_ADDM7, 1<<4                        @7-bit Address Detection/4-bit Address Detection
@.END

@.ITEM USART_CR3
.EQU USART_CR3_DEP, 1<<15                         @ Driver enable polarity selection
.EQU USART_CR3_DEM, 1<<14                         @ Driver enable mode
.EQU USART_CR3_DDRE, 1<<13                        @ DMA Disable on Reception Error
.EQU USART_CR3_OVRDIS, 1<<12                      @ Overrun Disable
.EQU USART_CR3_ONEBIT, 1<<11                      @ One sample bit method enable
.EQU USART_CR3_CTSIE, 1<<10                       @ CTS interrupt enable
.EQU USART_CR3_CTSE, 1<<9                         @ CTS enable
.EQU USART_CR3_RTSE, 1<<8                         @ RTS enable
.EQU USART_CR3_DMAT, 1<<7                         @ DMA enable transmitter
.EQU USART_CR3_DMAR, 1<<6                         @ DMA enable receiver
.EQU USART_CR3_HDSEL, 1<<3                        @ Half-duplex selection
.EQU USART_CR3_EIE, 1<<0                          @ Error interrupt enable
@.END

@.ITEN USART_BRR
.EQU USART_BRR_BRR_N, 0                           @ brr[15:0] Baud rate
@.END

@.ITEM USART_RTOR
.EQU USART_RTOR_RTO_N, 0                          @ Receiver timeout value
@.END

@.ITEM USART_RQR
.EQU USART_RQR_RXFRQ, 1<<3                        @ Receive data flush request
.EQU USART_RQR_MMRQ, 1<<2                         @ Mute mode request
.EQU USART_RQR_SBKRQ, 1<<1                        @ Send break request
.EQU USART_RQR_ABRRQ, 1<<0                        @ Auto baud rate request
@.END

@.ITEM USART_ISR
.EQU USART_ISR_RWU, 1<<19                         @ Receiver wakeup from Mute mode
.EQU USART_ISR_SBKF, 1<<18                        @ Send break flag
.EQU USART_ISR_CMF, 1<<17                         @ Character match flag
.EQU USART_ISR_BUSY, 1<<16                        @ Busy flag
.EQU USART_ISR_ABRF, 1<<15                        @ Auto baud rate flag
.EQU USART_ISR_ABRE, 1<<14                        @ Auto baud rate error
.EQU USART_ISR_RTOF, 1<<11                        @ Receiver timeout
.EQU USART_ISR_CTS, 1<<10                         @ CTS flag
.EQU USART_ISR_CTSIF, 1<<9                        @ CTS interrupt flag
.EQU USART_ISR_TXE, 1<<7                          @ Transmit data register empty
.EQU USART_ISR_TC, 1<<6                           @ Transmission complete
.EQU USART_ISR_RXNE, 1<<5                         @ Read data register not empty
.EQU USART_ISR_IDLE, 1<<4                         @ Idle line detected
.EQU USART_ISR_ORE, 1<<3                          @ Overrun error
.EQU USART_ISR_NF, 1<<2                           @ START bit Noise detection flag
.EQU USART_ISR_FE, 1<<1                           @ Framing error
.EQU USART_ISR_PE, 1<<0                           @ Parity error
@.END

@.ITEM USART_ICR
.EQU USART_ICR_CMCF, 1<<17                        @ Character match clear flag
.EQU USART_ICR_RTOCF, 1<<11                       @ Receiver timeout clear flag
.EQU USART_ICR_CTSCF, 1<<9                        @ CTS clear flag
.EQU USART_ICR_TCCF, 1<<6                         @ Transmission complete clear flag
.EQU USART_ICR_IDLECF, 1<<4                       @ Idle line detected clear flag
.EQU USART_ICR_ORECF, 1<<3                        @ Overrun error clear flag
.EQU USART_ICR_NCF, 1<<2                          @ Noise detected clear flag
.EQU USART_ICR_FECF, 1<<1                         @ Framing error clear flag
.EQU USART_ICR_PECF, 1<<0                         @ Parity error clear flag
@.END

@.ITEM USART_RDR
.EQU USART_RDR_RDR_N, 0                           @ RDR[8:0]: Receive data value
@.END

@.ITEM USART_TDR
.EQU USART_TDR_TDR_N, 0                           @ TDR[8:0]: Transmit data value
@.END


