
@.ITEM     TIM10_BASE TIM11_BASE TIM13_BASE TIM14_BASE TIM10 TIM11 TIM13 TIM14
.EQU  TIM10T11A13T14_CR1 , 0x00     @ TIM10/11/13/14 control register 1 (TIMx_CR1)
.EQU  TIM10T11A13T14_DIER, 0x0C     @ TIM10/11/13/14 Interrupt enable register (TIMx_DIER)
.EQU  TIM10T11A13T14_SR  , 0x10     @ TIM10/11/13/14 status register (TIMx_SR)
.EQU  TIM10T11A13T14_EGR , 0x14     @ TIM10/11/13/14 event generation register (TIMx_EGR)
.EQU  TIM10T11A13T14_CCMR1, 0x18    @ TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1)
.EQU  TIM10T11A13T14_CCER, 0x20     @ TIM10/11/13/14 capture/compare enable register (TIMx_CCER)
.EQU  TIM10T11A13T14_CNT , 0x24     @ TIM10/11/13/14 counter (TIMx_CNT)
.EQU  TIM10T11A13T14_PSC , 0x28     @ TIM10/11/13/14 p rescaler (T IMx_PSC)
.EQU  TIM10T11A13T14_ARR , 0x2C     @ TIM10/11/13/14 auto-reload register (TIMx_ARR)
.EQU  TIM10T11A13T14_CCR1, 0x34     @ TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)
.EQU  TIM11_OR           , 0x50     @ TIM11 option register 1 (TIM11_OR)
@.end

@.ITEM     TIM10T11A13T14_CR1
.EQU  TIM10T11A13T14_CR1_CKD_N     , 8          @ Bits 9:8 CKD: Clock division
                                                @ This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
                                                @ sampling clock used by the digital filters (TIx),
.EQU  TIM10T11A13T14_CR1_CKD_1     , 0          @ 00: tDTS = tCK_INT
.EQU  TIM10T11A13T14_CR1_CKD_2     , 1 << 8     @ 01: tDTS = 2 x tCK_INT
.EQU  TIM10T11A13T14_CR1_CKD_4     , 2 << 8     @ 10: tDTS = 4 x tCK_INT
.EQU  TIM10T11A13T14_CR1_APRE      , 1 << 7     @ Bit 7 ARPE: Auto-reload preload enable
                                                @ 0: TIMx_ARR register is not buffered.
                                                @ 1: TIMx_ARR register is buffered.
.EQU  TIM10T11A13T14_CR1_OPM       , 1 << 3     @ Bit 3 OPM: One-pulse mode
                                                @  0: Counter is not stopped on the update event
                                                @ 1: Counter stops counting on the next update event (clearing the CEN bit).
.EQU  TIM10T11A13T14_CR1_URS       , 1 << 2     @ Bit 2 URS: Update request source
                                                @ This bit is set and cleared by software to select the UEV event sources.
                                                @ 0: Any of the following events generates an update interrupt if enabled:
                                                @ – Counter overflow
                                                @ – Setting the UG bit
                                                @ 1: Only counter overflow generates an update interrupt if enabled
.EQU  TIM10T11A13T14_CR1_UDIS      , 1 << 1     @ Bit 1 UDIS: Update disable
                                                @ This bit is set and cleared by software to enable/disable update event (UEV) generation.
                                                @ 0: UEV enabled. An UEV is generated by one of the following events:
                                                @ – Counter overflow
                                                @ – Setting the UG bit
                                                @ Buffered registers are then loaded with their preload values.
                                                @ 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
                                                @ CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
.EQU  TIM10T11A13T14_CR1_CEN       , 1          @ Bit 0 CEN: Counter enable
                                                @ 0: Counter disabled
                                                @ 1: Counter enabled
                                                @ CEN is cleared automatically in one-pulse mode, when an update event occurs.
@.end

@.ITEM     TIM10T11A13T14_DIER
.EQU  TIM10T11A13T14_DIER_CC1IE , 1 << 1     @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
                                             @ 0: CC1 interrupt disabled.
                                             @ 1: CC1 interrupt enabled.
.EQU  TIM10T11A13T14_DIER_UIE   , 1          @ Bit 0 UIE: Update interrupt enable
                                             @ 0: Update interrupt disabled.
                                             @ 1: Update interrupt enabled.
@.end

@.ITEM     TIM10T11A13T14_SR
.EQU  TIM10T11A13T14_SR_CC1OF       , 1 << 9     @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
                                                 @ This flag is set by hardware only when the corresponding channel is configured in input
                                                 @ capture mode. It is cleared by software by writing it to ‘0’.
                                                 @ 0: No overcapture has been detected.
                                                 @ 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
                                                 @ already set
.EQU  TIM10T11A13T14_SR_CC1IF       , 1 << 1     @ Bit 1 CC1IF: Capture/compare 1 interrupt flag
                                                 @ If channel CC1 is configured as output:
                                                 @ This flag is set by hardware when the counter matches the compare value. It is cleared by
                                                 @ software.
                                                 @ 0: No match.
                                                 @ 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
                                                 @ When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
                                                 @ bit goes high on the counter overflow.
                                                 @ If channel CC1 is configured as input:
                                                 @ This bit is set by hardware on a capture. It is cleared by software or by reading the
                                                 @ TIMx_CCR1 register.
                                                 @ 0: No input capture occurred.
                                                 @ 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
                                                 @ on IC1 which matches the selected polarity).
.EQU  TIM10T11A13T14_SR_UIF         , 1          @ Bit 0 UIF: Update interrupt flag
                                                 @ This bit is set by hardware on an update event. It is cleared by software.
                                                 @ 0: No update occurred.
                                                 @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                                 @ – At overflow and if UDIS=’0’ in the TIMx_CR1 register.
                                                 @ – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and
                                                 @ UDIS=’0’ in the TIMx_CR1 register.
                                                 @ – When CNT is reinitialized by a trigger event (refer to the synchro control register
                                                 @ description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
@.end

@.ITEM     TIM10T11A13T14_EGR
.EQU  TIM10T11A13T14_EGR_CC1G    , 1 << 1     @ Bit 1 CC1G: Capture/compare 1 generation
                                              @ This bit is set by software to generate an event, it is automatically cleared by hardware.
                                              @ 0: No action
                                              @ 1: A capture/compare event is generated on channel 1:
                                              @ If channel CC1 is configured as output:
                                              @ the CC1IF flag is set, the corresponding interrupt is sent if enabled.
                                              @ If channel CC1 is configured as input:
                                              @ The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
                                              @ corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
                                              @ already high.
.EQU  TIM10T11A13T14_EGR_UG      , 1          @ Bit 0 UG: Update generation
                                              @ This bit can be set by software, it is automatically cleared by hardware.
                                              @ 0: No action
                                              @ 1: Re-initializes the counter and generates an update of the registers. The prescaler counter
                                              @ is also cleared and the prescaler ratio is not affected. The counter is cleared.
@.end

@.ITEM     TIM10T11A13T14_CCMR1
.EQU  TIM10T11A13T14_CCMR1_OUTPUT_COMPARE_MODE, 0
.EQU  TIM10T11A13T14_CCMR1_INPUT_CAPTURE_MODE, 0
.EQU  TIM10T11A13T14_CCMR1_CC1S_N   , 0
.EQU  TIM10T11A13T14_CCMR1_CC1S_OUT , 0          @ CC1 channel is configured as output
.EQU  TIM10T11A13T14_CCMR1_CC1S_TI3 , 1          @ CC1 channel is configured as input, IC3 is mapped on TI3
.EQU  TIM10T11A13T14_CCMR1_CC1S_TI4 , 2          @ CC1 channel is configured as input, IC3 is mapped on TI4
.EQU  TIM10T11A13T14_CCMR1_CC1S_TRC , 3          @ CC1 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

@.ITEM     TIM10T11A13T14_CCMR1_OUTPUT_COMPARE_MODE
.EQU  TIM10T11A13T14_CCMR1_OC1M_N   , 4          @  Output compare 1 mode
.EQU  TIM10T11A13T14_CCMR1_OC1M_FROZEN, 0        @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter     TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM10T11A13T14_CCMR1_OC1M_ACT , 1 << 4     @ Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM10T11A13T14_CCMR1_OC1M_INACT, 2 << 4    @ Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM10T11A13T14_CCMR1_OC1M_TOGGLE, 3 << 4    @ Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM10T11A13T14_CCMR1_OC1M_FORSEINACT, 4 << 4    @ Force inactive level - OC1REF is forced low.
.EQU  TIM10T11A13T14_CCMR1_OC1M_FORSEACT, 5 << 4    @ Force active level - OC1REF is forced high.
.EQU  TIM10T11A13T14_CCMR1_OC1M_PWM1, 6 << 4     @  PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1  else        inactive. In downcounting, channel 1 is inactive ( OC1REF = ‘0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM10T11A13T14_CCMR1_OC1M_PWM2, 7 << 4     @ PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else        active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM10T11A13T14_CCMR1_OC1PE    , 1 << 3     @ Output compare 1 preload enable
.EQU  TIM10T11A13T14_CCMR1_OC1FE    , 1 << 2     @ Output compare 1 fast enable

@.ITEM     TIM10T11A13T14_CCMR1_INPUT_CAPTURE_MODE
.EQU  TIM10T11A13T14_CCMR1_IC1F_N   , 4          @ Input capture 1 filter
.EQU  TIM10T11A13T14_CCMR1_IC1F_NOF , 0          @ No filter, sampling is done at fDTS
.EQU  TIM10T11A13T14_CCMR1_IC1F_N2  , 1 << 4     @ fSAMPLING=fCK_INT, N=2
.EQU  TIM10T11A13T14_CCMR1_IC1F_N4  , 2 << 4     @ fSAMPLING=fCK_INT, N=4
.EQU  TIM10T11A13T14_CCMR1_IC1F_N8  , 3 << 4     @ fSAMPLING=fCK_INT, N=8
.EQU  TIM10T11A13T14_CCMR1_IC1F_2N6 , 4 << 4     @ fSAMPLING=fDTS/2, N=6
.EQU  TIM10T11A13T14_CCMR1_IC1F_2N8 , 5 << 4     @ fSAMPLING=fDTS/2, N=8
.EQU  TIM10T11A13T14_CCMR1_IC1F_4N6 , 6 << 4     @ fSAMPLING=fDTS/4, N=6
.EQU  TIM10T11A13T14_CCMR1_IC1F_4N8 , 7 << 4     @ fSAMPLING=fDTS/4, N=8
.EQU  TIM10T11A13T14_CCMR1_IC1F_8N6 , 8 << 4     @ fSAMPLING=fDTS/8, N=6
.EQU  TIM10T11A13T14_CCMR1_IC1F_8N8 , 9 << 4     @ fSAMPLING=fDTS/8, N=8
.EQU  TIM10T11A13T14_CCMR1_IC1F_16N5, 10 << 4    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM10T11A13T14_CCMR1_IC1F_16N6, 11 << 4    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM10T11A13T14_CCMR1_IC1F_16N8, 12 << 4    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM10T11A13T14_CCMR1_IC1F_32N5, 13 << 4    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM10T11A13T14_CCMR1_IC1F_32N6, 14 << 4    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM10T11A13T14_CCMR1_IC1F_32N8, 15 << 4    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM10T11A13T14_CCMR1_IC1PSC_N , 2          @ Input capture 3 prescaler
.EQU  TIM10T11A13T14_CCMR1_IC1PSC_1 , 0          @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM10T11A13T14_CCMR1_IC1PSC_2 , 1 << 2     @ capture is done once every 2 events
.EQU  TIM10T11A13T14_CCMR1_IC1PSC_4 , 2 << 2     @ capture is done once every 4 events
.EQU  TIM10T11A13T14_CCMR1_IC1PSC_8 , 3 << 2     @ capture is done once every 8 events

@.ITEM     TIM10T11A13T14_CCER
.EQU  TIM10T11A13T14_CCER_CC1NP     , 1 << 3     @ Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity
                                                 @ CC1 channel configured as output: CC1NP must be kept cleared
                                                 @ CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define
                                                 @ TI1FP1/TI2FP1 polarity (refer to CC1P description).
.EQU  TIM10T11A13T14_CCER_CC1P      , 1 << 1     @ Bit 1 CC1P: Capture/Compare 1 output Polarity.
                                                 @ CC1 channel configured as output:
                                                 @ 0: OC1 active high.
                                                 @ 1: OC1 active low.
                                                 @ CC1 channel configured as input:
                                                 @ CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
                                                 @ 00: noninverted/rising edge
                                                 @ Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
                                                 @ mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
                                                 @ 01: inverted/falling edge
                                                 @ Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
                                                 @ mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
                                                 @ 10: reserved, do not use this configuration.
                                                 @ Note: 11: noninverted/both edges
                                                 @ Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,
                                                 @ external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This
                                                 @ configuration must not be used for encoder mode.
.EQU  TIM10T11A13T14_CCER_CC1E      , 1 << 0     @ Bit 0 CC1E: Capture/Compare 1 output enable.
                                                 @ CC1 channel configured as output:
                                                 @ 0: Off - OC1 is not active.
                                                 @ 1: On - OC1 signal is output on the corresponding output pin.
                                                 @ CC1 channel configured as input:
                                                 @ This bit determines if a capture of the counter value can actually be done into the input
                                                 @ capture/compare register 1 (TIMx_CCR1) or not.
                                                 @ 0: Capture disabled.
                                                 @ 1: Capture enabled.
@.end

@.ITEM     TIM11_OR
.EQU  TIM11_OR_TI1_RMP_N , 0          @  TIM11 Input 1 remapping capability
.EQU  TIM11_OR_TI1_RMP_GPIO_0, 0      @ Channel1 is connected to the GPIO
.EQU  TIM11_OR_TI1_RMP_GPIO_1, 1      @ Channel1 is connected to the GPIO
.EQU  TIM11_OR_TI1_RMP_HSE_RTC, 2     @ HSE_RTC clock (HSE divided by programmable prescaler) is connected to the TIM11_CH1 input for measurement purposes
.EQU  TIM11_OR_TI1_RMP_GPIO_3, 3      @ Channel1 is connected to the GPIO
@.end


