@GNU AS
@.CharSet=CP1251 (Cyrillic)

@.desc type=module
@ +------------------------------------------------------------------+
@ |          Определения Instrumentation Trace Macrocell             |
@ |                            CORTEX-M4                             |
@ +------------------------------------------------------------------+
@.enddesc

.include    "/src/inc/base.inc"

@.item ITM_BASE
.equ ITM_PORT , 0x000 @ (W)  ITM Stimulus Port Registers
.equ ITM_TER  , 0xE00 @ (R/W)  ITM Trace Enable Register
.equ ITM_TPR  , 0xE40 @ (R/W)  ITM Trace Privilege Register
.equ ITM_TCR  , 0xE80 @ (R/W)  ITM Trace Control Register
.equ ITM_IWR  , 0xEF8 @ (W)  ITM Integration Write Register
.equ ITM_IRR  , 0xEFC @ (R)  ITM Integration Read Register
.equ ITM_IMCR , 0xF00 @ (R/W)  ITM Integration Mode Control Register
.equ ITM_LAR  , 0xFB0 @ (W)  ITM Lock Access Register
.equ ITM_LSR  , 0xFB4 @ (R)  ITM Lock Status Register
.equ ITM_PID4 , 0xFD0 @ (R)  ITM Peripheral Identification Register #4
.equ ITM_PID5 , 0xFD4 @ (R)  ITM Peripheral Identification Register #5
.equ ITM_PID6 , 0xFD8 @ (R)  ITM Peripheral Identification Register #6
.equ ITM_PID7 , 0xFDC @ (R)  ITM Peripheral Identification Register #7
.equ ITM_PID0 , 0xFE0 @ (R)  ITM Peripheral Identification Register #0
.equ ITM_PID1 , 0xFE4 @ (R)  ITM Peripheral Identification Register #1
.equ ITM_PID2 , 0xFE8 @ (R)  ITM Peripheral Identification Register #2
.equ ITM_PID3 , 0xFEC @ (R)  ITM Peripheral Identification Register #3
.equ ITM_CID0 , 0xFF0 @ (R)  ITM Component  Identification Register #0
.equ ITM_CID1 , 0xFF4 @ (R)  ITM Component  Identification Register #1
.equ ITM_CID2 , 0xFF8 @ (R)  ITM Component  Identification Register #2
.equ ITM_CID3 , 0xFFC @ (R)  ITM Component  Identification Register #3
@.end

@.item ITM_TPR
.equ ITM_TPR_PRIVMASK_N       , 0
.equ ITM_TPR_PRIVMASK_M       , 0xF << ITM_TPR_PRIVMASK_N
.equ ITM_TPR_PRIVMASK_SP_7_0  , 0x1 << ITM_TPR_PRIVMASK_N   @ stimulus ports [7:0]
.equ ITM_TPR_PRIVMASK_SP_15_8 , 0x2 << ITM_TPR_PRIVMASK_N   @ stimulus ports [15:8]
.equ ITM_TPR_PRIVMASK_SP_23_16, 0x4 << ITM_TPR_PRIVMASK_N   @ stimulus ports [23:16]
.equ ITM_TPR_PRIVMASK_SP_31_24, 0x8 << ITM_TPR_PRIVMASK_N   @ stimulus ports [31:24]
@.end

@.item ITM_TCR
.equ ITM_TCR_BUSY_N           , 23
.equ ITM_TCR_BUSY             , 1 << ITM_TCR_BUSY_N
.equ ITM_TCR_TraceBusID_N     , 16
.equ ITM_TCR_TraceBusID_M     , 0x7F << ITM_TCR_TraceBusID_N
.equ ITM_TCR_GTSFREQ_N        , 10
.equ ITM_TCR_GTSFREQ_M        , 3 << ITM_TCR_GTSFREQ_N
.equ ITM_TCR_TSPrescale_N     , 8
.equ ITM_TCR_TSPrescale_M     , 3 << ITM_TCR_TSPrescale_N
.equ ITM_TCR_SWOENA_N         , 4
.equ ITM_TCR_SWOENA           , 1 << ITM_TCR_SWOENA_N
.equ ITM_TCR_DWTENA_N         , 3
.equ ITM_TCR_DWTENA           , 1 << ITM_TCR_DWTENA_N
.equ ITM_TCR_SYNCENA_N        , 2
.equ ITM_TCR_SYNCENA          , 1 << ITM_TCR_SYNCENA_N
.equ ITM_TCR_TSENA_N          , 1
.equ ITM_TCR_TSENA            , 1 << ITM_TCR_TSENA_N
.equ ITM_TCR_ITMENA_N         , 0
.equ ITM_TCR_ITMENA           , 1 << ITM_TCR_ITMENA_N
@.end


@.item ITM_IWR
.equ ITM_IWR_ATVALIDM_N       , 0
.equ ITM_IWR_ATVALIDM         , 1 << ITM_IWR_ATVALIDM_N
@.end


@.item ITM_IRR
.equ ITM_IRR_ATREADYM_N       , 0
.equ ITM_IRR_ATREADYM         , 1 << ITM_IRR_ATREADYM_N
@.end


@.item ITM_IMCR
.equ ITM_IMCR_INTEGRATION_N   , 0
.equ ITM_IMCR_INTEGRATION     , 1 << ITM_IMCR_INTEGRATION_N
@.end

@.item ITM_LSR
.equ ITM_LSR_ByteAcc_N        , 2
.equ ITM_LSR_ByteAcc          , 1 << ITM_LSR_ByteAcc_N
.equ ITM_LSR_Access_N         , 1
.equ ITM_LSR_Access           , 1 << ITM_LSR_Access_N
.equ ITM_LSR_Present_N        , 0
.equ ITM_LSR_Present          , 1 << ITM_LSR_Present_N
@.end




