@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.INCLUDE   "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  TIM12_BASE     , APB1PERIPH_BASE + 0x1800
.EQU  TIM12          , PERIPH_BASE + TIM12_BASE

@.ITEM     TIM12 TIM12_BASE
.EQU  TIM12_CR1      , 0x00                        @ TIM12 control register 1 (TIMx_CR1)
.EQU  TIM12_CR2      , 0x04                        @ TIM12 control register 2 (TIMx_CR2)
.EQU  TIM12_SMCR     , 0x08                        @ TIM12 slave mode control register (TIM12_SMCR)
.EQU  TIM12_DIER     , 0X0C                        @ TIM12 DMA/interrupt enable register (TIMx_DIER)
.EQU  TIM12_SR       , 0X10                        @ TIM12 status register (TIMx_SR)
.EQU  TIM12_EGR      , 0X14                        @ TIM12 event generation register (TIMx_EGR)
.EQU  TIM12_CCMR1    , 0X18                        @ TIM12 capture/compare mode register 1 (TIMx_CCMR1)
.EQU  TIM12_CCER     , 0X20                        @ TIM12 capture/compare enable register (TIMx_CCER)
.EQU  TIM12_CNT      , 0X24                        @ TIM12 counter ( TIMx_CNT)
.EQU  TIM12_PSC      , 0X28                        @ TIM12 prescaler ( TIMx_PSC)
.EQU  TIM12_ARR      , 0X2C                        @ TIM12 auto-reload register (TIMx_ARR)
.EQU  TIM12_CCR1     , 0X34                        @ TIM12 capture/compare register 1 (TIMx_CCR1)
.EQU  TIM12_CCR2     , 0X38                        @ TIM12 c apture/compare register 2 (TIM12_CCR2)


@.ITEM     TIM12_CR1
.EQU  TIM12_CR1_CKD_N, 8                           @ Bits 9:8 CKD[1:0]: Clock division
.EQU  TIM12_CR1_CKD_1TCK, 0                        @ 00: tDTS=tCK_INT
.EQU  TIM12_CR1_CKD_2TCK, 1 << 8                   @ 01: tDTS=2*tCK_INT
.EQU  TIM12_CR1_CKD_4TCK, 2 << 8                   @ 10: tDTS=4*tCK_INT
.EQU  TIM12_CR1_APRE , 1 << 7                      @ Bit 7 ARPE: Auto-reload preload enable
.EQU  TIM12_CR1_OPM  , 1 << 3                      @ Bit 3 OPM: One pulse mode
.EQU  TIM12_CR1_URS  , 1 << 2                      @ Bit 2 URS: Update request source
.EQU  TIM12_CR1_UDIS , 1 << 1                      @ Bit 1 UDIS: Update disable
.EQU  TIM12_CR1_CEN  , 1                           @ Bit 0 CEN: Counter enable

@.ITEM     TIM12_CR2
.EQU  TIM12_CR2_MMS_N, 4                           @ Bits 6:4 MMS[2:0]: Master mode selection
.EQU  TIM12_CR2_MMS_RESET, 0                       @ 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
.EQU  TIM12_CR2_MMS_ENABLE, 1 << 4                 @ 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
.EQU  TIM12_CR2_MMS_UPDATE, 2 << 4                 @ 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
.EQU  TIM12_CR2_MMS_COMPPULSE, 3 << 4              @ 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
.EQU  TIM12_CR2_MMS_COMP_OC1REF, 4 << 4            @ 100: Compare - OC1REF signal is used as trigger output (TRGO)
.EQU  TIM12_CR2_MMS_COMP_OC2REF, 5 << 4            @ 101: Compare - OC2REF signal is used as trigger output (TRGO)

@.ITEM     TIM12_SMCR
.EQU  TIM12_SMCR_MSM , 1 << 7                      @ Bit 7 MSM: Master/slave mode
.EQU  TIM12_SMCR_TS_N, 1 << 4                      @ Bits 6:4 TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter.
.EQU  TIM12_SMCR_TS_ITR0, 0                        @ 000: Internal Trigger 0 (ITR0)
.EQU  TIM12_SMCR_TS_ITR1, 1 << 4                   @ 001: Internal Trigger 1 (ITR1)
.EQU  TIM12_SMCR_TS_ITR2, 2 << 4                   @ 010: Internal Trigger 2 (ITR2)
.EQU  TIM12_SMCR_TS_ITR3, 3 << 4                   @ 011: Internal Trigger 3 (ITR3)
.EQU  TIM12_SMCR_TS_TI1F_ED, 4 << 4                @ 100: TI1 Edge Detector (TI1F_ED)
.EQU  TIM12_SMCR_TS_TI1FP1, 5 << 4                 @ 101: Filtered Timer Input 1 (TI1FP1
.EQU  TIM12_SMCR_TS_TI2FP2, 6 << 4                 @ 110: Filtered Timer Input 2 (TI2FP2)
.EQU  TIM12_SMCR_SMS_N, 0                          @ Bits 2:0 SMS: Slave mode selection
.EQU  TIM12_SMCR_SMS_SLD, 0                        @ 000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock
.EQU  TIM12_SMCR_SMS_ENC1, 1                       @ 001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level
.EQU  TIM12_SMCR_SMS_ENC2, 2                       @ 010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
.EQU  TIM12_SMCR_SMS_ENC3, 3                       @ 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
.EQU  TIM12_SMCR_SMS_RST, 4                        @ 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
.EQU  TIM12_SMCR_SMS_GATED, 5                      @ 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
.EQU  TIM12_SMCR_SMS_TRIG, 6                       @ 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
.EQU  TIM12_SMCR_SMS_EXTCLK, 7                     @ 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

@.ITEM     TIM12_DIER
.EQU  TIM12_DIER_TIE , 1 << 6                      @ Bit 6 TIE: Trigger interrupt enable
.EQU  TIM12_DIER_CC2IE, 1 << 2                     @ Bit 2 CC2IE: Capture/Compare 2 interrupt enable
.EQU  TIM12_DIER_CC1IE, 1 << 1                     @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
.EQU  TIM12_DIER_UIE , 1 << 0                      @ Bit 0 UIE: Update interrupt enable

@.ITEM     TIM12_SR
.EQU  TIM12_SR_CC2OF , 1 << 10                     @ Bit 10 CC2OF: Capture/Compare 2 overcapture flag
.EQU  TIM12_SR_CC1OF , 1 << 9                      @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
.EQU  TIM12_SR_TIF   , 1 << 6                      @ Bit 6 TIF: Trigger interrupt flag
.EQU  TIM12_SR_CC2IF , 1 << 2                      @ Bit 2 CC2IF: Capture/Compare 2 interrupt flag
.EQU  TIM12_SR_CC1IF , 1 << 1                      @ Bit 1 CC1IF: Capture/Compare 1 interrupt flag
.EQU  TIM12_SR_UIF   , 1 << 0                      @ Bit 0 UIF: Update interrupt flag

@.ITEM     TIM12_EGR
.EQU  TIM12_EGR_TG   , 1 << 6                      @ Bit 6 TG: Trigger generation
.EQU  TIM12_EGR_CC2G , 1 << 2                      @ Bit 2 CC2G: Capture/Compare 2 generation
.EQU  TIM12_EGR_CC1G , 1 << 1                      @ Bit 1 CC1G: Capture/Compare 1 generation
.EQU  TIM12_EGR_UG   , 1 << 0                      @ Bit 0 UG: Update generation

@.ITEM     TIM12_CCMR1
.EQU  TIM12_CCMR1_OCxM_FROZ, 0                     @ 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
.EQU  TIM12_CCMR1_OCxM_SETCH1, 1                   @ 001: Set channel to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM12_CCMR1_OCxM_RSTCH1, 2                   @ 010: Set channel to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM12_CCMR1_OCxM_TGLCH1, 3                   @ 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
.EQU  TIM12_CCMR1_OCxM_FORCELOW, 4                 @ 100: Force inactive level - OC1REF is forced low
.EQU  TIM12_CCMR1_OCxM_FORCEHIGH, 5                @ 101: Force active level - OC1REF is forced high
.EQU  TIM12_CCMR1_OCxM_PWM1, 6                     @ 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
.EQU  TIM12_CCMR1_OCxM_PWM2, 7                     @ 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1  else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.
.EQU  TIM12_CCMR1_OC2M_N, 12                       @ Bits 14:12 OC2M[2:0]: Output Compare 2 mode
.EQU  TIM12_CCMR1_OC2PE, 1 << 11                   @ Bit 11 OC2PE: Output Compare 2 preload enable
.EQU  TIM12_CCMR1_OC2FE, 1 << 10                   @ Bit 10 OC2FE: Output Compare 2 fast enable
.EQU  TIM12_CCMR1_CC2S_N, 8                        @ Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input
.EQU  TIM12_CCMR1_CC2S_CC2OUT, 0                   @ 00: CC2 channel is configured as output
.EQU  TIM12_CCMR1_CC2S_IC2_TO_TI2, 1 << 8          @ 01: CC2 channel is configured as input, IC2 is mapped on TI2
.EQU  TIM12_CCMR1_CC2S_IC2_TO_TI1, 2 << 8          @ 10: CC2 channel is configured as input, IC2 is mapped on TI1
.EQU  TIM12_CCMR1_CC2S_IC2_TO_TRC, 3 << 8          @ 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
.EQU  TIM12_CCMR1_OC1M_N, 4                        @ Bits 6:4 OC1M: Output Compare 1 mode
.EQU  TIM12_CCMR1_OC1PE, 1 << 3                    @ Bit 3 OC1PE: Output Compare 1 preload enable
.EQU  TIM12_CCMR1_OC1FE, 1 << 2                    @ Bit 2 OC1FE: Output Compare 1 fast enable
.EQU  TIM12_CCMR1_CC1S_N, 0                        @ Bits 1:0 CC1S: Capture/Compare 1 selection
.EQU  TIM12_CCMR1_CC1S_CC1OUT, 0                   @ 00: CC1 channel is configured as output
.EQU  TIM12_CCMR1_CC1S_IC1_TO_TI1, 1               @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM12_CCMR1_CC1S_IC1_TO_TI2, 2               @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM12_CCMR1_CC1S_IC1_TO_TRC, 3               @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
.EQU  TIM12_CCMR1_IC2F_N, 12                       @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
.EQU  TIM12_CCMR1_ICxF_OFCKLT, 0                   @ 0000: No filter, sampling is done at fDTS
.EQU  TIM12_CCMR1_ICxF_CKN2, 1                     @ 0001: fSAMPLING=fCK_INT, N=2
.EQU  TIM12_CCMR1_ICxF_CKN4, 2                     @ 0010: fSAMPLING=fCK_INT, N=4
.EQU  TIM12_CCMR1_ICxF_CKN8, 3                     @ 0011: fSAMPLING=fCK_INT, N=8
.EQU  TIM12_CCMR1_ICxF_TS2N6, 4                    @ 0100: fSAMPLING=fDTS/2, N=6
.EQU  TIM12_CCMR1_ICxF_TS2N8, 5                    @ 0101: fSAMPLING=fDTS/2, N=8
.EQU  TIM12_CCMR1_ICxF_TS4N6, 6                    @ 0110: fSAMPLING=fDTS/4, N=6
.EQU  TIM12_CCMR1_ICxF_TS4N8, 7                    @ 0111: fSAMPLING=fDTS/4, N=8
.EQU  TIM12_CCMR1_ICxF_TS8N6, 8                    @ 1000: fSAMPLING=fDTS/8, N=6
.EQU  TIM12_CCMR1_ICxF_TS8N8, 9                    @ 1001: fSAMPLING=fDTS/8, N=8
.EQU  TIM12_CCMR1_ICxF_TS16N5, 10                  @ 1010: fSAMPLING=fDTS/16, N=5
.EQU  TIM12_CCMR1_ICxF_TS16N6, 11                  @ 1011: fSAMPLING=fDTS/16, N=6
.EQU  TIM12_CCMR1_ICxF_TS16N8, 12                  @ 1100: fSAMPLING=fDTS/16, N=8
.EQU  TIM12_CCMR1_ICxF_TS32N5, 13                  @ 1101: fSAMPLING=fDTS/32, N=5
.EQU  TIM12_CCMR1_ICxF_TS32N6, 14                  @ 1110: fSAMPLING=fDTS/32, N=6
.EQU  TIM12_CCMR1_ICxF_TS32N8, 15                  @ 1111: fSAMPLING=fDTS/32, N=8
.EQU  TIM12_CCMR1_IC2PSC_N, 10                     @ Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
.EQU  TIM12_CCMR1_ICxPSC_1, 0                      @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM12_CCMR1_ICxPSC_2, 1                      @ 01: capture is done once every 2 events
.EQU  TIM12_CCMR1_ICxPSC_4, 2                      @ 10: capture is done once every 4 events
.EQU  TIM12_CCMR1_ICxPSC_8, 3                      @ 11: capture is done once every 8 events
.EQU  TIM12_CCMR1_IÑ1F_N, 4                        @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
.EQU  TIM12_CCMR1_IC1PSC_N, 2                      @ Bits 3:2 IC1PSC: Input capture 1 prescaler

@.ITEM     TIM12_CCER
.EQU  TIM12_CCER_CC2NP, 1 << 7                     @ Bit 7 CC2NP: Capture/Compare 2 complementary output polarity
.EQU  TIM12_CCER_CC2P, 1 << 5                      @ Bit 5 CC2P: Capture/Compare 2 output polarity
.EQU  TIM12_CCER_CC2E, 1 << 4                      @ Bit 4 CC2E: Capture/Compare 2 output enable
.EQU  TIM12_CCER_CC1NP, 1 << 3                     @ Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
.EQU  TIM12_CCER_CC1P, 1 << 1                      @ Bit 1 CC1P: Capture/Compare 1 output polarity
.EQU  TIM12_CCER_CC1E, 1 << 0                      @ Bit 0 CC1E: Capture/Compare 1 output enable



