@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  IWDG_BASE      , APB1PERIPH_BASE + 0x3000
.EQU  IWDG           , PERIPH_BASE + IWDG_BASE

@.ITEM     IWDG IWDG_BASE
.EQU  IWDG_KR        , 0x00                        @ Key register (IWDG_KR)
.EQU  IWDG_PR        , 0x04                        @ Prescaler register (IWDG_PR)
.EQU  IWDG_RLR       , 0x08                        @ Reload register (IWDG_RLR)
.EQU  IWDG_SR        , 0X0C                        @ Status register (IWDG_SR)

@.ITEM IWDG_PR
.EQU  IWDG_PR_PR_N   , 0                           @ Bits 2:0 PR[2:0]: Prescaler divider
.EQU  IWDG_PR_PR_DIV4, 0
.EQU  IWDG_PR_PR_DIV8, 1
.EQU  IWDG_PR_PR_DIV16, 2
.EQU  IWDG_PR_PR_DIV32, 3
.EQU  IWDG_PR_PR_DIV64, 4
.EQU  IWDG_PR_PR_DIV128, 5
.EQU  IWDG_PR_PR_DIV256, 6
.EQU  IWDG_PR_PR_DIV256, 7

@.ITEM IWDG_RLR
.EQU  IWDG_RLR_RL_RSTVAL, 0x0FFF                   @ Reset value: 0x0000 0FFF (reset by Standby mode)

@.ITEM IWDG_SR
.EQU  IWDG_SR_RVU    , 1 << 1                      @ Bit 1 RVU: Watchdog counter reload value update
.EQU  IWDG_SR_PVU    , 1                           @ Bit 0 PVU: Watchdog prescaler value update



