@GNU AS
@.CharSet=CP1251 (Cyrillic)

@.desc type=module
@ +------------------------------------------------------------------+
@ |                Определения Floating point unit                   |
@ |                            CORTEX-M4                             |
@ +------------------------------------------------------------------+
@.enddesc

.include    "/src/inc/base.inc"

@.item FPU_BASE
.equ FPU_FPCCR      , 0x004 @ (R/W)  Floating-Point Context Control Register
.equ FPU_FPCAR      , 0x008 @ (R/W)  Floating-Point Context Address Register
.equ FPU_FPDSCR     , 0x00C @ (R/W)  Floating-Point Default Status Control Register
.equ FPU_MVFR0      , 0x010 @ (R)  Media and FP Feature Register 0
.equ FPU_MVFR1      , 0x014 @ (R)  Media and FP Feature Register 1
@.end


@.item FPU_FPCCR
.equ FPU_FPCCR_ResetValue, 0xC0000000                 @ Значение после сброса
.equ FPU_FPCCR_ASPEN_N   , 31
.equ FPU_FPCCR_ASPEN     , 1 << FPU_FPCCR_ASPEN_N     @ ASPEN: Enables CONTROL<2> setting on execution of a floating-point instruction.
                                                      @ 0: Disable CONTROL<2> setting on execution of a floating-point instruction.
                                                      @ 1: Enable CONTROL<2> setting on execution of a floating-point instruction.
.equ FPU_FPCCR_LSPEN_N   , 30
.equ FPU_FPCCR_LSPEN     , 1 << FPU_FPCCR_LSPEN_N     @ 0: Disable automatic lazy state preservation for floating-point context.
                                                      @ 1: Enable automatic lazy state preservation for floating-point context.
.equ FPU_FPCCR_MONRDY_N  , 8
.equ FPU_FPCCR_MONRDY    , 1 << FPU_FPCCR_MONRDY_N    @ 0: DebugMonitor is disabled or priority did not permit setting MON_PEND when the floatingpoint stack frame was allocated.
                                                      @ 1: DebugMonitor is enabled and priority permits setting MON_PEND when  the floating-point stack frame was allocated.
.equ FPU_FPCCR_BFRDY_N   , 6
.equ FPU_FPCCR_BFRDY     , 1 << FPU_FPCCR_BFRDY_N     @ 0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
                                                      @ 1: BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
.equ FPU_FPCCR_MMRDY_N   , 5
.equ FPU_FPCCR_MMRDY     , 1 << FPU_FPCCR_MMRDY_N     @ 0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
                                                      @ 1: MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
.equ FPU_FPCCR_HFRDY_N   , 4
.equ FPU_FPCCR_HFRDY     , 1 << FPU_FPCCR_HFRDY_N     @ 0: Priority did not permit setting the HardFault handler to the pending state when the floatingpoint stack frame was allocated.
                                                      @ 1: Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
.equ FPU_FPCCR_THREAD_N  , 3
.equ FPU_FPCCR_THREAD    , 1 << FPU_FPCCR_THREAD_N    @ 0: Mode was not Thread Mode when the floating-point stack frame was allocated.
                                                      @ 1: Mode was Thread Mode when the floating-point stack frame was allocated.
.equ FPU_FPCCR_USER_N    , 1
.equ FPU_FPCCR_USER      , 1 << FPU_FPCCR_USER_N      @ 0: Privilege level was not user when the floating-point stack frame was allocated.
                                                      @ 1: Privilege level was user when the floating-point stack frame was allocated.
.equ FPU_FPCCR_LSPACT_N  , 0
.equ FPU_FPCCR_LSPACT    , 1 << FPU_FPCCR_LSPACT_N    @ 0: Lazy state preservation is not active.
                                                      @ 1: Lazy state preservation is active. floating-point stack frame is allocated but saving state to it is deferred.
@.end


@.item FPU_FPCAR
.equ FPU_FPCAR_ADDRESS_N , 3
.equ FPU_FPCAR_ADDRESS_M , 0x1FFFFFFF << FPU_FPCAR_ADDRESS_N     @ Location of unpopulated floating-point register space allocated on an exception stack frame.
@.end


@.item FPU_FPDSCR
.equ FPU_FPDSCR_ResetValue, 0                        @ Значение после сброса
.equ FPU_FPDSCR_AHP_N    , 26
.equ FPU_FPDSCR_AHP      , 1 << FPU_FPDSCR_AHP_N     @ Default value for FPSCR.AHP Alternative half-precision control bit:
                                                     @    0: IEEE half-precision format selected.
                                                     @    1: Alternative half-precision format selected.
.equ FPU_FPDSCR_DN_N     , 25
.equ FPU_FPDSCR_DN       , 1 << FPU_FPDSCR_DN_N      @ Default value for FPSCR.DN Default NaN mode control bit:
                                                     @   0: NaN operands propagate through to the output of a floating-point operation.
                                                     @   1: Any operation involving one or more NaNs returns the Default NaN.
.equ FPU_FPDSCR_FZ_N     , 24
.equ FPU_FPDSCR_FZ       , 1 << FPU_FPDSCR_FZ_N      @ Default value for FPSCR.FZ Flush-to-zero mode control bit:
                                                     @ 0: Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
                                                     @ 1: Flush-to-zero mode enabled.
.equ FPU_FPDSCR_RMode_N  , 22
.equ FPU_FPDSCR_RMode_M  , 3 << FPU_FPDSCR_RMode_N   @ Default value for FPSCR.RMode Rounding Mode control field. The specified rounding mode is used by almost all floating-point instructions:
                                                     @ 0b00: Round to nearest (RN) mode
.equ FPU_FPDSCR_RMode_Plus, 1 << FPU_FPDSCR_RMode_N  @ 0b01: Round towards plus infinity (RP) mode
.equ FPU_FPDSCR_RMode_Minus,2 << FPU_FPDSCR_RMode_N  @ 0b10: Round towards minus infinity (RM) mode
.equ FPU_FPDSCR_RMode_Zero, 3 << FPU_FPDSCR_RMode_N  @ 0b11: Round towards zero (RZ) mode.
@.end


@.item FPU_MVFR0
.equ FPU_MVFR0_FP_rounding_modes_N , 28
.equ FPU_MVFR0_FP_rounding_modes_M , 0xF << FPU_MVFR0_FP_rounding_modes_N
.equ FPU_MVFR0_Short_vectors_N     , 24
.equ FPU_MVFR0_Short_vectors_M     , 0xF << FPU_MVFR0_Short_vectors_N
.equ FPU_MVFR0_Square_root_N       , 20
.equ FPU_MVFR0_Square_root_M       , 0xF << FPU_MVFR0_Square_root_N
.equ FPU_MVFR0_Divide_N            , 16
.equ FPU_MVFR0_Divide_M            , 0xF << FPU_MVFR0_Divide_N
.equ FPU_MVFR0_FP_excep_trapping_N , 12
.equ FPU_MVFR0_FP_excep_trapping_M , 0xF << FPU_MVFR0_FP_excep_trapping_N
.equ FPU_MVFR0_Double_precision_N  , 8
.equ FPU_MVFR0_Double_precision_M  , 0xF << FPU_MVFR0_Double_precision_N
.equ FPU_MVFR0_Single_precision_N  , 4
.equ FPU_MVFR0_Single_precision_M  , 0xF << FPU_MVFR0_Single_precision_N
.equ FPU_MVFR0_A_SIMD_registers_N  , 0
.equ FPU_MVFR0_A_SIMD_registers_M  , 0xF << FPU_MVFR0_A_SIMD_registers_N
@.end


@.item FPU_MVFR1
.equ FPU_MVFR1_FP_fused_MAC_N , 28
.equ FPU_MVFR1_FP_fused_MAC_M , 0xF << FPU_MVFR1_FP_fused_MAC_N
.equ FPU_MVFR1_FP_HPFP_N      , 24
.equ FPU_MVFR1_FP_HPFP_M      , 0xF << FPU_MVFR1_FP_HPFP_N
.equ FPU_MVFR1_D_NaN_mode_N   , 4
.equ FPU_MVFR1_D_NaN_mode_M   , 0xF << FPU_MVFR1_D_NaN_mode_N
.equ FPU_MVFR1_FtZ_mode_N     , 0
.equ FPU_MVFR1_FtZ_mode_M     , 0xF << FPU_MVFR1_FtZ_mode_N
@.end



