@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +-------------------------------------------------------------------+
@ |                                                                   |
@ |   STM32F303   Базовые константы USART и UART   STM32F303          |  
@ |   Universal Synchronous Asynchronous Receiver Transmitter (USART) |
@ |                                                                   |
@ +-------------------------------------------------------------------+
@.ENDDESC

.INCLUDE       "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  USART2_BASE             , APB1PERIPH_BASE + 0x4400
.EQU  USART3_BASE             , APB1PERIPH_BASE + 0x4400
.EQU  UART4_BASE              , APB1PERIPH_BASE + 0x4C00
.EQU  UART5_BASE              , APB1PERIPH_BASE + 0x5000
.EQU  USART2                  , PERIPH_BASE + USART2_BASE
.EQU  USART3                  , PERIPH_BASE + USART3_BASE
.EQU  UART4                   , PERIPH_BASE + UART4_BASE
.EQU  UART5                   , PERIPH_BASE + UART5_BASE
@.END

@.ITEM     APB2PERIPH_BASE
.EQU  USART1_BASE             , APB2PERIPH_BASE + 0x3800
.EQU  USART1                  , PERIPH_BASE + USART1_BASE
@.END

@.ITEM USART1_BASE USART2_BASE USART3_BASE UART4_BASE UART5_BASE USART1 USART2 USART3 UART4 UART5
.EQU  USART_CR1               , 0x00          @ USART Control register 1
.EQU  USART_CR2               , 0x04          @ USART Contro2 register 1
.EQU  USART_CR3               , 0x08          @ USART Contro3 register 1
.EQU  USART_BRR               , 0x0C          @ USART Baud rate register
.EQU  USART_GTPR              , 0x10          @ USART Guard time and prescaler register
.EQU  USART_RTOR              , 0x14          @ USART Receiver Time Out register
.EQU  USART_RQR               , 0x18          @ USART Request register
.EQU  USART_ISR               , 0x1C          @ USART Interrupt and status register
.EQU  USART_ICR               , 0x20          @ USART Interrupt flag Clear register
.EQU  USART_RDR               , 0x24          @ USART Receive Data register
.EQU  RESERVED1               , 0x26          @ Reserved
.EQU  USART_TDR               , 0x28          @ USART Transmit Data register
.EQU  RESERVED2               , 0x2A          @ Reserved
@.END

@ +------------------------------------------------------------------+
@ |                    Bit definition for  USART и UART  register            |
@ +------------------------------------------------------------------+
@.ITEM     USART_CR1
.EQU  USART_CR1_UE_N          , 0             @ Bit 0 UE: USART enable
.EQU  USART_CR1_UE            , 1             @ 1: USART enabled
.EQU  USART_CR1_UESM_N        , 1             @ Bit 1 UESM: USART enable in Stop mode
.EQU  USART_CR1_UESM          , 1 << 1        @ 1: USART able to wake up the MCU from Stop mode.
.EQU  USART_CR1_RE_N          , 2             @ Bit 2 RE: Receiver enable
.EQU  USART_CR1_RE            , 1 << 2        @ 1: Receiver is enabled and begins searching for a start bit
.EQU  USART_CR1_TE_N          , 3             @ Bit 3 TE: Transmitter enable
.EQU  USART_CR1_TE            , 1 << 3        @ 1: Transmitter is enabled
.EQU  USART_CR1_IDLEIE_N      , 4             @ Bit 4 IDLEIE: IDLE interrupt enable
.EQU  USART_CR1_IDLEIE        , 1 << 4        @ IDLE Interrupt Enable
.EQU  USART_CR1_RXNEIE_N      , 5             @ Bit 5 RXNEIE: RXNE interrupt enable
.EQU  USART_CR1_RXNEIE        , 1 << 5        @ 1:RXNE Interrupt Enable
.EQU  USART_CR1_TCIE_N        , 6             @ Bit 6 TCIE: Transmission complete interrupt enable
.EQU  USART_CR1_TCIE          , 1 << 6        @1: A USART interrupt is generated whenever TC=1 in the USART_ISR register
.EQU  USART_CR1_TXEIE_N       , 7             @ Bit 7 TXEIE: interrupt enable
.EQU  USART_CR1_TXEIE         , 1 << 7        @ 1: A USART interrupt is generated whenever TXE=1 in the USART_ISR register
.EQU  USART_CR1_PEIE_N        , 8
.EQU  USART_CR1_PEIE          , 1 << 8        @ PE Interrupt Enable
.EQU  USART_CR1_PS_N          , 9             @ Bit 9 PS: Parity selection
.EQU  USART_CR1_PS            , 1 << 9        @ Parity Selection
.EQU  USART_CR1_PCE_N         , 10            @ Bit 10 PCE: Parity control enable
.EQU  USART_CR1_PCE           , 1 << 10       @ Parity Control Enable
.EQU  USART_CR1_WAKE_N        , 11            @ Bit 11 WAKE: Receiver wakeup method
.EQU  USART_CR1_WAKE          , 1 << 11       @ 1: Address mark
.EQU  USART_CR1_M1_N          , 28            @ Bit 28 M1: Word length
.EQU  USART_CR1_M0_N          , 12            @ This bit, with bit 28 (M1), determines the word length
.EQU  USART_CR1_M1            , 1 << 28       @ 1: Word length
.EQU  USART_CR1_M0            , 1 << 12       @ 1: Word length
.EQU  USART_CR1_MME_N         , 13            @ Bit 13 MME: Mute mode enable
.EQU  USART_CR1_MME           , 1 << 13       @ 1: Mute Mode Enable * /
.EQU  USART_CR1_CMIE_N        , 14            @ Bit 14 CMIE: Character match interrupt enable
.EQU  USART_CR1_CMIE          , 1 << 14       @ 1: Character match interrupt enable * /
.EQU  USART_CR1_OVER8_N       , 15            @ Bit 15 OVER8: Oversampling mode
.EQU  USART_CR1_OVER8         , 1 << 15       @ 1: Oversampling by 8 - bit or 16 - bit mode * /
.EQU  USART_CR1_DEDT_N        , 16            @ Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time              @
.EQU  USART_CR1_DEDT          , 1 << 16       @ 1: DEDT [ 4 : 0 ] bits ( Driver Enable Deassertion Time ) * /
.EQU  USART_CR1_DEDT_0        , 0x01 << 16
.EQU  USART_CR1_DEDT_1        , 0x02 << 16
.EQU  USART_CR1_DEDT_2        , 0x04 << 16
.EQU  USART_CR1_DEDT_3        , 0x08 << 16
.EQU  USART_CR1_DEDT_4        , 0x10 << 16
.EQU  USART_CR1_DEAT_N        , 21            @ Bits 25:21 DEAT[4:0]: Driver Enable assertion time
.EQU  USART_CR1_DEAT_M        , 0x1F << 21    @
.EQU  USART_CR1_DEAT_0        , 0x01 << 21    @
.EQU  USART_CR1_DEAT_1        , 0x02 << 21    @
.EQU  USART_CR1_DEAT_2        , 0x04 << 21    @
.EQU  USART_CR1_DEAT_3        , 0x08 << 21    @
.EQU  USART_CR1_DEAT_4        , 0x10 << 21    @
.EQU  USART_CR1_RTOIE_N       , 26            @ Bit 26 RTOIE: Receiver timeout interrupt enable
.EQU  USART_CR1_RTOIE         , 1 << 26       @ 1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.
.EQU  USART_CR1_EOBIE_N       , 27            @ Bit 27 EOBIE: End of Block interrupt enable
.EQU  USART_CR1_EOBIE         , 1 << 26       @ 1: 1: A USART interrupt is generated when the EOBF flag is set in the USART_ISR register
@.END

@.ITEM     USART_CR2
.EQU  USART_CR2_ADDM7_N       , 4             @ Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
.EQU  USART_CR2_ADDM7         , 1 << 4
.EQU  USART_CR2_LBDL_N        , 5             @ Bit 5 LBDL: LIN break detection length
.EQU  USART_CR2_LBDL          , 1 << 5        @ 1: 11-bit break detection
.EQU  USART_CR2_LBDIE_N       , 6             @ Bit 6 LBDIE: LIN break detection interrupt enable
.EQU  USART_CR2_LBDIE         , 1 << 6        @ 1: An interrupt is generated whenever LBDF=1 in the USART_ISR register
.EQU  USART_CR2_LBCL_N        , 8             @ Bit 8 LBCL: Last bit clock pulse
.EQU  USART_CR2_LBCL          , 1 << 8        @ 1: The clock pulse of the last data bit is output to the CK pin
.EQU  USART_CR2_CPHA_N        , 9             @ Bit 9 CPHA: Clock phase
.EQU  USART_CR2_CPHA          , 1 << 9        @ 1: The second clock transition is the first data capture edge
.EQU  USART_CR2_CPOL_N        , 10            @ Bit 10 CPOL: Clock polarity
.EQU  USART_CR2_CPOL          , 1 << 10       @ 1: Steady high value on CK pin outside transmission window
.EQU  USART_CR2_CLKEN_N       , 11            @ Bit 11 CLKEN: Clock enable
.EQU  USART_CR2_CLKEN         , 1 << 11       @ 1: CK pin enabled
.EQU  USART_CR2_STOP_N        , 12            @  Bits 13:12 STOP[1:0]: STOP bits
.EQU  USART_CR2_STOP_00       , 0x00 << 12    @ 00: 1 stop bit
.EQU  USART_CR2_STOP_01       , 0x01 << 12    @ 01: 0.5 stop bit
.EQU  USART_CR2_STOP_10       , 0x10 << 12    @ 10: 2 stop bits
.EQU  USART_CR2_STOP_11       , 0x10 << 12    @ 11: 1.5 stop bits
.EQU  USART_CR2_LINEN_N       , 14            @ Bit 14 LINEN: LIN mode enable
.EQU  USART_CR2_LINEN         , 1 << 14       @ 1: LIN mode enabled
.EQU  USART_CR2_SWAP_N        , 15            @ Bit 15 SWAP: Swap TX/RX pins
.EQU  USART_CR2_SWAP          , 1 << 15       @ 1: The TX and RX pins functions are swapped.
.EQU  USART_CR2_RXINV_N       , 16            @ Bit 16 RXINV: RX pin active level inversion
.EQU  USART_CR2_RXINV         , 1 << 16       @ 1: RX pin signal values are inverted.
.EQU  USART_CR2_TXINV_N       , 17            @ Bit 17 TXINV: TX pin active level inversion
.EQU  USART_CR2_TXINV         , 1 << 17       @ 1: TX pin signal values are inverted.
.EQU  USART_CR2_DATAINV_N     , 18            @ Bit 18 DATAINV: Binary data inversion
.EQU  USART_CR2_DATAINV       , 1 << 18       @ 1: Logical data from the data register are send/received in negative/inverse logic
.EQU  USART_CR2_MSBFIRST_N    , 19            @ Bit 19 MSBFIRST: Most significant bit first
.EQU  USART_CR2_MSBFIRST      , 1 << 19       @ 1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit.
.EQU  USART_CR2_ABREN_N       , 20            @ Bit 20 ABREN: Auto baud rate enable
.EQU  USART_CR2_ABREN         , 1 << 20       @ 1: Auto baud rate detection is enabled
.EQU  USART_CR2_ABRMODE_N     , 21            @ Bits 22:21 ABRMOD[1:0]: Auto baud rate mode
.EQU  USART_CR2_ABRMODE_00    , 0x00 << 21    @ 00: Measurement of the start bit is used to detect the baud rate.
.EQU  USART_CR2_ABRMODE_01    , 0x01 << 21    @ 01: Falling edge to falling edge measurement.
.EQU  USART_CR2_ABRMODE_10    , 0x02 << 21    @ 10: 0x7F frame detection.
.EQU  USART_CR2_ABRMODE_11    , 0x03 << 21    @ 11: 0x55 frame detection
.EQU  USART_CR2_RTOEN_N       , 23            @ Bit 23 RTOEN: Receiver timeout enable
.EQU  USART_CR2_RTOEN         , 0x01 << 23    @ 1: Receiver timeout feature enabled.
.EQU  USART_CR2_ADD_N         , 24            @ Bits 27:24 ADD[3:0]: Address of the USART node
@.END

@.ITEM     USART_CR3
.EQU  USART_CR3_EIE_N         , 0             @ Bit 0 EIE: Error interrupt enable
.EQU  USART_CR3_EIE           , 1 << 0        @ 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USART_ISR register.                      /*!< Error Interrupt Enable */
.EQU  USART_CR3_IREN_N        , 1             @ Bit 1 IREN: IrDA mode enable
.EQU  USART_CR3_IREN          , 1 << 1        @ 1: IrDA enabled                           /*!< IrDA mode Enable */
.EQU  USART_CR3_IRLP_N        , 2             @ Bit 2 IRLP: IrDA low-power
.EQU  USART_CR3_IRLP          , 1 << 2        @ 1: Low-power mode
.EQU  USART_CR3_HDSEL_N       , 3             @ Bit 3 HDSEL: Half-duplex selection
.EQU  USART_CR3_HDSEL         , 1 << 3        @ 1: Half duplex mode is selected
.EQU  USART_CR3_NACK_N        , 4             @ Bit 4 NACK: Smartcard NACK enable
.EQU  USART_CR3_NACK          , 1 << 4        @ 1: NACK transmission during parity error is enabled
.EQU  USART_CR3_SCEN_N        , 5             @ Bit 5 SCEN: Smartcard mode enable
.EQU  USART_CR3_SCEN          , 1 << 5        @ 1: Smartcard Mode enabled
.EQU  USART_CR3_DMAR_N        , 6             @ Bit 6 DMAR: DMA enable receiver
.EQU  USART_CR3_DMAR          , 1 << 6        @ 1: DMA mode is enabled for reception
.EQU  USART_CR3_DMAT_N        , 7             @ Bit 7 DMAT: DMA enable transmitter
.EQU  USART_CR3_DMAT          , 1 << 7        @ 1: DMA mode is enabled for transmission
.EQU  USART_CR3_RTSE_N        , 8             @ Bit 8 RTSE: RTS enable
.EQU  USART_CR3_RTSE          , 1 << 8        @ 1: RTS output enabled, data is only requested when there is space in the receive buffer
.EQU  USART_CR3_CTSE_N        , 9             @ Bit 9 CTSE: CTS enable
.EQU  USART_CR3_CTSE          , 1 << 9        @ 1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0).
.EQU  USART_CR3_CTSIE_N       , 10            @ Bit 10 CTSIE: CTS interrupt enable
.EQU  USART_CR3_CTSIE         , 1 << 10       @ 1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
.EQU  USART_CR3_ONEBIT_N      , 11            @ Bit 11 ONEBIT: One sample bit method enable
.EQU  USART_CR3_ONEBIT        , 1 << 11       @ 1: One sample bit method
.EQU  USART_CR3_OVRDIS_N      , 12            @ Bit 12 OVRDIS: Overrun Disable
.EQU  USART_CR3_OVRDIS        , 1 << 12       @ 1: Overrun functionality is disabled
.EQU  USART_CR3_DDRE_N        , 13            @ Bit 13 DDRE: DMA Disable on Reception Error
.EQU  USART_CR3_DDRE          , 1 << 13       @ 1: DMA is disabled following a reception error
.EQU  USART_CR3_DEM_N         , 14            @ Bit 14 DEM: Driver enable mode
.EQU  USART_CR3_DEM           , 1 << 14       @ 1: DE function is enabled. The DE signal is output on the RTS pin.
.EQU  USART_CR3_DEP_N         , 15            @ Bit 15 DEP: Driver enable polarity selection
.EQU  USART_CR3_DEP           , 1 << 15       @ 1 : DE signal is active low
.EQU  USART_CR3_SCARCNT_N     , 17            @ Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count
.EQU  USART_CR3_SCARCNT_M     , 0x7 << 17     @ x1 to 0x7: number of automatic retransmission attempts
.EQU  USART_CR3_SCARCNT_0     , 0x1 << 17
.EQU  USART_CR3_SCARCNT_1     , 0x2 << 17
.EQU  USART_CR3_SCARCNT_2     , 0x4 << 17
.EQU  USART_CR3_WUS_N         , 20            @ Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection
.EQU  USART_CR3_WUS_0         , 0 << 20       @ 00: WUF active on address match (
.EQU  USART_CR3_WUS_1         , 1 << 20       @ 01:Reserved.
.EQU  USART_CR3_WUS_2         , 2 << 20       @ 10: WuF active on Start bit detection
.EQU  USART_CR3_WUS_3         , 3 << 20       @ 11: WUF active on RXNE
.EQU  USART_CR3_WUFIE_N       , 22            @ Bit 22 WUFIE: Wakeup from Stop mode interrupt enable
.EQU  USART_CR3_WUFIE         , 1 << 22       @ 1: An USART interrupt is generated whenever WUF=1 in the USART_ISR register
@.END

@.ITEM     USART_BRR
.EQU  USART_BRR_DIV_FRACTION_N, 0             @ @ Bits 3:0 BRR[3:0]
.EQU  USART_BRR_DIV_FRACTION_M, 0xF << 0      @
.EQU  USART_BRR_DIV_MANTISSA_N, 4             @  Bits 15:4 BRR[15:4]
.EQU  USART_BRR_DIV_MANTISSA_M, 0xFFF << 4    @
@.END

@.ITEM     USART_GTPR
.EQU  USART_GTPR_PSC_N        , 0             @ Bits 7:0 PSC[7:0]: Prescaler value
.EQU  USART_GTPR_GT_N         , 8             @ Bits 15:8 GT[7:0]: Guard time value
@.END

@.ITEM     USART_RTOR
.EQU  USART_RTOR_RTO_N        , 0             @ Bits 23:0 RTO[23:0]: Receiver timeout value
.EQU  USART_RTOR_BLEN_N       , 24            @ Bits 31:24 BLEN[7:0]: Block Length
@.END

@.ITEM     USART_RQR
.EQU  USART_RQR_ABRRQ_N       , 0             @ Bit 0 ABRRQ: Auto baud rate request
.EQU  USART_RQR_ABRRQ         , 1 << 0        @ Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud
.EQU  USART_RQR_SBKRQ_N       , 1             @ Bit 1 SBKRQ: Send break request
.EQU  USART_RQR_SBKRQ         , 1 << 1        @ Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
.EQU  USART_RQR_MMRQ_N        , 2             @ Bit 2 MMRQ: Mute mode request
.EQU  USART_RQR_MMRQ          , 1 << 2        @ Writing 1 to this bit puts the USART in mute mode and sets the RWU flag.
.EQU  USART_RQR_RXFRQ_N       , 3             @ Bit 3 RXFRQ: Receive data flush request
.EQU  USART_RQR_RXFRQ         , 1 << 3        @ Writing 1 to this bit clears the RXNE flag.
.EQU  USART_RQR_TXFRQ_N       , 4             @ Bit 4 TXFRQ: Transmit data flush request
.EQU  USART_RQR_TXFRQ         , 1 << 4        @ Writing 1 to this bit sets the TXE flag.
@.END

@.ITEM     USART_ISR
.EQU  USART_ISR_PE_N          , 0             @ Bit 0 PE: Parity error.This bit is set by hardware when a parity error
.EQU  USART_ISR_PE            , 1 << 0        @ 1: Parity error
.EQU  USART_ISR_FE_N          , 1             @ Bit 1 FE: Framing error
.EQU  USART_ISR_FE            , 1 << 1        @ 1: Framing error or break character is detected
.EQU  USART_ISR_NE_N          , 2             @ Bit 2 NF: START bit Noise detection flag
.EQU  USART_ISR_NE            , 1 << 2        @ 1: Noise is detected
.EQU  USART_ISR_ORE_N         , 3             @ Bit 3 ORE: Overrun error
.EQU  USART_ISR_ORE           , 1 << 3        @ 1: Overrun error is detected
.EQU  USART_ISR_IDLE_N        , 4             @ Bit 4 IDLE: Idle line detected
.EQU  USART_ISR_IDLE          , 1 << 4        @ 1: Idle line is detected
.EQU  USART_ISR_RXNE_N        , 5             @ Bit 5 RXNE: Read data register not empty
.EQU  USART_ISR_RXNE          , 1 << 5        @ 1: Received data is ready to be read.
.EQU  USART_ISR_TC_N          , 6             @ Bit 6 TC: Transmission complete
.EQU  USART_ISR_TC            , 1 << 6        @ 1: Transmission is complete
.EQU  USART_ISR_TXE_N         , 7             @ Bit 7 TXE: Transmit data register empty
.EQU  USART_ISR_TXE           , 1 << 7        @ 1: data is transferred to the shift register)
.EQU  USART_ISR_LBDF_N        , 8             @ Bit 8 LBDF: LIN break detection flag
.EQU  USART_ISR_LBDF          , 1 << 8        @ 1: LIN break detected
.EQU  USART_ISR_CTSIF_N       , 9             @ Bit 9 CTSIF: CTS interrupt flag
.EQU  USART_ISR_CTSIF         , 1 << 9        @ 1: A change occurred on the CTS status line
.EQU  USART_ISR_CTS_N         , 10            @ Bit 10 CTS: CTS flag
.EQU  USART_ISR_CTS           , 1 << 10       @ 1: CTS line reset
.EQU  USART_ISR_RTOF_N        , 11            @ Bit 11 RTOF: Receiver timeout
.EQU  USART_ISR_RTOF          , 1 << 11       @ 1: Timeout value reached without any data reception
.EQU  USART_ISR_EOBF_N        , 12            @ 12 EOBF: End of block flag
.EQU  USART_ISR_EOBF          , 1 << 12       @ 1: End of Block (number of characters) reached
.EQU  USART_ISR_ABRE_N        , 14            @ Bit 14 ABRE: Auto baud rate error
.EQU  USART_ISR_ABRE          , 1 << 14       @ This bit is set by hardware if the baud rate measurement failed
.EQU  USART_ISR_ABRF_N        , 15            @ Bit 15 ABRF: Auto baud rate flag
.EQU  USART_ISR_ABRF          , 1 << 15       @ This bit is set by hardware when the automatic baud rate has been set
.EQU  USART_ISR_BUSY_N        , 16            @ Bit 16 BUSY: Busy flag
.EQU  USART_ISR_BUSY          , 1 << 16       @ 1: Reception on going
.EQU  USART_ISR_CMF_N         , 17            @ Bit 17 CMF: Character match flag
.EQU  USART_ISR_CMF           , 1 << 17       @ 1: Character Match detected
.EQU  USART_ISR_SBKF_N        , 18            @ Bit 18 SBKF: Send break flag
.EQU  USART_ISR_SBKF          , 1 << 18       @ 1: Break character will be transmitted
.EQU  USART_ISR_RWU_N         , 19            @ Bit 19 RWU: Receiver wakeup from Mute mode
.EQU  USART_ISR_RWU           , 1 << 19       @ 1: Receiver in mute mode
.EQU  USART_ISR_WUF_N         , 20            @ Bit 20 WUF: Wakeup from Stop mode flag
.EQU  USART_ISR_WUF           , 1 << 20       @ This bit is set by hardware, when a wakeup event is detected.
.EQU  USART_ISR_TEACK_N       , 21            @ Bit 21 TEACK: Transmit enable acknowledge flag
.EQU  USART_ISR_TEACK         , 1 << 21       @ This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART.
.EQU  USART_ISR_REACK_N       , 22            @ Bit 22 REACK: Receive enable acknowledge flag
.EQU  USART_ISR_REACK         , 1 << 22       @ This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART.
@.END

@.ITEM     USART_ICR
.EQU  USART_ICR_PECF_N        , 0             @ Bit 0 PECF: Parity error clear flag
.EQU  USART_ICR_PECF          , 1 << 0        @ Writing 1 to this bit clears the PE flag in the USART_ISR register.
.EQU  USART_ICR_FECF_N        , 1             @ Bit 1 FECF: Framing error clear flag
.EQU  USART_ICR_FECF          , 1 << 1        @ Writing 1 to this bit clears the FE flag in the USART_ISR register.
.EQU  USART_ICR_NCF_N         , 2             @ Bit 2 NCF: Noise detected clear flag
.EQU  USART_ICR_NCF           , 1 << 2        @ Writing 1 to this bit clears the NF flag in the USART_ISR register.
.EQU  USART_ICR_ORECF_N       , 3             @ Bit 3 ORECF: Overrun error clear flag
.EQU  USART_ICR_ORECF         , 1 << 3        @ Writing 1 to this bit clears the ORE flag in the USART_ISR register
.EQU  USART_ICR_IDLECF_N      , 4             @ Bit 4 IDLECF: Idle line detected clear flag
.EQU  USART_ICR_IDLECF        , 1 << 4        @ Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
.EQU  USART_ICR_TCCF_N        , 6             @ Bit 6 TCCF: Transmission complete clear flag
.EQU  USART_ICR_TCCF          , 1 << 6        @ Writing 1 to this bit clears the TC flag in the USART_ISR register.
.EQU  USART_ICR_LBDCF_N       , 8             @ Bit 8 LBDCF: LIN break detection clear flag
.EQU  USART_ICR_LBDCF         , 1 << 8        @ Writing 1 to this bit clears the LBDF flag in the USART_ISR register
.EQU  USART_ICR_CTSCF_N       , 9             @ Bit 9 CTSCF: CTS clear flag
.EQU  USART_ICR_CTSCF         , 1 << 9        @ Writing 1 to this bit clears the CTSIF flag in the USART_ISR register
.EQU  USART_ICR_RTOCF_N       , 11            @ Bit 11 RTOCF: Receiver timeout clear flag
.EQU  USART_ICR_RTOCF         , 1 << 11       @ Writing 1 to this bit clears the RTOF flag in the USART_ISR register
.EQU  USART_ICR_EOBCF_N       , 12            @ Bit 12 EOBCF: End of block clear flag
.EQU  USART_ICR_EOBCF         , 1 << 12       @ Writing 1 to this bit clears the EOBF flag in the USART_ISR register.
.EQU  USART_ICR_CMCF_N        , 17            @ Bit 17 CMCF: Character match clear flag
.EQU  USART_ICR_CMCF          , 1 << 17       @ Writing 1 to this bit clears the CMF flag in the USART_ISR register
.EQU  USART_ICR_WUCF_N        , 20            @ Bit 20 WUCF: Wakeup from Stop mode clear flag
.EQU  USART_ICR_WUCF          , 1 << 20       @ Writing 1 to this bit clears the WUF flag in the USART_ISR register.
@.END

@.ITEM     USART_RDR
.EQU  USART_RDR_RDR_N         , 0             @ Bits 8:0 RDR[8:0]: Receive data value
.EQU  USART_RDR_RDR           , 1 << 0        @ Contains the received data character.
@.END

@.ITEM     USART_TDR
.EQU  USART_TDR_TDR_N         , 0             @ Bits 8:0 TDR[8:0]: Transmit data value
.EQU  USART_TDR_TDR           , 1 << 0        @ Contains the data character to be transmitted.
@.END

