@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы PWR                        |
@ |               для STM32F401xB/C и STM32F401xD/E                  |
@ +------------------------------------------------------------------+
@.ENDDESC


.INCLUDE       "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  PWR_BASE      , APB1PERIPH_BASE + 0x7000
@.END

@.ITEM     PWR_BASE
.EQU  PWR_CR        , 0x00      @ PWR power control register (PWR_CR)
.EQU  PWR_CSR       , 0x04      @ PWR power control/status register (PWR_CSR)
@.END

@.ITEM     PWR_CR
.EQU  PWR_CR_RST_VAL, 0x00004000    @ значение по умолчанию
.EQU  PWR_CR_LPDS_N , 0          @ Bit 0 LPDS: Low-power deepsleep
                                 @ This bit is set and cleared by software. It works together with the PDDS bit.
                                 @ 0: Voltage regulator on during Stop mode.
.EQU  PWR_CR_LPDS   , 1          @ 1: Low-power Voltage regulator on during Stop mode.
.EQU  PWR_CR_PDDS_N , 1          @ Bit 1 PDDS: Power-down deepsleep
                                 @ This bit is set and cleared by software. It works together with the LPDS bit.
                                 @ 0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
                                 @ LPDS bit.
.EQU  PWR_CR_PDDS   , 1<<1       @ 1: Enter Standby mode when the CPU enters deepsleep.
.EQU  PWR_CR_CWUF_N , 2          @ Bit 2 CWUF: Clear wakeup flag
                                 @ This bit is always read as 0.
                                 @ 0: No effect.
.EQU  PWR_CR_CWUF   , 1<<2       @ 1: Clear the WUF Wakeup Flag after 2 System clock cycles.
.EQU  PWR_CR_CSBF_N , 3          @ Bit 3 CSBF: Clear standby flag
                                 @ This bit is always read as 0.
                                 @ 0: No effect.
.EQU  PWR_CR_CSBF   , 1<<3       @ 1: Clear the SBF Standby Flag (write).
.EQU  PWR_CR_PVDE_N , 4          @ Bit 4 PVDE: Power voltage detector enable
                                 @ This bit is set and cleared by software.
                                 @ 0: PVD disabled
.EQU  PWR_CR_PVDE   , 1 << 4     @ 1: PVD enabled
.EQU  PWR_CR_PLS_N  , 5          @ Bits 7:5 PLS[2:0]: PVD level selection
                                 @ These bits are written by software to select the voltage threshold detected by the Power
                                 @ Voltage Detector
.EQU  PWR_CR_PLS_2D2V, 0         @ 000: 2.2 V
.EQU  PWR_CR_PLS_2D3V, 1 << 5    @ 001: 2.3 V
.EQU  PWR_CR_PLS_2D4V, 2 << 5    @ 010: 2.4 V
.EQU  PWR_CR_PLS_2D5V, 3 << 5    @ 011: 2.5 V
.EQU  PWR_CR_PLS_2D6V, 4 << 5    @ 100: 2.6 V
.EQU  PWR_CR_PLS_2D7V, 5 << 5    @ 101: 2.7 V
.EQU  PWR_CR_PLS_2D8V, 6 << 5    @ 110: 2.8 V
.EQU  PWR_CR_PLS_2D9V, 7 << 5    @ 111: 2.9 V
                           @ Note: Refer to the electrical characteristics of the datasheet for more details.
.EQU  PWR_CR_DBP_N  , 8          @ Bit 8 DBP: Disable backup domain write protection
                                 @ In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
                                 @ and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This
                                 @ bit must be set to enable write access to these registers.
                                 @ 0: Access to RTC and RTC Backup registers.
.EQU  PWR_CR_DBP    , 0x01 << 8  @ 1: Access to RTC and RTC Backup registers.
.EQU  PWR_CR_FPDS_N , 9          @ Bit 9 FPDS : Flash power - down in Stop mode
                                 @ When set, the Flash memory enters power-down mode when the device enters Stop mode.
                                 @ This allows to achieve a lower consumption in stop mode but a longer restart time.
                                 @ 0: Flash memory not in power-down when the device is in Stop mode
.EQU  PWR_CR_FPDS   , 0x01 << 9  @ 1: Flash memory in power-down when the device is in Stop mode
.EQU  PWR_CR_LPLVDS_N, 10        @ Bit 10 LPLVDS: Low-power regulator Low Voltage in Deep Sleep
                                 @ 0: Low-power regulator on if LPDS bit is set when the device is in Stop mode.
.EQU  PWR_CR_LPLVDS , 1 << 10    @ 1: Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is
                                 @ set when device is in Stop mode.
.EQU  PWR_CR_MRLVDS_N, 11        @ Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep
                                 @ 0: Main regulator in Voltage scale 3 when the device is in Stop mode.
.EQU  PWR_CR_MPLVDS , 1 << 11    @ 1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is
                                 @ in Stop mode.
.EQU  PWR_CR_ADCDC1_N, 13        @ Bit 13 ADCDC1:
                                 @ 0: No effect.
.EQU  PWR_CR_ADCDC1 , 1 << 13    @ 1: Refer to AN4073 for details on how to use this bit.
                           @ Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when
                                 @ the Prefetch is OFF.
.EQU  PWR_CR_VOS_N  , 14         @ Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
                                 @ These bits control the main internal voltage regulator output voltage to achieve a trade-off
                                 @ between performance and power consumption when the device does not operate at the
                                 @ maximum frequency (refer to the corresponding datasheet for more details).
                                 @ These bits can be modified only when the PLL is OFF. The new value programmed is active
                                 @ only when the PLL is ON. When the PLL is OFF, the voltage regulator is set to scale 3
                                 @ independently of the VOS register content.
.EQU  PWR_CR_VOS_0  , 0          @ 00: Reserved (Scale 3 mode selected)
.EQU  PWR_CR_VOS_1  , 1 << 14    @ 01: Scale 3 mode
.EQU  PWR_CR_VOS_2  , 2 << 14    @ 10: Scale 2 mode
.EQU  PWR_CR_VOS_3  , 3 << 14    @ 11: Reserved (Scale 2 mode selected)
@.END

@.ITEM     PWR_CSR
.EQU  PWR_CSR_VOSRDY_N, 14       @ Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
                                 @ 0: Not ready
.EQU  PWR_CSR_VOSRDY, 1 << 14    @ 1: Ready
.EQU  PWR_CSR_BRE_N , 9          @ Bit 9 BRE: Backup regulator enable
                                 @ When set, the Backup regulator (used to maintain the backup domain content) is enabled. If
                                 @ BRE is reset, the backup regulator is switched off. Once set, the application must wait that
                                 @ the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the
                                 @ backup registers will be maintained in the Standby and VBAT modes.
                                 @ 0: Backup regulator disabled
.EQU  PWR_CSR_BRE   , 1 << 9     @ 1: Backup regulator enabled
                           @ Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
                                 @ or by a power reset.
.EQU  PWR_CSR_EWUP_N, 8          @ Bit 8 EWUP: Enable WKUP pin
                                 @ This bit is set and cleared by software.
                                 @ 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup
                                 @ the device from Standby mode.
.EQU  PWR_CSR_EWUP  , 1 << 8     @ 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down
                                 @ configuration (rising edge on WKUP pin wakes-up the system from Standby mode).
                           @ Note: This bit is reset by a system reset.
.EQU  PWR_CSR_BRR_N , 3          @ Bit 3 BRR: Backup regulator ready
                                 @ Set by hardware to indicate that the Backup Regulator is ready.
                                 @ 0: Backup Regulator not ready
.EQU  PWR_CSR_BRR   , 1 << 3     @ 1: Backup Regulator ready
                           @ Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
                                 @ or power reset.
.EQU  PWR_CSR_PVDO_N, 2          @ Bit 2 PVDO: PVD output
                                 @ This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
                                 @ 0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
.EQU  PWR_CSR_PVDO  , 1 << 2     @ 1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
                           @ Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
                                 @ Standby or reset until the PVDE bit is set.
.EQU  PWR_CSR_SBF_N , 1          @ Bit 1 SBF: Standby flag
                                 @ This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
                                 @ reset) or by setting the CSBF bit in the PWR_CR register.
                                 @ 0: Device has not been in Standby mode
.EQU  PWR_CSR_SBF   , 1 << 1     @ 1: Device has been in Standby mode
.EQU  PWR_CSR_WUF_N , 0          @ Bit 0 WUF: Wakeup flag
                                 @ This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in
                                 @ the PWR_CR register.
                                 @ 0: No wakeup event occurred
.EQU  PWR_CSR_WUF   , 1          @ 1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
                                 @ Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
                           @ Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
                                 @ EWUP bit) when the WKUP pin level is already high.
@.END

