@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.INCLUDE   "/src/inc/base.inc"

@.ITEM     APB2PERIPH_BASE
.EQU  TIM16_BASE     , APB2PERIPH_BASE + 0x4400
.EQU  TIM16          , PERIPH_BASE + TIM16_BASE
.EQU  TIM17_BASE     , APB2PERIPH_BASE + 0x4800
.EQU  TIM17          , PERIPH_BASE + TIM17_BASE

@.ITEM     TIM16 TIM16_BASE TIM17 TIM17_BASE
.EQU  TIM16T17_CR1      , 0x00                        @ TIM16T17 control register 1 (TIMx_CR1)
.EQU  TIM16T17_CR2      , 0x04                        @ TIM16T17 control register 2 (TIMx_CR2)
.EQU  TIM16T17_DIER     , 0X0C                        @ TIM16T17 DMA/interrupt enable register (TIMx_DIER)
.EQU  TIM16T17_SR       , 0X10                        @ TIM16T17 status register (TIMx_SR)
.EQU  TIM16T17_EGR      , 0X14                        @ TIM16T17 event generation register (TIMx_EGR)
.EQU  TIM16T17_CCMR1    , 0X18                        @ TIM16T17 capture/compare mode register 1 (TIMx_CCMR1)
.EQU  TIM16T17_CCER     , 0X20                        @ TIM16T17 capture/compare enable register (TIMx_CCER)
.EQU  TIM16T17_CNT      , 0X24                        @ TIM16T17 counter ( TIMx_CNT)
.EQU  TIM16T17_PSC      , 0X28                        @ TIM16T17 prescaler ( TIMx_PSC)
.EQU  TIM16T17_ARR      , 0X2C                        @ TIM16T17 auto-reload register (TIMx_ARR)
.EQU  TIM16T17_RCR      , 0X30                        @ TIM16T17 repetition counter register (TIMx_RCR)
.EQU  TIM16T17_CCR1     , 0X34                        @ TIM16T17 capture/compare register 1 (TIMx_CCR1)
.EQU  TIM16T17_BDTR     , 0X44                        @ TIM16T17 break and dead-time register (TIMx_BDTR)
.EQU  TIM16T17_DCR      , 0X48                        @ TIM16T17 DMA control register (TIMx_DCR)
.EQU  TIM16T17_DMAR     , 0X4C                        @ TIM16T17 DMA address for full transfer (TIMx_DMAR)


@.ITEM     TIM16T17_CR1
.EQU  TIM16T17_CR1_CKD_N, 8                           @ Bits 9:8 CKD[1:0]: Clock division
.EQU  TIM16T17_CR1_CKD_1TCK, 0                        @ 00: tDTS=tCK_INT
.EQU  TIM16T17_CR1_CKD_2TCK, 1 << 8                   @ 01: tDTS=2*tCK_INT
.EQU  TIM16T17_CR1_CKD_4TCK, 2 << 8                   @ 10: tDTS=4*tCK_INT
.EQU  TIM16T17_CR1_APRE , 1 << 7                      @ Bit 7 ARPE: Auto-reload preload enable
.EQU  TIM16T17_CR1_OPM  , 1 << 3                      @ Bit 3 OPM: One pulse mode
.EQU  TIM16T17_CR1_URS  , 1 << 2                      @ Bit 2 URS: Update request source
.EQU  TIM16T17_CR1_UDIS , 1 << 1                      @ Bit 1 UDIS: Update disable
.EQU  TIM16T17_CR1_CEN  , 1                           @ Bit 0 CEN: Counter enable

@.ITEM     TIM16T17_CR2
.EQU  TIM16T17_CR2_OIS1N, 1 << 9                      @ Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N = 0 after a dead - time when MOE = 0;  1: OC1N = 1 after a dead - time when MOE = 0
.EQU  TIM16T17_CR2_OIS1 , 1 << 8                      @ Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0; 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
.EQU  TIM16T17_CR2_CCDS, 1 << 3                    @ Bit 3 CCDS: Capture/compare DMA selection; 0: CCx DMA request sent when CCx event occurs; 1: CCx DMA requests sent when update event occurs
.EQU  TIM16T17_CR2_CCUS , 1 << 2                      @ Bit 2 CCUS: Capture/compare control update selection; 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only; 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
.EQU  TIM16T17_CR2_CCPS , 1                           @ Bit 0 CCPC: Capture/compare preloaded control; 0: CCxE, CCxNE and OCxM bits are not preloaded; 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).

@.ITEM     TIM16T17_DIER
.EQU  TIM16T17_DIER_TDE , 1 << 14                     @ Bit 14 TDE: Trigger DMA request enable
.EQU  TIM16T17_DIER_CC1DE, 1 << 9                     @ Bit 9 CC1DE: Capture/Compare 1 DMA request enable
.EQU  TIM16T17_DIER_UDE , 1 << 8                      @ Bit 8 UDE: Update DMA request enable
.EQU  TIM16T17_DIER_BIE , 1 << 7                      @ Bit 7 BIE: Break interrupt enable
.EQU  TIM16T17_DIER_TIE , 1 << 6                      @ Bit 6 TIE: Trigger interrupt enable
.EQU  TIM16T17_DIER_COMIE, 1 << 5                     @ Bit 5 COMIE: COM interrupt enable
.EQU  TIM16T17_DIER_CC1IE, 1 << 1                     @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
.EQU  TIM16T17_DIER_UIE , 1 << 0                      @ Bit 0 UIE: Update interrupt enable

@.ITEM     TIM16T17_SR
.EQU  TIM16T17_SR_CC1OF , 1 << 9                      @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
.EQU  TIM16T17_SR_BIF   , 1 << 7                      @ Bit 7 BIF: Break interrupt flag
.EQU  TIM16T17_SR_TIF   , 1 << 6                      @ Bit 6 TIF: Trigger interrupt flag
.EQU  TIM16T17_SR_COMIF , 1 << 5                      @ Bit 5 COMIF: COM interrupt flag
.EQU  TIM16T17_SR_CC1IF , 1 << 1                      @ Bit 1 CC1IF: Capture/Compare 1 interrupt flag
.EQU  TIM16T17_SR_UIF   , 1 << 0                      @ Bit 0 UIF: Update interrupt flag

@.ITEM     TIM16T17_EGR
.EQU  TIM16T17_EGR_BG   , 1 << 7                      @ Bit 7 BG: Break generation
.EQU  TIM16T17_EGR_TG   , 1 << 6                      @ Bit 6 TG: Trigger generation
.EQU  TIM16T17_EGR_COMG , 1 << 5                      @ Bit 5 COMG: Capture/Compare control update generation
.EQU  TIM16T17_EGR_CC1G , 1 << 1                      @ Bit 1 CC1G: Capture/Compare 1 generation
.EQU  TIM16T17_EGR_UG   , 1 << 0                      @ Bit 0 UG: Update generation

@.ITEM     TIM16T17_CCMR1
.EQU  TIM16T17_CCMR1_OCxM_FROZ, 0                     @ 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).
.EQU  TIM16T17_CCMR1_OCxM_SETCH1, 1                   @ 001: Set channel to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM16T17_CCMR1_OCxM_RSTCH1, 2                   @ 010: Set channel to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM16T17_CCMR1_OCxM_TGLCH1, 3                   @ 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
.EQU  TIM16T17_CCMR1_OCxM_FORCELOW, 4                 @ 100: Force inactive level - OC1REF is forced low
.EQU  TIM16T17_CCMR1_OCxM_FORCEHIGH, 5                @ 101: Force active level - OC1REF is forced high
.EQU  TIM16T17_CCMR1_OCxM_PWM1, 6                     @ 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
.EQU  TIM16T17_CCMR1_OCxM_PWM2, 7                     @ 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1  else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.
.EQU  TIM16T17_CCMR1_OC1M_N, 4                        @ Bits 6:4 OC1M: Output Compare 1 mode
.EQU  TIM16T17_CCMR1_OC1PE, 1 << 3                    @ Bit 3 OC1PE: Output Compare 1 preload enable
.EQU  TIM16T17_CCMR1_OC1FE, 1 << 2                    @ Bit 2 OC1FE: Output Compare 1 fast enable
.EQU  TIM16T17_CCMR1_CC1S_N, 0                        @ Bits 1:0 CC1S: Capture/Compare 1 selection
.EQU  TIM16T17_CCMR1_CC1S_CC1OUT, 0                   @ 00: CC1 channel is configured as output
.EQU  TIM16T17_CCMR1_CC1S_IC1_TO_TI1, 1               @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM16T17_CCMR1_CC1S_IC1_TO_TI2, 2               @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM16T17_CCMR1_CC1S_IC1_TO_TRC, 3               @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
.EQU  TIM16T17_CCMR1_ICxF_OFCKLT, 0                   @ 0000: No filter, sampling is done at fDTS
.EQU  TIM16T17_CCMR1_ICxF_CKN2, 1                     @ 0001: fSAMPLING=fCK_INT, N=2
.EQU  TIM16T17_CCMR1_ICxF_CKN4, 2                     @ 0010: fSAMPLING=fCK_INT, N=4
.EQU  TIM16T17_CCMR1_ICxF_CKN8, 3                     @ 0011: fSAMPLING=fCK_INT, N=8
.EQU  TIM16T17_CCMR1_ICxF_TS2N6, 4                    @ 0100: fSAMPLING=fDTS/2, N=6
.EQU  TIM16T17_CCMR1_ICxF_TS2N8, 5                    @ 0101: fSAMPLING=fDTS/2, N=8
.EQU  TIM16T17_CCMR1_ICxF_TS4N6, 6                    @ 0110: fSAMPLING=fDTS/4, N=6
.EQU  TIM16T17_CCMR1_ICxF_TS4N8, 7                    @ 0111: fSAMPLING=fDTS/4, N=8
.EQU  TIM16T17_CCMR1_ICxF_TS8N6, 8                    @ 1000: fSAMPLING=fDTS/8, N=6
.EQU  TIM16T17_CCMR1_ICxF_TS8N8, 9                    @ 1001: fSAMPLING=fDTS/8, N=8
.EQU  TIM16T17_CCMR1_ICxF_TS16N5, 10                  @ 1010: fSAMPLING=fDTS/16, N=5
.EQU  TIM16T17_CCMR1_ICxF_TS16N6, 11                  @ 1011: fSAMPLING=fDTS/16, N=6
.EQU  TIM16T17_CCMR1_ICxF_TS16N8, 12                  @ 1100: fSAMPLING=fDTS/16, N=8
.EQU  TIM16T17_CCMR1_ICxF_TS32N5, 13                  @ 1101: fSAMPLING=fDTS/32, N=5
.EQU  TIM16T17_CCMR1_ICxF_TS32N6, 14                  @ 1110: fSAMPLING=fDTS/32, N=6
.EQU  TIM16T17_CCMR1_ICxF_TS32N8, 15                  @ 1111: fSAMPLING=fDTS/32, N=8
.EQU  TIM16T17_CCMR1_ICxPSC_1, 0                      @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM16T17_CCMR1_ICxPSC_2, 1                      @ 01: capture is done once every 2 events
.EQU  TIM16T17_CCMR1_ICxPSC_4, 2                      @ 10: capture is done once every 4 events
.EQU  TIM16T17_CCMR1_ICxPSC_8, 3                      @ 11: capture is done once every 8 events
.EQU  TIM16T17_CCMR1_IÑ1F_N, 4                        @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
.EQU  TIM16T17_CCMR1_IC1PSC_N, 2                      @ Bits 3:2 IC1PSC: Input capture 1 prescaler

@.ITEM     TIM16T17_CCER
.EQU  TIM16T17_CCER_CC1NP, 1 << 3                     @ Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
.EQU  TIM16T17_CCER_CC1NE, 1 << 2                     @ Bit 2 CC1NE: Capture/Compare 1 complementary output enable
.EQU  TIM16T17_CCER_CC1P, 1 << 1                      @ Bit 1 CC1P: Capture/Compare 1 output polarity
.EQU  TIM16T17_CCER_CC1E, 1 << 0                      @ Bit 0 CC1E: Capture/Compare 1 output enable

@.ITEM     TIM16T17_BDTR
.EQU  TIM16T17_BDTR_MOE , 1 << 15                     @ Bit 15 MOE: Main output enable
.EQU  TIM16T17_BDTR_AOE , 1 << 14                     @ Bit 14 AOE: Automatic output enable
.EQU  TIM16T17_BDTR_BKP , 1 << 13                     @ Bit 13 BKP: Break polarity
.EQU  TIM16T17_BDTR_BKE , 1 << 12                     @ Bit 12 BKE: Break enable
.EQU  TIM16T17_BDTR_OSSR, 1 << 11                     @ Bit 11 OSSR: Off-state selection for Run mode
.EQU  TIM16T17_BDTR_OSSI, 1 << 10                     @ Bit 10 OSSI: Off-state selection for Idle mode
.EQU  TIM16T17_BDTR_LOCK_N, 8                         @ Bits 9:8 LOCK[1:0]: Lock configuration
.EQU  TIM16T17_BDTR_LOCK_OFF, 0                       @ 00: LOCK OFF - No bit is write protected
.EQU  TIM16T17_BDTR_LOCK_LEV1, 1 << 8                 @ 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
.EQU  TIM16T17_BDTR_LOCK_LEV2, 2 << 8                 @ 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
.EQU  TIM16T17_BDTR_LOCK_LEV3, 3 << 8                 @ 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
.EQU  TIM16T17_BDTR_DTG_N, 0                          @ Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration

@.ITEM     TIM16T17_DCR
.EQU  TIM16T17_DCR_DBL_N, 8                           @ Bits 12:8 DBL[4:0]: DMA burst length
.EQU  TIM16T17_DCR_DBL_MIN, 0                         @ 1 transfer
.EQU  TIM16T17_DCR_DBL_MAX, 18                        @ 18 transfers
.EQU  TIM16T17_DCR_DBA_N, 0                           @ Bits 4:0 DBA[4:0]: DMA base address
.EQU  TIM16T17_DCR_DBA_M, 0x1F                        @ DBA Mask


