@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы PWR                        |
@ |                           STM32F303                              |
@ +------------------------------------------------------------------+
@.ENDDESC


.INCLUDE   "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  PWR_BASE                     , ( APB1PERIPH_BASE + 0x7000 )
@.END

@.ITEM     PWR_BASE
.EQU  PWR_CR                       , 0x00
.EQU  PWR_CSR                      , 0x04
@.END

@.ITEM     PWR_CR
.EQU  PWR_CR_RST_VAL               , 0x00000000    @ значение по умолчанию
.EQU  PWR_CR_LPDS_N                , 0
.EQU  PWR_CR_LPDS                  , 0x01    @ Bit 0 LPDS: Low-power deepsleep
.EQU  PWR_CR_PDDS_N                , 1
.EQU  PWR_CR_PDDS                  , 0x02    @ Bit 1 PDDS: Power-down deepsleep
.EQU  PWR_CR_CWUF_N                , 2
.EQU  PWR_CR_CWUF                  , 0x04    @ Bit 2 CWUF: Clear wakeup flag
.EQU  PWR_CR_CSBF_N                , 3
.EQU  PWR_CR_CSBF                  , 0x08    @ Bit 3 CSBF: Clear standby flag
.EQU  PWR_CR_PVDE_N                , 4
.EQU  PWR_CR_PVDE                  , 0x10    @ Bit 4 PVDE: Power voltage detector enable
.EQU  PWR_CR_PLS_N                 , 5    @ Bits 7:5 PLS[2:0]: PVD level selection
.EQU  PWR_CR_PLS_2D0V              , 0 << 5
.EQU  PWR_CR_PLS_2D1V              , 1 << 5
.EQU  PWR_CR_PLS_2D3V              , 2 << 5
.EQU  PWR_CR_PLS_2D5V              , 3 << 5
.EQU  PWR_CR_PLS_2D6V              , 4 << 5
.EQU  PWR_CR_PLS_2D7V              , 5 << 5
.EQU  PWR_CR_PLS_2D8V              , 6 << 5
.EQU  PWR_CR_PLS_2D9V              , 7 << 5
.EQU  PWR_CR_DBP_N                 , 8
.EQU  PWR_CR_DBP                   , 0x01 << 8    @ Bit 8 DBP: Disable backup domain write protection
@.END

@.ITEM     PWR_CSR
.EQU  PWR_CSR_EWUP3_N              , 10    @ Bit 10 EWUP3: Enable WKUP3 pin
.EQU  PWR_CSR_EWUP2_N              , 9    @ Bit 9 EWUP2: Enable WKUP2 pin
.EQU  PWR_CSR_EWUP1_N              , 8    @ Bit 8 EWUP1: Enable WKUP1 pin
.EQU  PWR_CSR_VREFINTRDYF_N        , 3    @ Bit 3 VREFINTRDYF: VREFINT Ready. Read Only. This bit indicates the state of the internal reference voltage. It is set when VREFINT is ready. It is reset during stabilization of VREFINT.
.EQU  PWR_CSR_PVDO_N               , 2    @ Bit 2 PVDO: PVD output
.EQU  PWR_CSR_SBF_N                , 1    @ Bit 1 SBF: Standby flag
.EQU  PWR_CSR_WUF_N                , 0    @ Bit 0 WUF: Wakeup flag
.EQU  PWR_CSR_EWUP3                , 1 << 10    @ Bit 10 EWUP3: Enable WKUP3 pin
.EQU  PWR_CSR_EWUP2                , 1 << 9    @ Bit 9 EWUP2: Enable WKUP2 pin
.EQU  PWR_CSR_EWUP1                , 1 << 8    @ Bit 8 EWUP1: Enable WKUP1 pin
.EQU  PWR_CSR_VREFINTRDYF          , 1 << 3    @ Bit 3 VREFINTRDYF: VREFINT Ready. Read Only. This bit indicates the state of the internal reference voltage. It is set when VREFINT is ready. It is reset during stabilization of VREFINT.
.EQU  PWR_CSR_PVDO                 , 1 << 2    @ Bit 2 PVDO: PVD output
.EQU  PWR_CSR_SBF                  , 1 << 1    @ Bit 1 SBF: Standby flag
.EQU  PWR_CSR_WUF                  , 1    @ Bit 0 WUF: Wakeup flag
@.END
