@.CHARSET =CP1251 ( Cyrillic )
@GNU AS


.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  TIM6_BASE      , APB1PERIPH_BASE + 0x1000
.EQU  TIM6           , PERIPH_BASE + TIM6_BASE

@.ITEM     TIM6 TIM6_BASE
.EQU  TIM6T7_CR1       , 0x00                        @ TIM6T7 control register 1 (TIMx_CR1)
.EQU  TIM6T7_CR2       , 0x04                        @ TIM6T7 control register 2 (TIMx_CR2)
.EQU  TIM6T7_DIER      , 0X0C                        @ TIM6T7 DMA/interrupt enable register (TIMx_DIER)
.EQU  TIM6T7_SR        , 0X10                        @ TIM6T7 status register (TIMx_SR)
.EQU  TIM6T7_EGR       , 0X14                        @ TIM6T7 event generation register (TIMx_EGR)
.EQU  TIM6T7_CNT       , 0X24                        @ TIM6T7 counter ( TIMx_CNT)
.EQU  TIM6T7_PSC       , 0X28                        @ TIM6T7 prescaler ( TIMx_PSC)
.EQU  TIM6T7_ARR       , 0X2C                        @ TIM6T7 auto-reload register (TIMx_ARR)


@.ITEM     TIM6T7_CR1
.EQU  TIM6T7_CR1_APRE  , 1 << 7                      @ Bit 7 ARPE: Auto-reload preload enable
.EQU  TIM6T7_CR1_OPM   , 1 << 3                      @ Bit 3 OPM: One pulse mode
.EQU  TIM6T7_CR1_URS   , 1 << 2                      @ Bit 2 URS: Update request source
.EQU  TIM6T7_CR1_UDIS  , 1 << 1                      @ Bit 1 UDIS: Update disable
.EQU  TIM6T7_CR1_CEN   , 1                           @ Bit 0 CEN: Counter enable

@.ITEM     TIM6T7_CR2
.EQU  TIM6T7_CR2_MMS_N     , 4                           @ Bits 6:4 MMS[2:0]: Master mode selection
.EQU  TIM6T7_CR2_MMS_RESET , 0                           @ 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
.EQU  TIM6T7_CR2_MMS_ENABLE, 1 << 4                      @ 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
.EQU  TIM6T7_CR2_MMS_UPDATE, 2 << 4                      @ 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
.EQU  TIM6T7_CR2_MMS_COMPPULSE, 3 << 4                   @ 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
.EQU  TIM6T7_CR2_MMS_COMP_OC1REF, 4 << 4                 @ 100: Compare - OC1REF signal is used as trigger output (TRGO)
.EQU  TIM6T7_CR2_MMS_COMP_OC2REF, 5 << 4                 @ 101: Compare - OC2REF signal is used as trigger output (TRGO)
.EQU  TIM6T7_CR2_MMS_COMP_OC3REF, 6 << 4                 @ 110: Compare - OC3REF signal is used as trigger output (TRGO)
.EQU  TIM6T7_CR2_MMS_COMP_OC4REF, 7 << 4                 @ 111: Compare - OC4REF signal is used as trigger output (TRGO)

@.ITEM     TIM6T7_DIER
.EQU  TIM6T7_DIER_UDE  , 1 << 8                      @ Bit 8 UDE: Update DMA request enable
.EQU  TIM6T7_DIER_UIE  , 1 << 0                      @ Bit 0 UIE: Update interrupt enable

@.ITEM     TIM6T7_SR
.EQU  TIM6T7_SR_UIF    , 1 << 0                      @ Bit 0 UIF: Update interrupt flag

@.ITEM     TIM6T7_EGR
.EQU  TIM6T7_EGR_UG    , 1 << 0                      @ Bit 0 UG: Update generation


