@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                        Îďđĺäĺëĺíč˙ USB OTG FS                    |
@ |                                STM32F401                         |
@ +------------------------------------------------------------------+
@.ENDDESC

.INCLUDE       "/src/inc/base.inc"

@.ITEM     AHB2PERIPH_BASE
.EQU  OTG_FS_BASE   , 0x00
.EQU  OTG_FS        , PERIPH_BASE + OTG_FS_BASE
@.END

@ Core global control and status registers (CSRs)
@.ITEM OTG_FS OTG_FS_BASE
.EQU  OTG_FS_GOTGCTL, 0x000      @ OTG_FS control and status register (OTG_FS_GOTGCTL
.EQU  OTG_FS_GOTGINT, 0x004      @ OTG_FS interrupt register
.EQU  OTG_FS_GAHBCFG, 0x008      @ OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
.EQU  OTG_FS_GUSBCFG, 0x00C      @ OTG_FS USB configuration register (OTG_FS_GUSBCFG)
.EQU  OTG_FS_GRSTCTL, 0x010      @ OTG_FS reset register (OTG_FS_GRSTCTL)
.EQU  OTG_FS_GINTSTS, 0x014      @ OTG_FS core interrupt register (OTG_FS_GINTSTS)
.EQU  OTG_FS_GINTMSK, 0x018      @ OTG_FS interrupt mask register (OTG_FS_GINTMSK)
.EQU  OTG_FS_GRXSTSR, 0x01C      @ OTG_FS Receive status debug read
.EQU  OTG_FS_GRXSTSP, 0x020      @ OTG status read and pop registers
.EQU  OTG_FS_GRXFSIZ, 0x024      @ OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
.EQU  OTG_FS_HNPTXFSIZ, 0x028    @ OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)
.EQU  OTG_FS_DIEPTXF0, 0x028     @ Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)
.EQU  OTG_FS_HNPTXSTS, 0x02C     @ OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS)
.EQU  OTG_FS_GCCFG  , 0x038      @ OTG_FS general core configuration register (OTG_FS_GCCFG)
.EQU  OTG_FS_CID    , 0x03C      @ OTG_FS core ID register (OTG_FS_CID)
.EQU  OTG_FS_HPTXFSIZ, 0x100     @ OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
.EQU  OTG_FS_DIEPTXF1, 0x104     @ OTG_FS device IN endpoint 1 transmit FIFO size register (OTG_FS_DIEPTXF1)
.EQU  OTG_FS_DIEPTXF2, 0x108     @ OTG_FS device IN endpoint 2 transmit FIFO size register (OTG_FS_DIEPTXF2)
.EQU  OTG_FS_DIEPTXF3, 0x10C     @ OTG_FS device IN endpoint 3 transmit FIFO size register (OTG_FS_DIEPTXF3)
@ Host-mode control and status registers (CSRs)
.EQU  OTG_FS_HCFG   , 0x400      @ OTG_FS Host configuration register (OTG_FS_HCFG)
.EQU  OTG_FS_HFIR   , 0x404      @ OTG_FS Host frame interval register (OTG_FS_HFIR)
.EQU  OTG_FS_HFNUM  , 0x408      @ OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM)
.EQU  OTG_FS_HPTXSTS, 0x410      @ OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
.EQU  OTG_FS_HAINT  , 0x414      @ OTG_FS Host all channels interrupt register (OTG_FS_HAINT)
.EQU  OTG_FS_HAINTMSK, 0x418     @ OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)
.EQU  OTG_FS_HPRT   , 0x440      @ OTG_FS Host port control and status register (OTG_FS_HPRT)
.EQU  OTG_FS_HCCHAR0, 0x500      @ OTG_FS Host channel-0 characteristics register (OTG_FS_HCCHAR0)
.EQU  OTG_FS_HCCHAR1, 0x520      @ OTG_FS Host channel-1 characteristics register (OTG_FS_HCCHAR1)
.EQU  OTG_FS_HCCHAR2, 0x540      @ OTG_FS Host channel-2 characteristics register (OTG_FS_HCCHAR2)
.EQU  OTG_FS_HCCHAR3, 0x560      @ OTG_FS Host channel-3 characteristics register (OTG_FS_HCCHAR3)
.EQU  OTG_FS_HCCHAR4, 0x580      @ OTG_FS Host channel-4 characteristics register (OTG_FS_HCCHAR4)
.EQU  OTG_FS_HCCHAR5, 0x5A0      @ OTG_FS Host channel-5 characteristics register (OTG_FS_HCCHAR5)
.EQU  OTG_FS_HCCHAR6, 0x5C0      @ OTG_FS Host channel-6 characteristics register (OTG_FS_HCCHAR6)
.EQU  OTG_FS_HCCHAR7, 0x5E0      @ OTG_FS Host channel-7 characteristics register (OTG_FS_HCCHAR7)
@ Device-mode control and status registers
.EQU  OTG_FS_DCFG   , 0x800      @ OTG_FS device configuration register (OTG_FS_DCFG)
.EQU  OTG_FS_DCTL   , 0x804      @ OTG_FS device control register (OTG_FS_DCTL)
.EQU  OTG_FS_DSTS   , 0x808      @ OTG_FS device status register (OTG_FS_DSTS)
.EQU  OTG_FS_DIEPMSK, 0x810      @ OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
.EQU  OTG_FS_DOEPMSK, 0x814      @ OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
.EQU  OTG_FS_DAINT  , 0x818      @ OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
.EQU  OTG_FS_DAINTMSK, 0x81C     @ OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
.EQU  OTG_FS_DVBUSDIS, 0x828     @ OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS)
.EQU  OTG_FS_DVBUSPULSE, 0x82C   @ OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE)
.EQU  OTG_FS_DIEPEMPMSK, 0x834   @ OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK)
.EQU  OTG_FS_DIEPCTL0 , 0x900    @ OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
.EQU  OTG_FS_DIEPCTL1 , 0x920    @ OTG_FS device control IN endpoint 1 control register (OTG_FS_DIEPCTL1)
.EQU  OTG_FS_DIEPCTL2 , 0x940    @ OTG_FS device control IN endpoint 2 control register (OTG_FS_DIEPCTL2)
.EQU  OTG_FS_DIEPCTL3 , 0x960    @ OTG_FS device control IN endpoint 3 control register (OTG_FS_DIEPCTL3)
.EQU  OTG_FS_DIEPINT0 , 0x908    @ OTG_FS device endpoint-0 interrupt register (OTG_FS_DIEPINT0)
.EQU  OTG_FS_DIEPINT1 , 0x928    @ OTG_FS device endpoint-1 interrupt register (OTG_FS_DIEPINT1)
.EQU  OTG_FS_DIEPINT2 , 0x948    @ OTG_FS device endpoint-2 interrupt register (OTG_FS_DIEPINT2)
.EQU  OTG_FS_DIEPINT3 , 0x968    @ OTG_FS device endpoint-3 interrupt register (OTG_FS_DIEPINT3)
.EQU  OTG_FS_DIEPTSIZ0, 0x910    @ OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0)
.EQU  OTG_FS_DIEPTSIZ1, 0x930    @ OTG_FS device IN endpoint 1 transfer size register (OTG_FS_DIEPTSIZ1)
.EQU  OTG_FS_DIEPTSIZ2, 0x950    @ OTG_FS device IN endpoint 2 transfer size register (OTG_FS_DIEPTSIZ2)
.EQU  OTG_FS_DIEPTSIZ3, 0x970    @ OTG_FS device IN endpoint 3 transfer size register (OTG_FS_DIEPTSIZ3)
.EQU  OTG_FS_DTXFSTS0 , 0x918    @ OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTS0)
.EQU  OTG_FS_DTXFSTS1 , 0x938    @ OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTS1)
.EQU  OTG_FS_DTXFSTS2 , 0x958    @ OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTS2)
.EQU  OTG_FS_DTXFSTS3 , 0x978    @ OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTS3)
.EQU  OTG_FS_DOEPCTL0 , 0xB00    @ OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0)
.EQU  OTG_FS_DOEPCTL1 , 0xB20    @ OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL1)
.EQU  OTG_FS_DOEPCTL2 , 0xB40    @ OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL2)
.EQU  OTG_FS_DOEPCTL3 , 0xB60    @ OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL3)
.EQU  OTG_FS_DOEPINT0 , 0xB08    @ OTG_FS device endpoint-0 interrupt register (OTG_FS_DOEPINT0)
.EQU  OTG_FS_DOEPINT1 , 0xB28    @ OTG_FS device endpoint-1 interrupt register (OTG_FS_DOEPINT1)
.EQU  OTG_FS_DOEPINT2 , 0xB48    @ OTG_FS device endpoint-2 interrupt register (OTG_FS_DOEPINT2)
.EQU  OTG_FS_DOEPINT3 , 0xB68    @ OTG_FS device endpoint-3 interrupt register (OTG_FS_DOEPINT3)
.EQU  OTG_FS_DOEPTSIZ0, 0xB10    @ OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0)
.EQU  OTG_FS_DOEPTSIZ1, 0xB30    @ OTG_FS device OUT endpoint 1 transfer size register (OTG_FS_DOEPTSIZ1)
.EQU  OTG_FS_DOEPTSIZ2, 0xB50    @ OTG_FS device OUT endpoint 2 transfer size register (OTG_FS_DOEPTSIZ2)
.EQU  OTG_FS_DOEPTSIZ3, 0xB70    @ OTG_FS device OUT endpoint 3 transfer size register (OTG_FS_DOEPTSIZ3)
@ Power and clock gating control and status registers
.equ  OTG_FS_PCGCCTL0, 0xE00     @ Power and clock gating control register
.equ  OTG_FS_PCGCCTL1, 0xE04     @ Power and clock gating control register
@.end

@.item OTG_FS_HCCHAR0 OTG_FS_HCCHAR1 OTG_FS_HCCHAR2 OTG_FS_HCCHAR3 OTG_FS_HCCHAR4 OTG_FS_HCCHAR5 OTG_FS_HCCHAR6 OTG_FS_HCCHAR7
.EQU  OTG_FS_HCINT_OFS   , 0x08  @ OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx)
.EQU  OTG_FS_HCINTMSK_OFS, 0x0C  @ OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx)
.EQU  OTG_FS_HCTSIZ_OFS  , 0x10  @ OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx)
@.END

@.item OTG_FS_GOTGCTL
.equ OTG_FS_GOTGCTL_RSTVAL, 0X00010000 @ Reset value
.EQU  OTG_FS_GOTGCTL_BSVLD, 1 << 19    @ Bit 19 BSVLD: B-session valid
                                       @ Indicates the device mode transceiver status.
                                       @ 0: B-session is not valid.
                                       @ 1: B-session is valid.
                                       @ In OTG mode, you can use this bit to determine if the device is connected or disconnected.
                                 @ Note: Only accessible in device mode.
.EQU  OTG_FS_GOTGCTL_ASVLD, 1 << 18    @ Bit 18 ASVLD: A-session valid
                                       @ Indicates the host mode transceiver status.
                                       @ 0: A-session is not valid
                                       @ 1: A-session is valid
                                 @ Note: Only accessible in host mode.
.EQU  OTG_FS_GOTGCTL_DBCT, 1<<17       @ Bit 17 DBCT: Long/short debounce time
                                       @ Indicates the debounce time of a detected connection.
                                       @ 0: Long debounce time, used for physical connections (100 ms + 2.5 µs)
                                       @ 1: Short debounce time, used for soft connections (2.5 µs)
                                 @ Note: Only accessible in host mode.
.EQU  OTG_FS_GOTGCTL_CIDSTS, 1<<16     @ Bit 16 CIDSTS: Connector ID status
                                       @ Indicates the connector ID status on a connect event.
                                       @ 0: The OTG_FS controller is in A-device mode
                                       @ 1: The OTG_FS controller is in B-device mode
                                 @ Note: Accessible in both device and host modes.
.EQU  OTG_FS_GOTGCTL_DHNPEN, 1<<11     @ Bit 11 DHNPEN: Device HNP enabled
                                       @ The application sets this bit when it successfully receives a SetFeature.SetHNPEnable
                                       @ command from the connected USB host.
                                       @ 0: HNP is not enabled in the application
                                       @ 1: HNP is enabled in the application
                                 @ Note: Only accessible in device mode.
.EQU  OTG_FS_GOTGCTL_HSHNPEN, 1<<10    @ Bit 10 HSHNPEN: host set HNP enable
                                       @ The application sets this bit when it has successfully enabled HNP (using the
                                       @ SetFeature.SetHNPEnable command) on the connected device.
                                       @ 0: Host Set HNP is not enabled
                                       @ 1: Host Set HNP is enabled
                                 @ Note: Only accessible in host mode.
.EQU  OTG_FS_GOTGCTL_HNPRQ, 1<<9       @ Bit 9 HNPRQ: HNP request
                                       @ The application sets this bit to initiate an HNP request to the connected USB host. The
                                       @ application can clear this bit by writing a 0 when the host negotiation success status change
                                       @ bit in the OTG_FS_GOTGINT register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The
                                       @ core clears this bit when the HNSSCHG bit is cleared.
                                       @ 0: No HNP request
                                       @ 1: HNP request
                                 @ Note: Only accessible in device mode.
.EQU  OTG_FS_GOTGCTL_HNGSCS, 1<<8      @ Bit 8 HNGSCS: Host negotiation success
                                       @ The core sets this bit when host negotiation is successful. The core clears this bit when the
                                       @ HNP Request (HNPRQ) bit in this register is set.
                                       @ 0: Host negotiation failure
                                       @ 1: Host negotiation success
                                 @ Note: Only accessible in device mode.
.EQU  OTG_FS_GOTGCTL_SRQ, 1<<1         @ Bit 1 SRQ: Session request
                                       @ The application sets this bit to initiate a session request on the USB. The application can
                                       @ clear this bit by writing a 0 when the host negotiation success status change bit in the
                                       @ OTG_FS_GOTGINT register (HNSSCHG bit in OTG_FS_GOTGINT) is set. The core clears
                                       @ this bit when the HNSSCHG bit is cleared.
                                       @ If you use the USB 1.1 full-speed serial transceiver interface to initiate the session request,
                                       @ the application must wait until VBUS discharges to 0.2 V, after the B-Session Valid bit in this
                                       @ register (BSVLD bit in OTG_FS_GOTGCTL) is cleared.
                                       @ 0: No session request
                                       @ 1: Session request
                                 @ Note: Only accessible in device mode.
.EQU  OTG_FS_GOTGCTL_SRQSCS, 1         @ Bit 0 SRQSCS: Session request success
                                       @ The core sets this bit when a session request initiation is successful.
                                       @ 0: Session request failure
                                       @ 1: Session request success
                                 @ Note: Only accessible in device mode.
@.end



@.item OTG_FS_GOTGINT
.equ OTG_FS_GOTGINT_DBCDNE  , 1<<19    @ Bit 19 DBCDNE: Debounce done
                                       @ The core sets this bit when the debounce is completed after the device connect. The
                                       @ application can start driving USB reset after seeing this interrupt. This bit is only valid when
                                       @ the HNP Capable or SRP Capable bit is set in the OTG_FS_GUSBCFG register (HNPCAP
                                       @ bit or SRPCAP bit in OTG_FS_GUSBCFG, respectively).
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GOTGINT_ADTOCHG , 1<<18    @ Bit 18 ADTOCHG: A-device timeout change
                                       @ The core sets this bit to indicate that the A-device has timed out while waiting for the B-device
                                       @ to connect.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GOTGINT_HNGDET  , 1<<17    @ Bit 17 HNGDET: Host negotiation detected
                                       @ The core sets this bit when it detects a host negotiation request on the USB.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GOTGINT_HNSSCHG  , 1<<9    @ Bit 9 HNSSCHG: Host negotiation success status change
                                       @ The core sets this bit on the success or failure of a USB host negotiation request. The
                                       @ application must read the host negotiation success bit of the OTG_FS_GOTGCTL register
                                       @ (HNGSCS in OTG_FS_GOTGCTL) to check for success or failure.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GOTGINT_SRSSCHG  , 1<<8    @ Bit 8 SRSSCHG: Session request success status change
                                       @ The core sets this bit on the success or failure of a session request. The application must
                                       @ read the session request success bit in the OTG_FS_GOTGCTL register (SRQSCS bit in
                                       @ OTG_FS_GOTGCTL) to check for success or failure.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GOTGINT_SEDET  , 1<<2      @ Bit 2 SEDET: Session end detected
                                       @ The core sets this bit to indicate that the level of the voltage on VBUS is no longer valid for a
                                       @ B-Peripheral session when VBUS < 0.8 V.
@.end

@.item OTG_FS_GAHBCFG
.equ  OTG_FS_GAHBCFG_PTXFELVL , 1<<8   @ Bit 8 PTXFELVL: Periodic TxFIFO empty level
                                       @ Indicates when the periodic TxFIFO empty interrupt bit in the OTG_FS_GINTSTS register
                                       @ (PTXFE bit in OTG_FS_GINTSTS) is triggered.
                                       @ 0: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is half empty
                                       @ 1: PTXFE (in OTG_FS_GINTSTS) interrupt indicates that the Periodic TxFIFO is completely
                                       @ empty
                                 @ Note: Only accessible in host mode
.equ  OTG_FS_GAHBCFG_TXFELVL , 1<<7    @ Bit 7 TXFELVL: TxFIFO empty level
                                       @ In device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (TXFE in
                                       @ OTG_FS_DIEPINTx.) is triggered.
                                       @ 0: the TXFE (in OTG_FS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is half
                                       @ empty
                                       @ 1: the TXFE (in OTG_FS_DIEPINTx) interrupt indicates that the IN Endpoint TxFIFO is
                                       @ completely empty
                                       @ In host mode, this bit indicates when the nonperiodic Tx FIFO empty interrupt (NPTXFE bit in
                                       @ OTG_FS_GINTSTS) is triggered:
                                       @ 0: the NPTXFE (in OTG_FS_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is
                                       @ half empty
                                       @ 1: the NPTXFE (in OTG_FS_GINTSTS) interrupt indicates that the nonperiodic Tx FIFO is
                                       @ completely empty
.equ  OTG_FS_GAHBCFG_GINTMSK  , 1      @ Bit 0 GINTMSK: Global interrupt mask
                                       @ The application uses this bit to mask or unmask the interrupt line assertion to itself.
                                       @ Irrespective of this bit’s setting, the interrupt status registers are updated by the core.
                                       @ 0: Mask the interrupt assertion to the application.
                                       @ 1: Unmask the interrupt assertion to the application.
                                 @ Note: Accessible in both device and host modes.
@.end

@.item OTG_FS_GUSBCFG
.equ OTG_FS_GUSBCFG_CTXPKT  , 1<<31    @ Bit 31 CTXPKT: Corrupt Tx packet
                                       @ This bit is for debug purposes only. Never set this bit to 1.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GUSBCFG_FDMOD  , 1<<30     @ Bit 30 FDMOD: Force device mode
                                       @ Writing a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input
                                       @ pin.
                                       @ 0: Normal mode
                                       @ 1: Force device mode
                                       @ After setting the force bit, the application must wait at least 25 ms before the change takes
                                       @ effect.
                                 @ Note: Accessible in both device and host modes
.equ OTG_FS_GUSBCFG_FHMOD  , 1<<30     @ Bit 29 FHMOD: Force host mode
                                       @ Writing a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin.
                                       @ 0: Normal mode
                                       @ 1: Force host mode
                                       @ After setting the force bit, the application must wait at least 25 ms before the change takes
                                       @ effect.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GUSBCFG_TRDT_N  , 10       @ Bits 13:10 TRDT: USB turnaround time
.equ OTG_FS_GUSBCFG_TRDT_L  , 4        @ These bits allow setting the turnaround time in PHY clocks. They must be configured
                                       @ according to Table 133: TRDT values, depending on the application AHB frequency. Higher
                                       @ TRDT values allow stretching the USB response time to IN tokens in order to compensate for
                                       @ longer AHB read access latency to the Data FIFO.
                                 @ Note: Only accessible in device mode.
@
@                   Table 133. TRDT values (stm32f401)
@
@ AHB frequency range (MHz)     TRDT  minimum value
@      Min.         Max
@     14.2          15                 0xF
@     15            16                 0xE
@     16            17.2               0xD
@     17.2          18.5               0xC
@     18.5          20                 0xB
@     20            21.8               0xA
@     21.8          24                 0x9
@     24            27.5               0x8
@     27.5          32                 0x7
@     32             -                 0x6
@
.equ OTG_FS_GUSBCFG_HNPCAP  , 1<<9     @ Bit 9 HNPCAP: HNP-capable
                                       @ The application uses this bit to control the OTG_FS controller’s HNP capabilities.
                                       @ 0: HNP capability is not enabled.
                                       @ 1: HNP capability is enabled.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GUSBCFG_SRPCAP  , 1<<8     @ Bit 8 SRPCAP: SRP-capable
                                       @ The application uses this bit to control the OTG_FS controller’s SRP capabilities. If the core
                                       @ operates as a non-SRP-capable
                                       @ B-device, it cannot request the connected A-device (host) to activate VBUS and start a
                                       @ session.
                                       @ 0: SRP capability is not enabled.
                                       @ 1: SRP capability is enabled.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GUSBCFG_PHYSEL  , 1<<6     @ Bit 6 PHYSEL: Full speed serial transceiver select
                                       @ This bit is always 1 with read-only access.
.equ OTG_FS_GUSBCFG_TOCAL_N  , 0       @ Bits 2:0 TOCAL: FS timeout calibration
.equ OTG_FS_GUSBCFG_TOCAL_L  , 3       @ The number of PHY clocks that the application programs in this field is added to the full-
                                       @ speed interpacket timeout duration in the core to account for any additional delays
                                       @ introduced by the PHY. This can be required, because the delay introduced by the PHY in
                                       @ generating the line state condition can vary from one PHY to another.
                                       @ The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
                                       @ application must program this field based on the speed of enumeration. The number of bit
                                       @ times added per PHY clock is 0.25 bit times.
@.end

@.item OTG_FS_GRSTCTL
.equ OTG_FS_GRSTCTL_AHBIDL  , 1<<31    @ Bit 31 AHBIDL: AHB master idle
                                       @ Indicates that the AHB master state machine is in the Idle condition.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GRSTCTL_TXFNUM_N  , 6      @ Bits 10:6 TXFNUM: TxFIFO number
.equ OTG_FS_GRSTCTL_TXFNUM_L  , 5      @ This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not
                                       @ be changed until the core clears the TxFIFO Flush bit.
                                       @ 00000:
                                       @        – Non-periodic TxFIFO flush in host mode
                                       @        – Tx FIFO 0 flush in device mode
                                       @ 00001:
                                       @        – Periodic TxFIFO flush in host mode
                                       @        – TXFIFO 1 flush in device mode
                                       @ 00010: TXFIFO 2 flush in device mode
                                       @ ...
                                       @ 00101: TXFIFO 15 flush in device mode
                                       @ 10000: Flush all the transmit FIFOs in device or host mode.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GRSTCTL_TXFFLSH  , 1<<5    @ Bit 5 TXFFLSH: TxFIFO flush
                                       @ This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the
                                       @ midst of a transaction.
                                       @ The application must write this bit only after checking that the core is neither writing to the
                                       @ TxFIFO nor reading from the TxFIFO. Verify using these registers:
                                       @ Read—NAK Effective Interrupt ensures the core is not reading from the FIFO
                                       @ Write—AHBIDL bit in OTG_FS_GRSTCTL ensures the core is not writing anything to the
                                       @ FIFO.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GRSTCTL_RXFFLSH  , 1<<4    @ Bit 4 RXFFLSH: RxFIFO flush
                                       @ The application can flush the entire RxFIFO using this bit, but must first ensure that the core
                                       @ is not in the middle of a transaction.
                                       @ The application must only write to this bit after checking that the core is neither reading from
                                       @ the RxFIFO nor writing to the RxFIFO.
                                       @ The application must wait until the bit is cleared before performing any other operations. This
                                       @ bit requires 8 clocks (slowest of PHY or AHB clock) to clear.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GRSTCTL_FCRST  , 1<<2      @ Bit 2 FCRST: Host frame counter reset
                                       @ The application writes this bit to reset the frame number counter inside the core. When the
                                       @ frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0.
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GRSTCTL_HSRST  , 1<<1      @ Bit 1 HSRST: HCLK soft reset
                                       @ The application uses this bit to flush the control logic in the AHB Clock domain. Only AHB
                                       @ Clock Domain pipelines are reset.
                                       @ FIFOs are not flushed with this bit.
                                       @ All state machines in the AHB clock domain are reset to the Idle state after terminating the
                                       @ transactions on the AHB, following the protocol.
                                       @ CSR control bits used by the AHB clock domain state machines are cleared.
                                       @ To clear this interrupt, status mask bits that control the interrupt status and are generated by
                                       @ the AHB clock domain state machine are cleared.
                                       @ Because interrupt status bits are not cleared, the application can get the status of any core
                                       @ events that occurred after it set this bit.
                                       @ This is a self-clearing bit that the core clears after all necessary logic is reset in the core. This
                                       @ can take several clocks, depending on the core’s current state.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GRSTCTL_CSRST  , 0         @ Bit 0 CSRST: Core soft reset
                                       @ Resets the HCLK and PCLK domains as follows:
                                       @ Clears the interrupts and all the CSR register bits except for the following bits:
                                       @ – RSTPDMODL bit in OTG_FS_PCGCCTL
                                       @ – GAYEHCLK bit in OTG_FS_PCGCCTL
                                       @ – PWRCLMP bit in OTG_FS_PCGCCTL
                                       @ – STPPCLK bit in OTG_FS_PCGCCTL
                                       @ – FSLSPCS bit in OTG_FS_HCFG
                                       @ – DSPD bit in OTG_FS_DCFG
                                       @ All module state machines (except for the AHB slave unit) are reset to the Idle state, and all
                                       @ the transmit FIFOs and the receive FIFO are flushed.
                                       @ Any transactions on the AHB Master are terminated as soon as possible, after completing the
                                       @ last data phase of an AHB transfer. Any transactions on the USB are terminated immediately.
                                       @ The application can write to this bit any time it wants to reset the core. This is a self-clearing
                                       @ bit and the core clears this bit after all the necessary logic is reset in the core, which can take
                                       @ several clocks, depending on the current state of the core. Once this bit has been cleared,
                                       @ the software must wait at least 3 PHY clocks before accessing the PHY domain
                                       @ (synchronization delay). The software must also check that bit 31 in this register is set to 1
                                       @ (AHB Master is Idle) before starting any operation.
                                       @ Typically, the software reset is used during software development and also when you
                                       @ dynamically change the PHY selection bits in the above listed USB configuration registers.
                                       @ When you change the PHY, the corresponding clock for the PHY is selected and used in the
                                       @ PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper
                                       @ operation.
                                 @ Note: Accessible in both device and host modes.
@.end

@.item OTG_FS_GINTSTS
.equ OTG_FS_GINTSTS_RSTVAL , 0x04000020  @ Reset value
.equ OTG_FS_GINTSTS_WKUPINT  , 1<<31   @ Bit 31 WKUPINT: Resume/remote wakeup detected interrupt
                                       @ In device mode, this interrupt is asserted when a resume is detected on the USB. In host
                                       @ mode, this interrupt is asserted when a remote wakeup is detected on the USB.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GINTSTS_SRQINT  , 1<<30    @ Bit 30 SRQINT: Session request/new session detected interrupt
                                       @ In host mode, this interrupt is asserted when a session request is detected from the device.
                                       @ In device mode, this interrupt is asserted when VBUS is in the valid range for a B-peripheral
                                       @ device. Accessible in both device and host modes.
.equ OTG_FS_GINTSTS_DISCINT  , 1<<29   @ Bit 29 DISCINT: Disconnect detected interrupt
                                       @ Asserted when a device disconnect is detected.
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTSTS_CIDSCHG  , 1<<28   @ Bit 28 CIDSCHG: Connector ID status change
                                       @ The core sets this bit when there is a change in connector ID status.
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GINTSTS_PTXFE  , 1<<26     @ Bit 26 PTXFE: Periodic TxFIFO empty
                                       @ Asserted when the periodic transmit FIFO is either half or completely empty and there is
                                       @ space for at least one entry to be written in the periodic request queue. The half or
                                       @ completely empty status is determined by the periodic TxFIFO empty level bit in the
                                       @ OTG_FS_GAHBCFG register (PTXFELVL bit in OTG_FS_GAHBCFG).
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTSTS_HCINT  , 1<<25     @ Bit 25 HCINT: Host channels interrupt
                                       @ The core sets this bit to indicate that an interrupt is pending on one of the channels of the
                                       @ core (in host mode). The application must read the OTG_FS_HAINT register to determine
                                       @ the exact number of the channel on which the interrupt occurred, and then read the
                                       @ corresponding OTG_FS_HCINTx register to determine the exact cause of the interrupt. The
                                       @ application must clear the appropriate status bit in the OTG_FS_HCINTx register to clear
                                       @ this bit.
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTSTS_HPRTINT  , 1<<24   @ Bit 24 HPRTINT: Host port interrupt
                                       @ The core sets this bit to indicate a change in port status of one of the OTG_FS controller
                                       @ ports in host mode. The application must read the OTG_FS_HPRT register to determine the
                                       @ exact event that caused this interrupt. The application must clear the appropriate status bit in
                                       @ the OTG_FS_HPRT register to clear this bit.
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTSTS_IPXFR  , 1<<21     @ Bit 21 IPXFR: Incomplete periodic transfer
                                       @ In host mode, the core sets this interrupt bit when there are incomplete periodic transactions
                                       @ still pending, which are scheduled for the current frame.
                                       @ INCOMPISOOUT: Incomplete isochronous OUT transfer
                                       @ In device mode, the core sets this interrupt to indicate that there is at least one isochronous
                                       @ OUT endpoint on which the transfer is not completed in the current frame. This interrupt is
                                       @ asserted along with the End of periodic frame interrupt (EOPF) bit in this register.
.equ OTG_FS_GINTSTS_IISOIXFR  , 1<<20  @ Bit 20 IISOIXFR: Incomplete isochronous IN transfer
                                       @ The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on
                                       @ which the transfer is not completed in the current frame. This interrupt is asserted along with
                                       @ the End of periodic frame interrupt (EOPF) bit in this register.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_OEPINT  , 1<<19    @ Bit 19 OEPINT: OUT endpoint interrupt
                                       @ The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of
                                       @ the core (in device mode). The application must read the OTG_FS_DAINT register to
                                       @ determine the exact number of the OUT endpoint on which the interrupt occurred, and then
                                       @ read the corresponding OTG_FS_DOEPINTx register to determine the exact cause of the
                                       @ interrupt. The application must clear the appropriate status bit in the corresponding
                                       @ OTG_FS_DOEPINTx register to clear this bit.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_IEPINT  , 1<<18    @ Bit 18 IEPINT: IN endpoint interrupt
                                       @ The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the
                                       @ core (in device mode). The application must read the OTG_FS_DAINT register to determine
                                       @ the exact number of the IN endpoint on which the interrupt occurred, and then read the
                                       @ corresponding OTG_FS_DIEPINTx register to determine the exact cause of the interrupt.
                                       @ The application must clear the appropriate status bit in the corresponding
                                       @ OTG_FS_DIEPINTx register to clear this bit.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_EOPF  , 1<<15      @ Bit 15 EOPF: End of periodic frame interrupt
                                       @ Indicates that the period specified in the periodic frame interval field of the OTG_FS_DCFG
                                       @ register (PFIVL bit in OTG_FS_DCFG) has been reached in the current frame.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_ISOODRP  , 1<<14   @ Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt
                                       @ The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO
                                       @ because the RxFIFO does not have enough space to accommodate a maximum size packet
                                       @ for the isochronous OUT endpoint.
                                 @ Note: Only accessible in device mode
.equ OTG_FS_GINTSTS_ENUMDNE  , 1<<13   @ Bit 13 ENUMDNE: Enumeration done
                                       @ The core sets this bit to indicate that speed enumeration is complete. The application must
                                       @ read the OTG_FS_DSTS register to obtain the enumerated speed.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_USBRST  , 1<<12    @ Bit 12 USBRST: USB reset
                                       @ The core sets this bit to indicate that a reset is detected on the USB.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_USBSUSP  , 1<<11   @ Bit 11 USBSUSP: USB suspend
                                       @ The core sets this bit to indicate that a suspend was detected on the USB. The core enters
                                       @ the Suspended state when there is no activity on the data lines for a period of 3 ms.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_ESUSP  , 1<<10     @ Bit 10 ESUSP: Early suspend
                                       @ The core sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_GONAKEFF  , 1<<7   @ Bit 7 GONAKEFF: Global OUT NAK effective
                                       @ Indicates that the Set global OUT NAK bit in the OTG_FS_DCTL register (SGONAK bit in
                                       @ OTG_FS_DCTL), set by the application, has taken effect in the core. This bit can be cleared
                                       @ by writing the Clear global OUT NAK bit in the OTG_FS_DCTL register (CGONAK bit in
                                       @ OTG_FS_DCTL).
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_GINAKEFF  , 1<<6   @ Bit 6 GINAKEFF: Global IN non-periodic NAK effective
                                       @ Indicates that the Set global non-periodic IN NAK bit in the OTG_FS_DCTL register
                                       @ (SGINAK bit in OTG_FS_DCTL), set by the application, has taken effect in the core. That is,
                                       @ the core has sampled the Global IN NAK bit set by the application. This bit can be cleared by
                                       @ clearing the Clear global non-periodic IN NAK bit in the OTG_FS_DCTL register (CGINAK
                                       @ bit in OTG_FS_DCTL).
                                       @ This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The
                                       @ STALL bit takes precedence over the NAK bit.
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTSTS_NPTXFE  , 1<<5     @ Bit 5 NPTXFE: Non-periodic TxFIFO empty
                                       @ This interrupt is asserted when the non-periodic TxFIFO is either half or completely empty,
                                       @ and there is space for at least one entry to be written to the non-periodic transmit request
                                       @ queue. The half or completely empty status is determined by the non-periodic TxFIFO empty
                                       @ level bit in the OTG_FS_GAHBCFG register (TXFELVL bit in OTG_FS_GAHBCFG).
                                 @ Note: Accessible in host mode only.
.equ OTG_FS_GINTSTS_RXFLVL  , 1<<4     @ Bit 4 RXFLVL: RxFIFO non-empty
                                       @ Indicates that there is at least one packet pending to be read from the RxFIFO.
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTSTS_SOF  , 1<<3        @ Bit 3 SOF: Start of frame
                                       @ In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is
                                       @ transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.
                                       @ In device mode, in the core sets this bit to indicate that an SOF token has been received on
                                       @ the USB. The application can read the Device Status register to get the current frame
                                       @ number. This interrupt is seen only when the core is operating in FS.
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTSTS_OTGINT  , 1<<2     @ Bit 2 OTGINT: OTG interrupt
                                       @ The core sets this bit to indicate an OTG protocol event. The application must read the OTG
                                       @ Interrupt Status (OTG_FS_GOTGINT) register to determine the exact event that caused this
                                       @ interrupt. The application must clear the appropriate status bit in the OTG_FS_GOTGINT
                                       @ register to clear this bit.
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTSTS_MMIS  , 1<<1       @ Bit 1 MMIS: Mode mismatch interrupt
                                       @ The core sets this bit when the application is trying to access:
                                       @ – A host mode register, when the core is operating in device mode
                                       @ – A device mode register, when the core is operating in host mode
                                       @ The register access is completed on the AHB with an OKAY response, but is ignored by the
                                       @ core internally and does not affect the operation of the core.
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTSTS_CMOD  , 1          @ Bit 0 CMOD: Current mode of operation
                                       @ Indicates the current mode.
                                       @ 0: Device mode
                                       @ 1: Host mode
                                 @ Note: Accessible in both host and device modes.
@.end

@.item OTG_FS_GINTMSK
.equ OTG_FS_GINTMSK_WUIM , 1<<31       @ Bit 31 WUIM: Resume/remote wakeup detected interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTMSK_SRQIM , 1<<30      @ Bit 30 SRQIM: Session request/new session detected interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTMSK_DISCINT , 1<<29    @ Bit 29 DISCINT: Disconnect detected interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode
.equ OTG_FS_GINTMSK_CIDSCHGM , 1<<28   @ Bit 28 CIDSCHGM: Connector ID status change mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both host and device modes.
.equ OTG_FS_GINTMSK_PTXFEM , 1<<26     @ Bit 26 PTXFEM: Periodic TxFIFO empty mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTMSK_HCIM , 1<<25       @ Bit 25 HCIM: Host channels interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTMSK_PRTIM , 1<<24      @ Bit 24 PRTIM: Host port interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in host mode.
.equ OTG_FS_GINTMSK_IPXFRM , 1<<21     @ Bit 21 IPXFRM: Incomplete periodic transfer mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in host mode.
                                       @ IISOOXFRM: Incomplete isochronous OUT transfer mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_IISOIXFRM , 1<<20  @ Bit 20 IISOIXFRM: Incomplete isochronous IN transfer mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_OEPINT , 1<<19     @ Bit 19 OEPINT: OUT endpoints interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_IEPINT , 1<<18     @ Bit 18 IEPINT: IN endpoints interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_EOPFM , 1<<15      @ Bit 15 EOPFM: End of periodic frame interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_ISOODRPM , 1<<14   @ Bit 14 ISOODRPM: Isochronous OUT packet dropped interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_ENUMDNEM , 1<<13   @ Bit 13 ENUMDNEM: Enumeration done mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_USBRST , 1<<12     @ Bit 12 USBRST: USB reset mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_USBSUSPM , 1<<11   @ Bit 11 USBSUSPM: USB suspend mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_ESUSPM , 1<<10     @ Bit 10 ESUSPM: Early suspend mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_GONAKEFFM , 1<<7   @ Bit 7 GONAKEFFM: Global OUT NAK effective mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_GINAKEFFM , 1<<6   @ Bit 6 GINAKEFFM: Global non-periodic IN NAK effective mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in device mode.
.equ OTG_FS_GINTMSK_NPTXFEM , 1<<5     @ Bit 5 NPTXFEM: Non-periodic TxFIFO empty mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Only accessible in Host mode.
.equ OTG_FS_GINTMSK_RXFLVLM , 1<<4     @ Bit 4 RXFLVLM: Receive FIFO non-empty mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GINTMSK_SOFM , 1<<3        @ Bit 3 SOFM: Start of frame mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GINTMSK_OTGINT , 1<<2      @ Bit 2 OTGINT: OTG interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both device and host modes.
.equ OTG_FS_GINTMSK_MMISM , 1<<1       @ Bit 1 MMISM: Mode mismatch interrupt mask
                                       @ 0: Masked interrupt
                                       @ 1: Unmasked interrupt
                                 @ Note: Accessible in both device and host modes.
@.end

@.item OTG_FS_GRXSTSR OTG_FS_GRXSTSP
@ Host mode
.equ OTG_FS_GRXSTSx_PKTSTS_N   , 17    @ Bits 20:17 PKTSTS: Packet status
.equ OTG_FS_GRXSTSx_PKTSTS_L   , 4     @ Indicates the status of the received packet
                                       @ 0010: IN data packet received
                                       @ 0011: IN transfer completed (triggers an interrupt)
                                       @ 0101: Data toggle error (triggers an interrupt)
                                       @ 0111: Channel halted (triggers an interrupt)
                                       @ Others: Reserved
.equ OTG_FS_GRXSTSx_DPID_N , 15        @ Bits 16:15 DPID: Data PID
.equ OTG_FS_GRXSTSx_DPID_L , 2         @ Indicates the Data PID of the received packet
                                       @ 00 : DATA0
                                       @ 10 : DATA1
                                       @ 01 : DATA2
                                       @ 11 : MDATA
.equ OTG_FS_GRXSTSx_BCNT_N   , 4       @ Bits 14:4 BCNT: Byte count
.equ OTG_FS_GRXSTSx_BCNT_L   , 11      @ Indicates the byte count of the received IN data packet.
.equ OTG_FS_GRXSTSx_CHNUM_N  , 0       @ Bits 3:0 CHNUM: Channel number
.equ OTG_FS_GRXSTSx_CHNUM_L  , 4       @ Indicates the channel number to which the current received packet belongs.
@
@ Device mode
.equ OTG_FS_GRXSTSx_FRMNUM_N  , 21     @ Bits 24:21 FRMNUM: Frame number
.equ OTG_FS_GRXSTSx_FRMNUM_L  , 4      @ This is the least significant 4 bits of the frame number in which the packet is received on the
                                       @ USB. This field is supported only when isochronous OUT endpoints are supported.
.equ OTG_FS_GRXSTSx_PKTSTS_N  , 17     @ Bits 20:17 PKTSTS: Packet status
.equ OTG_FS_GRXSTSx_PKTSTS_L  , 4      @ Indicates the status of the received packet
                                       @ 0001: Global OUT NAK (triggers an interrupt)
                                       @ 0010: OUT data packet received
                                       @ 0011: OUT transfer completed (triggers an interrupt)
                                       @ 0100: SETUP transaction completed (triggers an interrupt)
                                       @ 0110: SETUP data packet received
                                       @ Others: Reserved
.equ OTG_FS_GRXSTSx_DPID_N  , 15       @ Bits 16:15 DPID: Data PID
.equ OTG_FS_GRXSTSx_DPID_L  , 2        @ Indicates the Data PID of the received OUT data packet
                                       @ 00: DATA0
                                       @ 10: DATA1
                                       @ 01: DATA2
                                       @ 11: MDATA
.equ OTG_FS_GRXSTSx_BCNT_N  , 4        @ Bits 14:4 BCNT: Byte count
.equ OTG_FS_GRXSTSx_BCNT_L  , 11       @ Indicates the byte count of the received data packet.
.equ OTG_FS_GRXSTSx_EPNUM_N  , 0       @ Bits 3:0 EPNUM: Endpoint number
.equ OTG_FS_GRXSTSx_EPNUM_L  , 4       @ Indicates the endpoint number to which the current received packet belongs.
@.end

@.item OTG_FS_GRXFSIZ
.equ OTG_FS_GRXFSIZ_RSTVAL, 0x0200     @ Reset value
.equ OTG_FS_GRXFSIZ_RXFD_N   , 0       @ Bits 15:0 RXFD: RxFIFO depth
.equ OTG_FS_GRXFSIZ_RXFD_L   , 16      @ This value is in terms of 32-bit words.
.equ OTG_FS_GRXFSIZ_RXFD_M   , 0xFFFF  @ Minimum value is 16
                                       @ Maximum value is 256
                                       @ The power-on reset value of this register is specified as the largest Rx data FIFO depth.
@.end

@.item OTG_FS_HNPTXFSIZ
.equ OTG_FS_HNPTXFSIZ_NPTXFD_N  , 16   @ Bits 31:16 NPTXFD: Non-periodic TxFIFO depth
.equ OTG_FS_HNPTXFSIZ_NPTXFD_L  , 16   @ This value is in terms of 32-bit words.
.equ OTG_FS_HNPTXFSIZ_NPTXFD_M  , 0xFFFF @ Minimum value is 16
                                       @ Maximum value is 256
.equ OTG_FS_HNPTXFSIZ_NPTXFSA_N, 0     @ Bits 15:0 NPTXFSA: Non-periodic transmit RAM start address
.equ OTG_FS_HNPTXFSIZ_NPTXFSA_L, 16    @ This field contains the memory start address for non-periodic transmit FIFO RAM.
.equ OTG_FS_HNPTXFSIZ_NPTXFSA_M, 0xFFFF
@.end

@.item OTG_FS_DIEPTXF0
.equ OTG_FS_DIEPTXF0_TX0FD_N, 16       @ Bits 31:16 TX0FD: Endpoint 0 TxFIFO depth
.equ OTG_FS_DIEPTXF0_TX0FD_L, 16       @ This value is in terms of 32-bit words.
.equ OTG_FS_DIEPTXF0_TX0FD_M, 0xFFFF   @ Minimum value is 16
                                       @ Maximum value is 256
.equ OTG_FS_DIEPTXF0_TXFSA_N, 0        @ Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address
.equ OTG_FS_DIEPTXF0_TXFSA_L, 16       @ This field contains the memory start address for the endpoint 0 transmit FIFO RAM.
.equ OTG_FS_DIEPTXF0_TXFSA_M, 0xFFFF
@.end

@.item OTG_FS_HNPTXSTS
.equ OTG_FS_HNPTXSTS_RSTVAL, 0x00080200 @ Reset value
.equ OTG_FS_HNPTXSTS_NPTXQTOP_N  , 24  @ Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue
.equ OTG_FS_HNPTXSTS_NPTXQTOP_L  , 7   @ Entry in the non-periodic Tx request queue that is currently being processed by the MAC.
                                       @ Bits 30:27: Channel/endpoint number
                                       @ Bits 26:25:
                                       @ – 00: IN/OUT token
                                       @ – 01: Zero-length transmit packet (device IN/host OUT)
                                       @ – 11: Channel halt command
                                       @ Bit 24: Terminate (last entry for selected channel/endpoint)
.equ OTG_FS_HNPTXSTS_NPTQXSAV_N  , 16  @ Bits 23:16 NPTQXSAV: Non-periodic transmit request queue space available
.equ OTG_FS_HNPTXSTS_NPTQXSAV_L  , 8   @ Indicates the amount of free space available in the non-periodic transmit request queue.
                                       @ This queue holds both IN and OUT requests in host mode. Device mode has only IN
                                       @ requests.
                                       @ 00: Non-periodic transmit request queue is full
                                       @ 01: 1 location available
                                       @ 10: 2 locations available
                                       @ bxn: n locations available (0  n  8)
                                       @ Others: Reserved
.equ OTG_FS_HNPTXSTS_NPTXFSAV_N  , 0   @ Bits 15:0 NPTXFSAV: Non-periodic TxFIFO space available
.equ OTG_FS_HNPTXSTS_NPTXFSAV_L  , 16  @ Indicates the amount of free space available in the non-periodic TxFIFO.
                                       @ Values are in terms of 32-bit words.
                                       @ 00: Non-periodic TxFIFO is full
                                       @ 01: 1 word available
                                       @ 10: 2 words available
                                       @ 0xn: n words available (where 0  n  256)
                                       @ Others: Reserved
@.end

@.item OTG_FS_GCCFG
.equ OTG_FS_GCCFG_NOVBUSSENS  , 1<<21  @ Bit 21 NOVBUSSENS: VBUS sensing disable option
                                       @ When this bit is set, VBUS is considered internally to be always at VBUS valid level (5 V). This
                                       @ option removes the need for a dedicated VBUS pad, and leave this pad free to be used for
                                       @ other purposes such as a shared functionality. VBUS connection can be remapped on
                                       @ another general purpose input pad and monitored by software.
                                       @ This option is only suitable for host-only or device-only applications.
                                       @ 0: VBUS sensing available by hardware
                                       @ 1: VBUS sensing not available by hardware.
.equ OTG_FS_GCCFG_SOFOUTEN  , 1<<20    @ Bit 20 SOFOUTEN: SOF output enable
                                       @ 0: SOF pulse not available on PAD (OTG_FS_SOF)
                                       @ 1: SOF pulse available on PAD (OTG_FS_SOF)
.equ OTG_FS_GCCFG_VBUSBSEN  , 1<<19    @ Bit 19 VBUSBSEN: Enable the VBUS sensing “B” device
                                       @ 0: VBUS sensing “B” disabled
                                       @ 1: VBUS sensing “B” enabled
.equ OTG_FS_GCCFG_VBUSASEN  , 1<<18    @ Bit 18 VBUSASEN: Enable the VBUS sensing “A” device
                                       @ 0: VBUS sensing “A” disabled
                                       @ 1: VBUS sensing “A” enabled
.equ OTG_FS_GCCFG_PWRDWN  , 1<<16      @ Bit 16 PWRDWN: Power down
                                       @ Used to activate the transceiver in transmission/reception
                                       @ 0: Power down active
                                       @ 1: Power down deactivated (“Transceiver active”)
@.end

@.item OTG_FS_CID
.equ OTG_FS_CID_RSTVAL, 0x00001200
@.end

@.item OTG_FS_HPTXFSIZ
.equ OTG_FS_HPTXFSIZ_RSTVAL, 0x02000400
.equ OTG_FS_HPTXFSIZ_PTXFD_N  , 16     @ Bits 31:16 PTXFD: Host periodic TxFIFO depth
.equ OTG_FS_HPTXFSIZ_PTXFD_L  , 16     @ This value is in terms of 32-bit words.
.equ OTG_FS_HPTXFSIZ_PTXFD_M  , 0xFFFF @ Minimum value is 16
.equ OTG_FS_HPTXFSIZ_PTXSA_N  , 0      @ Bits 15:0 PTXSA: Host periodic TxFIFO start address
.equ OTG_FS_HPTXFSIZ_PTXSA_L  , 16     @ The power-on reset value of this register is the sum of the largest Rx data FIFO depth and
.equ OTG_FS_HPTXFSIZ_PTXSA_M  , 0xFFFF @ largest non-periodic Tx data FIFO depth.
@.end

@.item OTG_FS_DIEPTXF1 OTG_FS_DIEPTXF2 OTG_FS_DIEPTXF3
.equ OTG_FS_DIEPTXFx_RSTVAL , 0x02000200
.equ OTG_FS_DIEPTXFx_INEPTXFD_N  , 16  @ Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth
.equ OTG_FS_DIEPTXFx_INEPTXFD_L  , 16  @ This value is in terms of 32-bit words.
.equ OTG_FS_DIEPTXFx_INEPTXFD_M  , 0xFFFF  @ Minimum value is 16
                                       @ The power-on reset value of this register is specified as the largest IN endpoint FIFO
                                       @ number depth.
.equ OTG_FS_DIEPTXFx_INEPTXSA_N  , 0   @ Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address
.equ OTG_FS_DIEPTXFx_INEPTXSA_L  , 16  @ This field contains the memory start address for IN endpoint transmit FIFOx. The address
.equ OTG_FS_DIEPTXFx_INEPTXSA_M  , 0xFFFF @ must be aligned with a 32-bit memory location.
@.end

@.item OTG_FS_HCFG
.equ OTG_FS_HCFG_FSLSS   , 1<<2        @ Bit 2 FSLSS: FS- and LS-only support
                                       @ The application uses this bit to control the core’s enumeration speed. Using this bit, the
                                       @ application can make the core enumerate as an FS host, even if the connected device
                                       @ supports HS traffic. Do not make changes to this field after initial programming.
                                       @ 1: FS/LS-only, even if the connected device can support HS (read-only)
.equ OTG_FS_HCFG_FSLSPCS_N   , 0       @ Bits 1:0 FSLSPCS: FS/LS PHY clock select
.equ OTG_FS_HCFG_FSLSPCS_L   , 2       @ When the core is in FS host mode
.equ OTG_FS_HCFG_FSLSPCS_M   , 3       @ 01: PHY clock is running at 48 MHz
                                       @ Others: Reserved
                                       @ When the core is in LS host mode
                                       @ 00: Reserved
                                       @ 01: Select 48 MHz PHY clock frequency
                                       @ 10: Select 6 MHz PHY clock frequency
                                       @ 11: Reserved
                                 @ Note: The FSLSPCS must be set on a connection event according to the speed of the
                                       @ connected device (after changing this bit, a software reset must be performed)
@.end

@.item  OTG_FS_HFIR
.equ OTG_FS_HFIR_RSTVAL, 0x0000EA60
.equ OTG_FS_HFIR_FRIVL_N , 0           @ Bits 15:0 FRIVL: Frame interval
.equ OTG_FS_HFIR_FRIVL_L , 16          @ The value that the application programs to this field specifies the interval between two
.equ OTG_FS_HFIR_FRIVL_M , 0xFFFF      @ consecutive SOFs (FS) or Keep-Alive tokens (LS). This field contains the number of PHY
                                       @ clocks that constitute the required frame interval. The application can write a value to this
                                       @ register only after the Port enable bit of the host port control and status register (PENA bit in
                                       @ OTG_FS_HPRT) has been set. If no value is programmed, the core calculates the value
                                       @ based on the PHY clock specified in the FS/LS PHY Clock Select field of the host
                                       @ configuration register (FSLSPCS in OTG_FS_HCFG). Do not change the value of this field
                                       @ after the initial configuration.
                                       @ – Frame interval = 1 ms × (FRIVL - 1)
@.end

@.item  OTG_FS_HFNUM
.equ OTG_FS_HFNUM_RSTVAL, 0x3FFF
.equ OTG_FS_HFNUM_FTREM_N   , 16       @ Bits 31:16 FTREM: Frame time remaining
.equ OTG_FS_HFNUM_FTREM_L   , 16       @ Indicates the amount of time remaining in the current frame, in terms of PHY clocks. This
.equ OTG_FS_HFNUM_FTREM_M   , 0xFFFF   @ field decrements on each PHY clock. When it reaches zero, this field is reloaded with the
                                       @ value in the Frame interval register and a new SOF is transmitted on the USB.
.equ OTG_FS_HFNUM_FRNUM_N   , 0        @ Bits 15:0 FRNUM: Frame number
.equ OTG_FS_HFNUM_FRNUM_L   , 16       @ This field increments when a new SOF is transmitted on the USB, and is cleared to 0 when
.equ OTG_FS_HFNUM_FRNUM_M   , 0xFFFF   @ it reaches 0x3FFF.
@.end

@.item OTG_FS_HPTXSTS
.equ OTG_FS_HPTXSTS_RSTVAL, 0x00080100
.equ OTG_FS_HPTXSTS_PTXQTOP_N, 24      @ Bits 31:24 PTXQTOP: Top of the periodic transmit request queue
.equ OTG_FS_HPTXSTS_PTXQTOP_L, 8       @ This indicates the entry in the periodic Tx request queue that is currently being processed by
.equ OTG_FS_HPTXSTS_PTXQTOP_M, 0xFF    @ the MAC.
                                       @ This register is used for debugging.
                                       @ Bit 31: Odd/Even frame
                                       @ – 0: send in even frame
                                       @ – 1: send in odd frame
                                       @ Bits 30:27: Channel/endpoint number
                                       @ Bits 26:25: Type
                                       @ – 00: IN/OUT
                                       @ – 01: Zero-length packet
                                       @ – 11: Disable channel command
                                       @ Bit 24: Terminate (last entry for the selected channel/endpoint)
.equ OTG_FS_HPTXSTS_PTXQSAV_N, 16      @ Bits 23:16 PTXQSAV: Periodic transmit request queue space available
.equ OTG_FS_HPTXSTS_PTXQSAV_L, 8       @ Indicates the number of free locations available to be written in the periodic transmit request
.equ OTG_FS_HPTXSTS_PTXQSAV_M, 0xFF    @ queue. This queue holds both IN and OUT requests.
                                       @ 00: Periodic transmit request queue is full
                                       @ 01: 1 location available
                                       @ 10: 2 locations available
                                       @ bxn: n locations available (0  n  8)
                                       @ Others: Reserved
.equ OTG_FS_HPTXSTS_PTXFSAVL_N, 0      @ Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available
.equ OTG_FS_HPTXSTS_PTXFSAVL_L, 16     @ Indicates the number of free locations available to be written to in the periodic TxFIFO.
.equ OTG_FS_HPTXSTS_PTXFSAVL_M, 0xFFFF @ Values are in terms of 32-bit words
                                       @ 0000: Periodic TxFIFO is full
                                       @ 0001: 1 word available
                                       @ 0010: 2 words available
                                       @ bxn: n words available (where 0  n  PTXFD)
                                       @ Others: Reserved
@.end

@.item OTG_FS_HAINT
.equ OTG_FS_HAINT_HAINT_N , 0          @ Bits 15:0 HAINT: Channel interrupts
.equ OTG_FS_HAINT_HAINT_L , 16         @ One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
.equ OTG_FS_HAINT_HAINT_M , 0xFFFF
@.end

@.item OTG_FS_HAINTMSK
.equ OTG_FS_HAINTMSK_HAINTM_N , 0      @ Bits 15:0 HAINTM: Channel interrupt mask
.equ OTG_FS_HAINTMSK_HAINTM_L , 16     @ 0: Masked interrupt
.equ OTG_FS_HAINTMSK_HAINTM_M , 0xFFFF @ 1: Unmasked interrupt
                                       @ One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
@.end

@.item OTG_FS_HPRT
.equ OTG_FS_HPRT_PSPD_N , 17            @ Bits 18:17 PSPD: Port speed
.equ OTG_FS_HPRT_PSPD_L , 2             @ Indicates the speed of the device attached to this port.
.equ OTG_FS_HPRT_PSPD_M , 3             @ 01: Full speed
                                        @ 10: Low speed
                                        @ 11: Reserved
.equ OTG_FS_HPRT_PTCTL_N , 13           @ Bits 16:13 PTCTL: Port test control
.equ OTG_FS_HPRT_PTCTL_L , 4            @ The application writes a nonzero value to this field to put the port into a Test mode, and the
.equ OTG_FS_HPRT_PTCTL_M , 0xF          @ corresponding pattern is signaled on the port.
                                        @ 0000: Test mode disabled
                                        @ 0001: Test_J mode
                                        @ 0010: Test_K mode
                                        @ 0011: Test_SE0_NAK mode
                                        @ 0100: Test_Packet mode
                                        @ 0101: Test_Force_Enable
                                        @ Others: Reserved
.equ OTG_FS_HPRT_PPWR , 1<<12           @ Bit 12 PPWR: Port power
                                        @ The application uses this field to control power to this port, and the core clears this bit on an
                                        @ overcurrent condition.
                                        @ 0: Power off
                                        @ 1: Power on
.equ OTG_FS_HPRT_PLSTS_N , 10           @ Bits 11:10 PLSTS: Port line status
.equ OTG_FS_HPRT_PLSTS_L , 2            @ Indicates the current logic level USB data lines
.equ OTG_FS_HPRT_PLSTS_M , 3            @ Bit 10: Logic level of OTG_FS_DP
                                        @ Bit 11: Logic level of OTG_FS_DM
.equ OTG_FS_HPRT_PRST , 1<<8            @ Bit 8 PRST: Port reset
                                        @ When the application sets this bit, a reset sequence is started on this port. The application
                                        @ must time the reset period and clear this bit after the reset sequence is complete.
                                        @ 0: Port not in reset
                                        @ 1: Port in reset
                                        @ The application must leave this bit set for a minimum duration of at least 10 ms to start a
                                        @ reset on the port. The application can leave it set for another 10 ms in addition to the
                                        @ required minimum duration, before clearing the bit, even though there is no maximum limit
                                        @ set by the USB standard
.equ OTG_FS_HPRT_PSUSP , 1<<7           @ Bit 7 PSUSP: Port suspend
                                        @ The application sets this bit to put this port in Suspend mode. The core only stops sending
                                        @ SOFs when this is set. To stop the PHY clock, the application must set the Port clock stop
                                        @ bit, which asserts the suspend input pin of the PHY.
                                        @ The read value of this bit reflects the current suspend status of the port. This bit is cleared
                                        @ by the core after a remote wakeup signal is detected or the application sets the Port reset bit
                                        @ or Port resume bit in this register or the Resume/remote wakeup detected interrupt bit or
                                        @ Disconnect detected interrupt bit in the Core interrupt register (WKUINT or DISCINT in
                                        @ OTG_FS_GINTSTS, respectively).
                                        @ 0: Port not in Suspend mode
                                        @ 1: Port in Suspend mode
.equ OTG_FS_HPRT_PRES , 1<<6            @ Bit 6 PRES: Port resume
                                        @ The application sets this bit to drive resume signaling on the port. The core continues to
                                        @ drive the resume signal until the application clears this bit.
                                        @ If the core detects a USB remote wakeup sequence, as indicated by the Port
                                        @ resume/remote wakeup detected interrupt bit of the Core interrupt register (WKUINT bit in
                                        @ OTG_FS_GINTSTS), the core starts driving resume signaling without application
                                        @ intervention and clears this bit when it detects a disconnect condition. The read value of this
                                        @ bit indicates whether the core is currently driving resume signaling.
                                        @ 0: No resume driven
                                        @ 1: Resume driven
.equ OTG_FS_HPRT_POCCHNG , 1<<5         @ Bit 5 POCCHNG: Port overcurrent change
                                        @ The core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register
                                        @ changes.
.equ OTG_FS_HPRT_POCA , 1<<4            @ Bit 4 POCA: Port overcurrent active
                                        @ Indicates the overcurrent condition of the port.
                                        @ 0: No overcurrent condition
                                        @ 1: Overcurrent condition
.equ OTG_FS_HPRT_PENCHNG , 1<<3         @ Bit 3 PENCHNG: Port enable/disable change
                                        @ The core sets this bit when the status of the Port enable bit 2 in this register changes.
.equ OTG_FS_HPRT_PENA , 1<<2            @ Bit 2 PENA: Port enable
                                        @ A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent
                                        @ condition, a disconnect condition, or by the application clearing this bit. The application
                                        @ cannot set this bit by a register write. It can only clear it to disable the port. This bit does not
                                        @ trigger any interrupt to the application.
                                        @ 0: Port disabled
                                        @ 1: Port enabled
.equ OTG_FS_HPRT_PCDET , 1<<1           @ Bit 1 PCDET: Port connect detected
                                        @ The core sets this bit when a device connection is detected to trigger an interrupt to the
                                        @ application using the host port interrupt bit in the Core interrupt register (HPRTINT bit in
                                        @ OTG_FS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.
.equ OTG_FS_HPRT_PCSTS , 1              @ Bit 0 PCSTS: Port connect status
                                        @ 0: No device is attached to the port
                                        @ 1: A device is attached to the port
@.end

@.item OTG_FS_HCCHAR0 OTG_FS_HCCHAR1 OTG_FS_HCCHAR2 OTG_FS_HCCHAR3 OTG_FS_HCCHAR4 OTG_FS_HCCHAR5 OTG_FS_HCCHAR6 OTG_FS_HCCHAR7
.equ OTG_FS_HCCHARx_CHENA  , 1<<31      @ Bit 31 CHENA: Channel enable
                                        @ This field is set by the application and cleared by the OTG host.
                                        @ 0: Channel disabled
                                        @ 1: Channel enabled
.equ OTG_FS_HCCHARx_CHDIS  , 1<<30      @ Bit 30 CHDIS: Channel disable
                                        @ The application sets this bit to stop transmitting/receiving data on a channel, even before
                                        @ the transfer for that channel is complete. The application must wait for the Channel disabled
                                        @ interrupt before treating the channel as disabled.
.equ OTG_FS_HCCHARx_ODDFRM  , 1<<29     @ Bit 29 ODDFRM: Odd frame
                                        @ This field is set (reset) by the application to indicate that the OTG host must perform a
                                        @ transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt)
                                        @ transactions.
                                        @ 0: Even frame
                                        @ 1: Odd frame
.equ OTG_FS_HCCHARx_DAD_N  , 22         @ Bits 28:22 DAD: Device address
.equ OTG_FS_HCCHARx_DAD_L  , 7          @ This field selects the specific device serving as the data source or sink.
.equ OTG_FS_HCCHARx_MCNT_N  , 20        @ Bits 21:20 MCNT: Multicount
.equ OTG_FS_HCCHARx_MCNT_L  , 2         @ This field indicates to the host the number of transactions that must be executed per frame
                                        @ for this periodic endpoint. For non-periodic transfers, this field is not used
                                        @ 00: Reserved. This field yields undefined results
                                        @ 01: 1 transaction
                                        @ 10: 2 transactions per frame to be issued for this endpoint
                                        @ 11: 3 transactions per frame to be issued for this endpoint
                                  @ Note: This field must be set to at least 01.
.equ OTG_FS_HCCHARx_EPTYP_N  , 18       @ Bits 19:18 EPTYP: Endpoint type
.equ OTG_FS_HCCHARx_EPTYP_L  , 2        @ Indicates the transfer type selected.
                                        @ 00: Control
                                        @ 01: Isochronous
                                        @ 10: Bulk
                                        @ 11: Interrupt
.equ OTG_FS_HCCHARx_LSDEV  , 1<<17      @ Bit 17 LSDEV: Low-speed device
                                        @ This field is set by the application to indicate that this channel is communicating to a low-
                                        @ speed device.
.equ OTG_FS_HCCHARx_EPDIR  , 1<<15      @ Bit 15 EPDIR: Endpoint direction
                                        @ Indicates whether the transaction is IN or OUT.
                                        @ 0: OUT
                                        @ 1: IN
.equ OTG_FS_HCCHARx_EPNUM_N  , 11       @ Bits 14:11 EPNUM: Endpoint number
.equ OTG_FS_HCCHARx_EPNUM_L  , 4        @ Indicates the endpoint number on the device serving as the data source or sink.
.equ OTG_FS_HCCHARx_MPSIZ_N  , 0        @ Bits 10:0 MPSIZ: Maximum packet size
.equ OTG_FS_HCCHARx_MPSIZ_L  , 11       @ Indicates the maximum packet size of the associated endpoint.
@.end

@.item OTG_FS_HCINT_OFS
.equ OTG_FS_HCINTx_DTERR , 1<<10        @ Bit 10 DTERR: Data toggle error
.equ OTG_FS_HCINTx_FRMOR , 1<<9         @ Bit 9 FRMOR: Frame overrun
.equ OTG_FS_HCINTx_BBERR , 1<<8         @ Bit 8 BBERR: Babble error
.equ OTG_FS_HCINTx_TXERR , 1<<7         @ Bit 7 TXERR: Transaction error
                                        @ Indicates one of the following errors occurred on the USB.
                                        @ CRC check failure
                                        @ Timeout
                                        @ Bit stuff error
                                        @ False EOP
.equ OTG_FS_HCINTx_ACK , 1<<5           @ Bit 5 ACK: ACK response received/transmitted interrupt
.equ OTG_FS_HCINTx_NAK , 1<<4           @ Bit 4 NAK: NAK response received interrupt
.equ OTG_FS_HCINTx_STALL , 1<<3         @ Bit 3 STALL: STALL response received interrupt
.equ OTG_FS_HCINTx_CHH , 1<<1           @ Bit 1 CHH: Channel halted
                                        @ Indicates the transfer completed abnormally either because of any USB transaction error or
                                        @ in response to disable request by the application.
.equ OTG_FS_HCINTx_XFRC , 1             @ Bit 0 XFRC: Transfer completed
                                        @ Transfer completed normally without any errors.
@.end

@.item OTG_FS_HCINTMSK0 OTG_FS_HCINTMSK1 OTG_FS_HCINTMSK2 OTG_FS_HCINTMSK3 OTG_FS_HCINTMSK4 OTG_FS_HCINTMSK5 OTG_FS_HCINTMSK6 OTG_FS_HCINTMSK7
.equ OTG_FS_HCINTMSKx_DTERRM , 1<<10    @ Bit 10 DTERRM: Data toggle error mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_FRMORM , 1<<9     @ Bit 9 FRMORM: Frame overrun mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_BBERRM , 1<<8     @ Bit 8 BBERRM: Babble error mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_TXERRM , 1<<7     @ Bit 7 TXERRM: Transaction error mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_ACKM , 1<<5       @ Bit 5 ACKM: ACK response received/transmitted interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_NAKM , 1<<4       @ Bit 4 NAKM: NAK response received interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_STALLM , 1<<3     @ Bit 3 STALLM: STALL response received interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_CHHM , 1<<1       @ Bit 1 CHHM: Channel halted mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_HCINTMSKx_XFRCM , 1         @ Bit 0 XFRCM: Transfer completed mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
@.end

@.item OTG_FS_HCTSIZ0 OTG_FS_HCTSIZ1 OTG_FS_HCTSIZ2 OTG_FS_HCTSIZ3 OTG_FS_HCTSIZ4 OTG_FS_HCTSIZ5 OTG_FS_HCTSIZ6 OTG_FS_HCTSIZ7
.equ OTG_FS_HCTSIZx_DPID_N  , 29        @ Bits 30:29 DPID: Data PID
.equ OTG_FS_HCTSIZx_DPID_L  , 2         @ The application programs this field with the type of PID to use for the initial transaction. The
                                        @ host maintains this field for the rest of the transfer.
                                        @ 00: DATA0
                                        @ 01: DATA2
                                        @ 10: DATA1
                                        @ 11: MDATA (non-control)/SETUP (control)
.equ OTG_FS_HCTSIZx_PKTCNT_N  , 19      @ Bits 28:19 PKTCNT: Packet count
.equ OTG_FS_HCTSIZx_PKTCNT_L  , 10      @ This field is programmed by the application with the expected number of packets to be
                                        @ transmitted (OUT) or received (IN).
                                        @ The host decrements this count on every successful transmission or reception of an OUT/IN
                                        @ packet. Once this count reaches zero, the application is interrupted to indicate normal
                                        @ completion.
.equ OTG_FS_HCTSIZx_XFRSIZ_N  , 0       @ Bits 18:0 XFRSIZ: Transfer size
.equ OTG_FS_HCTSIZx_XFRSIZ_L  , 19      @ For an OUT, this field is the number of data bytes the host sends during the transfer.
                                        @ For an IN, this field is the buffer size that the application has reserved for the transfer. The
                                        @ application is expected to program this field as an integer multiple of the maximum packet
                                        @ size for IN transactions (periodic and non-periodic).
@.END

@.item OTG_FS_DCFG
.EQU  OTG_FS_DCFG_RSTVAL, 0x02200000
.equ OTG_FS_DCFG_PFIVL_N , 11           @ Bits 12:11 PFIVL: Periodic frame interval
.equ OTG_FS_DCFG_PFIVL_L , 2            @ Indicates the time within a frame at which the application must be notified using the end of
                                        @ periodic frame interrupt. This can be used to determine if all the isochronous traffic for that
                                        @ frame is complete.
                                        @ 00: 80% of the frame interval
                                        @ 01: 85% of the frame interval
                                        @ 10: 90% of the frame interval
                                        @ 11: 95% of the frame interval
.equ OTG_FS_DCFG_DAD_N , 4              @ Bits 10:4 DAD: Device address
.equ OTG_FS_DCFG_DAD_L , 7              @ The application must program this field after every SetAddress control command.
.equ OTG_FS_DCFG_NZLSOHSK , 1<<2        @ Bit 2 NZLSOHSK: Non-zero-length status OUT handshake
                                        @ The application can use this field to select the handshake the core sends on receiving a
                                        @ nonzero-length data packet during the OUT transaction of a control transfer’s Status stage.
                                        @ 1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send
                                        @ the received OUT packet to the application.
                                        @ 0: Send the received OUT packet to the application (zero-length or nonzero-length) and
                                        @ send a handshake based on the NAK and STALL bits for the endpoint in the Device
                                        @ endpoint control register.
.equ OTG_FS_DCFG_DSPD_N , 0             @ Bits 1:0 DSPD: Device speed
.equ OTG_FS_DCFG_DSPD_L , 2             @ Indicates the speed at which the application requires the core to enumerate, or the
                                        @ maximum speed the application can support. However, the actual bus speed is determined
                                        @ only after the chirp sequence is completed, and is based on the speed of the USB host to
                                        @ which the core is connected.
                                        @ 00: Reserved
                                        @ 01: Reserved
                                        @ 10: Reserved
                                        @ 11: Full speed (USB 1.1 transceiver clock is 48 MHz)
@.end

@.item OTG_FS_DCTL
.equ OTG_FS_DCTL_POPRGDNE , 1<<11       @ Bit 11 POPRGDNE: Power-on programming done
                                        @ The application uses this bit to indicate that register programming is completed after a
                                        @ wakeup from power down mode.
.equ OTG_FS_DCTL_CGONAK  , 1<<10        @ Bit 10 CGONAK: Clear global OUT NAK
                                        @ Writing 1 to this field clears the Global OUT NAK.
.equ OTG_FS_DCTL_SGONAK  , 1<<9         @  Bit 9 SGONAK: Set global OUT NAK
                                        @ Writing 1 to this field sets the Global OUT NAK.
                                        @ The application uses this bit to send a NAK handshake on all OUT endpoints.
                                        @ The application must set the this bit only after making sure that the Global OUT NAK
                                        @ effective bit in the Core interrupt register (GONAKEFF bit in OTG_FS_GINTSTS) is cleared.
.equ OTG_FS_DCTL_CGINAK  , 1<<8         @ Bit 8 CGINAK: Clear global IN NAK
                                        @ Writing 1 to this field clears the Global IN NAK.
.equ OTG_FS_DCTL_SGINAK  , 1<<7         @ Bit 7 SGINAK: Set global IN NAK
                                        @ Writing 1 to this field sets the Global non-periodic IN NAK. The application uses this bit to
                                        @ send a NAK handshake on all non-periodic IN endpoints.
                                        @ The application must set this bit only after making sure that the Global IN NAK effective bit
                                        @ in the Core interrupt register (GINAKEFF bit in OTG_FS_GINTSTS) is cleared.
.equ OTG_FS_DCTL_TCTL_N  , 4            @ Bits 6:4 TCTL: Test control
.equ OTG_FS_DCTL_TCTL_L  , 3            @ 000: Test mode disabled
                                        @ 001: Test_J mode
                                        @ 010: Test_K mode
                                        @ 011: Test_SE0_NAK mode
                                        @ 100: Test_Packet mode
                                        @ 101: Test_Force_Enable
                                        @ Others: Reserved
.equ OTG_FS_DCTL_GONSTS  , 1<<3         @ Bit 3 GONSTS: Global OUT NAK status
                                        @ 0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
                                        @ 1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK
                                        @ handshake on all packets, except on SETUP transactions. All isochronous OUT packets are
                                        @ dropped.
.equ OTG_FS_DCTL_GINSTS  , 1<<2         @ Bit 2 GINSTS: Global IN NAK status
                                        @ 0: A handshake is sent out based on the data availability in the transmit FIFO.
                                        @ 1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data
                                        @ availability in the transmit FIFO.
.equ OTG_FS_DCTL_SDIS  , 1<<1           @ Bit 1 SDIS: Soft disconnect
                                        @ The application uses this bit to signal the USB OTG core to perform a soft disconnect. As
                                        @ long as this bit is set, the host does not see that the device is connected, and the device
                                        @ does not receive signals on the USB. The core stays in the disconnected state until the
                                        @ application clears this bit.
                                        @ 0: Normal operation. When this bit is cleared after a soft disconnect, the core generates a
                                        @ device connect event to the USB host. When the device is reconnected, the USB host
                                        @ restarts device enumeration.
                                        @ 1: The core generates a device disconnect event to the USB host.
.equ OTG_FS_DCTL_RWUSIG  , 1            @ Bit 0 RWUSIG: Remote wakeup signaling
                                        @ When the application sets this bit, the core initiates remote signaling to wake up the USB
                                        @ host. The application must set this bit to instruct the core to exit the Suspend state. As
                                        @ specified in the USB 2.0 specification, the application must clear this bit 1 ms to 15 ms after
                                        @ setting it.
@.end

@.item OTG_FS_DSTS
.equ OTG_FS_DSTS_FNSOF_N   , 8          @ Bits 21:8 FNSOF: Frame number of the received SOF
.equ OTG_FS_DSTS_FNSOF_L   , 14
.equ OTG_FS_DSTS_EERR  , 1<<3           @ Bit 3 EERR: Erratic error
                                        @ The core sets this bit to report any erratic errors.
                                        @ Due to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is
                                        @ generated to the application with Early suspend bit of the OTG_FS_GINTSTS register
                                        @ (ESUSP bit in OTG_FS_GINTSTS). If the early suspend is asserted due to an erratic error,
                                        @ the application can only perform a soft disconnect recover.
.equ OTG_FS_DSTS_ENUMSPD_N  , 1         @ Bits 2:1 ENUMSPD: Enumerated speed
.equ OTG_FS_DSTS_ENUMSPD_L  , 2         @ Indicates the speed at which the OTG_FS controller has come up after speed detection
                                        @ through a chirp sequence.
                                        @ 01: Reserved
                                        @ 10: Reserved
                                        @ 11: Full speed (PHY clock is running at 48 MHz)
                                        @ Others: reserved
.equ OTG_FS_DSTS_SUSPSTS  , 1           @ Bit 0 SUSPSTS: Suspend status
                                        @ In device mode, this bit is set as long as a Suspend condition is detected on the USB. The
                                        @ core enters the Suspended state when there is no activity on the USB data lines for a period
                                        @ of 3 ms. The core comes out of the suspend:
                                        @ – When there is an activity on the USB data lines
                                        @ – When the application writes to the Remote wakeup signaling bit in the OTG_FS_DCTL
                                        @ register (RWUSIG bit in OTG_FS_DCTL).
@.end

@.item  OTG_FS_DIEPMSK
.equ OTG_FS_DIEPMSK_NAKM  , 1<<13       @ Bit 13 NAKM: NAK interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DIEPMSK_INEPNEM  , 1<<6     @ Bit 6 INEPNEM: IN endpoint NAK effective mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DIEPMSK_INEPNMM  , 1<<5     @ Bit 5 INEPNMM: IN token received with EP mismatch mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DIEPMSK_ITTXFEMSK  , 1<<4   @ Bit 4 ITTXFEMSK: IN token received when TxFIFO empty mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DIEPMSK_EPDM  , 1<<1        @ Bit 1 EPDM: Endpoint disabled interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DIEPMSK_XFRCM  , 1          @ Bit 0 XFRCM: Transfer completed interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
@.end

@.item OTG_FS_DOEPMSK
.equ OTG_FS_DOEPMSK_NAKMSK  , 1<<13     @ Bit 13 NAKMSK: NAK interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_BERRM  , 1<<12      @ Bit 12 BERRM: Babble error interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_OUTPKTERRM , 1<<8   @ Bit 8 OUTPKTERRM: Out packet error mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_STSPHSRXM  , 1<<5   @ Bit 5 STSPHSRXM: Status phase received for control write mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_OTEPDM  , 1<<4      @ Bit 4 OTEPDM: OUT token received when endpoint disabled mask
                                        @ Applies to control OUT endpoints only.
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_STUPM  , 1<<3       @ Bit 3 STUPM: SETUP phase done mask
                                        @ Applies to control endpoints only.
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_EPDM  , 1<<1        @ Bit 1 EPDM: Endpoint disabled interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DOEPMSK_XFRCM  , 1          @ Bit 0 XFRCM: Transfer completed interrupt mask
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
@.end

@.item OTG_FS_DAINT
.equ OTG_FS_DAINT_OEPINT_N  , 16        @ Bits 31:16 OEPINT: OUT endpoint interrupt bits
.equ OTG_FS_DAINT_OEPINT_L  , 16        @ One bit per OUT endpoint:
                                        @ Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.
.equ OTG_FS_DAINT_IEPINT_N  , 0         @ Bits 15:0 IEPINT: IN endpoint interrupt bits
.equ OTG_FS_DAINT_IEPINT_L  , 16        @ One bit per IN endpoint:
                                        @ Bit 0 for IN endpoint 0, bit 3 for endpoint 3.
@.end

@.item OTG_FS_DAINTMSK
.equ OTG_FS_DAINTMSK_OEPM_N  , 16       @ Bits 31:16 OEPM: OUT EP interrupt mask bits
.equ OTG_FS_DAINTMSK_OEPM_L  , 16       @ One per OUT endpoint:
                                        @ Bit 16 for OUT EP 0, bit 19 for OUT EP 3
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
.equ OTG_FS_DAINTMSK_IEPM_N   , 0       @ Bits 15:0 IEPM: IN EP interrupt mask bits
.equ OTG_FS_DAINTMSK_IEPM_L   , 16      @ One bit per IN endpoint:
                                        @ Bit 0 for IN EP 0, bit 3 for IN EP 3
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
@.end

@.item OTG_FS_DVBUSDIS
.equ OTG_FS_DVBUSDIS_RSTVAL  , 0x000017D7
.equ OTG_FS_DVBUSDIS_VBUSDT_N  , 0      @ Bits 15:0 VBUSDT: Device VBUS discharge time
.equ OTG_FS_DVBUSDIS_VBUSDT_L  , 16     @ Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals:
                                        @ VBUS discharge time in PHY clocks / 1 024
                                        @ Depending on your VBUS load, this value may need adjusting.
@.end

@.item OTG_FS_DVBUSPULSE
.equ OTG_FS_DVBUSPULSE_RSTVAL, 0x000005B8
.equ OTG_FS_DVBUSPULSE_DVBUSP_N  , 0    @ Bits 11:0 DVBUSP: Device VBUS pulsing time
.equ OTG_FS_DVBUSPULSE_DVBUSP_L  , 12   @ Specifies the VBUS pulsing time during SRP. This value equals:
                                        @ VBUS pulsing time in PHY clocks / 1 024
@.end

@.item OTG_FS_DIEPEMPMSK
.equ OTG_FS_DIEPEMPMSK_INEPTXFEM_N , 0  @ Bits 15:0 INEPTXFEM: IN EP Tx FIFO empty interrupt mask bits
.equ OTG_FS_DIEPEMPMSK_INEPTXFEM_L , 16 @ These bits act as mask bits for OTG_FS_DIEPINTx.
                                        @ TXFE interrupt one bit per IN endpoint:
                                        @ Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3
                                        @ 0: Masked interrupt
                                        @ 1: Unmasked interrupt
@.end

@.item OTG_FS_DIEPCTL0
.equ OTG_FS_DIEPCTL0_EPENA  , 1<<31     @ Bit 31 EPENA: Endpoint enable
                                        @ The application sets this bit to start transmitting data on the endpoint 0.
                                        @ The core clears this bit before setting any of the following interrupts on this endpoint:
                                        @ – Endpoint disabled
                                        @ – Transfer completed
.equ OTG_FS_DIEPCTL0_EPDIS  , 1<<30     @ Bit 30 EPDIS: Endpoint disable
                                        @ The application sets this bit to stop transmitting data on an endpoint, even before the
                                        @ transfer for that endpoint is complete. The application must wait for the Endpoint disabled
                                        @ interrupt before treating the endpoint as disabled. The core clears this bit before setting the
                                        @ Endpoint disabled interrupt. The application must set this bit only if Endpoint enable is
                                        @ already set for this endpoint.
.equ OTG_FS_DIEPCTL0_SNAK  , 1<<27      @ Bit 27 SNAK: Set NAK
                                        @ A write to this bit sets the NAK bit for the endpoint.
                                        @ Using this bit, the application can control the transmission of NAK handshakes on an
                                        @ endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on
                                        @ that endpoint.
.equ OTG_FS_DIEPCTL0_CNAK  , 1<<26      @ Bit 26 CNAK: Clear NAK
                                        @ A write to this bit clears the NAK bit for the endpoint.
.equ OTG_FS_DIEPCTL0_TXFNUM_N  , 22     @ Bits 25:22 TXFNUM: TxFIFO number
.equ OTG_FS_DIEPCTL0_TXFNUM_L  , 4      @ This value is set to the FIFO number that is assigned to IN endpoint 0.
.equ OTG_FS_DIEPCTL0_STALL  , 1<<21     @ Bit 21 STALL: STALL handshake
                                        @ The application can only set this bit, and the core clears it when a SETUP token is received
                                        @ for this endpoint. If a NAK bit, a Global IN NAK or Global OUT NAK is set along with this bit,
                                        @ the STALL bit takes priority.
.equ OTG_FS_DIEPCTL0_EPTYP_N  , 18      @ Bits 19:18 EPTYP: Endpoint type
.equ OTG_FS_DIEPCTL0_EPTYP_L  , 2       @ Hardcoded to ‘00’ for control.
.equ OTG_FS_DIEPCTL0_NAKSTS  , 1<<17    @ Bit 17 NAKSTS: NAK status
                                        @ Indicates the following:
                                        @ 0: The core is transmitting non-NAK handshakes based on the FIFO status
                                        @ 1: The core is transmitting NAK handshakes on this endpoint.
                                        @ When this bit is set, either by the application or core, the core stops transmitting data, even
                                        @ if there are data available in the TxFIFO. Irrespective of this bit’s setting, the core always
                                        @ responds to SETUP data packets with an ACK handshake.
.equ OTG_FS_DIEPCTL0_USBAEP  , 1<<15    @ Bit 15 USBAEP: USB active endpoint
                                        @ This bit is always set to 1, indicating that control endpoint 0 is always active in all
                                        @ configurations and interfaces.
.equ OTG_FS_DIEPCTL0_MPSIZ_N  , 0       @ Bits 1:0 MPSIZ: Maximum packet size
.equ OTG_FS_DIEPCTL0_MPSIZ_L  , 2       @ The application must program this field with the maximum packet size for the current logical
                                        @ endpoint.
                                        @ 00: 64 bytes
                                        @ 01: 32 bytes
                                        @ 10: 16 bytes
                                        @ 11: 8 bytes
@.end

@.item OTG_FS_DIEPCTL1, OTG_FS_DIEPCTL2 OTG_FS_DIEPCTL3
.equ OTG_FS_DIEPCTLx_EPENA , 1<<31      @ Bit 31 EPENA: Endpoint enable
                                        @ The application sets this bit to start transmitting data on an endpoint.
                                        @ The core clears this bit before setting any of the following interrupts on this endpoint:
                                        @ – SETUP phase done
                                        @ – Endpoint disabled
                                        @ – Transfer completed
.equ OTG_FS_DIEPCTLx_EPDIS , 1<<30      @ Bit 30 EPDIS: Endpoint disable
                                        @ The application sets this bit to stop transmitting/receiving data on an endpoint, even before
                                        @ the transfer for that endpoint is complete. The application must wait for the Endpoint
                                        @ disabled interrupt before treating the endpoint as disabled. The core clears this bit before
                                        @ setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint
                                        @ enable is already set for this endpoint.
.equ OTG_FS_DIEPCTLx_SODDFRM , 1<<29    @ Bit 29 SODDFRM: Set odd frame
                                        @ Applies to isochronous IN and OUT endpoints only.
                                        @ Writing to this field sets the Even/Odd frame (EONUM) field to odd frame.
.equ OTG_FS_DIEPCTLx_SD0PID , 1<<28     @ Bit 28 SD0PID: Set DATA0 PID
                                        @ Applies to interrupt/bulk IN endpoints only.
                                        @ Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0.
.equ OTG_FS_DIEPCTLx_SEVNFRM , 1<<28    @ SEVNFRM: Set even frame
                                        @ Applies to isochronous IN endpoints only.
                                        @ Writing to this field sets the Even/Odd frame (EONUM) field to even frame.
.equ OTG_FS_DIEPCTLx_SNAK , 1<<27       @ Bit 27 SNAK: Set NAK
                                        @ A write to this bit sets the NAK bit for the endpoint.
                                        @ Using this bit, the application can control the transmission of NAK handshakes on an
                                        @ endpoint. The core can also set this bit for OUT endpoints on a Transfer completed
                                        @ interrupt, or after a SETUP is received on the endpoint.
.equ OTG_FS_DIEPCTLx_CNAK , 1<<26       @ Bit 26 CNAK: Clear NAK
                                        @ A write to this bit clears the NAK bit for the endpoint.
.equ OTG_FS_DIEPCTLx_TXFNUM_N , 1<<22   @ Bits 25:22 TXFNUM: TxFIFO number
.equ OTG_FS_DIEPCTLx_TXFNUM_L , 4       @ These bits specify the FIFO number associated with this endpoint. Each active IN endpoint
                                        @ must be programmed to a separate FIFO number.
                                        @ This field is valid only for IN endpoints.
.equ OTG_FS_DIEPCTLx_STALL , 1<<21      @ Bit 21 STALL: STALL handshake
                                        @ Applies to non-control, non-isochronous IN endpoints only (access type is rw).
                                        @ The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK
                                        @ bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority.
                                        @ Only the application can clear this bit, never the core.
.equ OTG_FS_DIEPCTLx_EPTYP_N , 18       @ Bits 19:18 EPTYP: Endpoint type
.equ OTG_FS_DIEPCTLx_EPTYP_L , 2        @ This is the transfer type supported by this logical endpoint.
                                        @ 00: Control
                                        @ 01: Isochronous
                                        @ 10: Bulk
                                        @ 11: Interrupt
.equ OTG_FS_DIEPCTLx_NAKSTS , 1<<17     @ Bit 17 NAKSTS: NAK status
                                        @ It indicates the following:
                                        @ 0: The core is transmitting non-NAK handshakes based on the FIFO status.
                                        @ 1: The core is transmitting NAK handshakes on this endpoint.
                                        @ When either the application or the core sets this bit:
                                        @ For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint,
                                        @ even if there are data available in the TxFIFO.
                                        @ For isochronous IN endpoints: The core sends out a zero-length data packet, even if there
                                        @ are data available in the TxFIFO.
                                        @ Irrespective of this bit’s setting, the core always responds to SETUP data packets with an
                                        @ ACK handshake.
.equ OTG_FS_DIEPCTLx_EONUM , 1<<16      @ Bit 16 EONUM: Even/odd frame
                                        @ Applies to isochronous IN endpoints only.
                                        @ Indicates the frame number in which the core transmits/receives isochronous data for this
                                        @ endpoint. The application must program the even/odd frame number in which it intends to
                                        @ transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM
                                        @ fields in this register.
                                        @ 0: Even frame
                                        @ 1: Odd frame
.equ OTG_FS_DIEPCTLx_DPID , 1<<16       @ Bit 16 DPID: Endpoint data PID
                                        @ Applies to interrupt/bulk IN endpoints only.
                                        @ Contains the PID of the packet to be received or transmitted on this endpoint. The
                                        @ application must program the PID of the first packet to be received or transmitted on this
                                        @ endpoint, after the endpoint is activated. The application uses the SD0PID register field to
                                        @ program either DATA0 or DATA1 PID.
                                        @ 0: DATA0
                                        @ 1: DATA1
.equ OTG_FS_DIEPCTLx_USBAEP , 1<<15     @ Bit 15 USBAEP: USB active endpoint
                                        @ Indicates whether this endpoint is active in the current configuration and interface. The core
                                        @ clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving
                                        @ the SetConfiguration and SetInterface commands, the application must program endpoint
                                        @ registers accordingly and set this bit.
.equ OTG_FS_DIEPCTLx_MPSIZ_N , 0        @ Bits 10:0 MPSIZ: Maximum packet size
.equ OTG_FS_DIEPCTLx_MPSIZ_L , 11       @ The application must program this field with the maximum packet size for the current logical
.equ OTG_FS_DIEPCTLx_MPSIZ_M , 0b11111111111  @ endpoint. This value is in bytes.
@.end

@.item OTG_FS_DOEPCTL0
.equ OTG_FS_DOEPCTL0_RSTVAL, 0x8000
.equ OTG_FS_DOEPCTL0_EPENA   , 1<<31    @ Bit 31 EPENA: Endpoint enable
                                        @ The application sets this bit to start transmitting data on endpoint 0.
                                        @ The core clears this bit before setting any of the following interrupts on this endpoint:
                                        @ – SETUP phase done
                                        @ – Endpoint disabled
                                        @ – Transfer completed
.equ OTG_FS_DOEPCTL0_EPDIS   , 1<<30    @ Bit 30 EPDIS: Endpoint disable
                                        @ The application cannot disable control OUT endpoint 0.
.equ OTG_FS_DOEPCTL0_SNAK   , 1<<27     @ Bit 27 SNAK: Set NAK
                                        @ A write to this bit sets the NAK bit for the endpoint.
                                        @ Using this bit, the application can control the transmission of NAK handshakes on an
                                        @ endpoint. The core can also set this bit on a Transfer completed interrupt, or after a SETUP
                                        @ is received on the endpoint.
.equ OTG_FS_DOEPCTL0_CNAK   , 1<<26     @ Bit 26 CNAK: Clear NAK
                                        @ A write to this bit clears the NAK bit for the endpoint.
.equ OTG_FS_DOEPCTL0_STALL   , 1<<21    @ Bit 21 STALL: STALL handshake
                                        @ The application can only set this bit, and the core clears it, when a SETUP token is received
                                        @ for this endpoint. If a NAK bit or Global OUT NAK is set along with this bit, the STALL bit
                                        @ takes priority. Irrespective of this bit’s setting, the core always responds to SETUP data
                                        @ packets with an ACK handshake.
.equ OTG_FS_DOEPCTL0_SNPM   , 1<<20     @ Bit 20 SNPM: Snoop mode
                                        @ This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check
                                        @ the correctness of OUT packets before transferring them to application memory.
.equ OTG_FS_DOEPCTL0_EPTYP_N   , 1<<18  @ Bits 19:18 EPTYP: Endpoint type
.equ OTG_FS_DOEPCTL0_EPTYP_L ,  2       @ Hardcoded to 2’b00 for control.
.equ OTG_FS_DOEPCTL0_NAKSTS   , 1<<17   @ Bit 17 NAKSTS: NAK status
                                        @ Indicates the following:
                                        @ 0: The core is transmitting non-NAK handshakes based on the FIFO status.
                                        @ 1: The core is transmitting NAK handshakes on this endpoint.
                                        @ When either the application or the core sets this bit, the core stops receiving data, even if
                                        @ there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s
                                        @ setting, the core always responds to SETUP data packets with an ACK handshake.
.equ OTG_FS_DOEPCTL0_USBAEP   , 1<<15   @ Bit 15 USBAEP: USB active endpoint
                                        @ This bit is always set to 1, indicating that a control endpoint 0 is always active in all
                                        @ configurations and interfaces.
.equ OTG_FS_DOEPCTL0_MPSIZ_N   , 0      @ Bits 1:0 MPSIZ: Maximum packet size
.equ OTG_FS_DOEPCTL0_MPSIZ_L   , 2      @ The maximum packet size for control OUT endpoint 0 is the same as what is programmed in
                                        @ control IN endpoint 0.
                                        @ 00: 64 bytes
                                        @ 01: 32 bytes
                                        @ 10: 16 bytes
                                        @ 11: 8 bytes
@.end

@.item OTG_FS_DOEPCTL1 OTG_FS_DOEPCTL2 OTG_FS_DOEPCTL3
.equ OTG_FS_DOEPCTLx_EPENA  , 1<<31     @ Bit 31 EPENA: Endpoint enable
                                        @ Applies to IN and OUT endpoints.
                                        @ The application sets this bit to start transmitting data on an endpoint.
                                        @ The core clears this bit before setting any of the following interrupts on this endpoint:
                                        @ – SETUP phase done
                                        @ – Endpoint disabled
                                        @ – Transfer completed
.equ OTG_FS_DOEPCTLx_EPDIS  , 1<<30     @ Bit 30 EPDIS: Endpoint disable
                                        @ The application sets this bit to stop transmitting/receiving data on an endpoint, even before
                                        @ the transfer for that endpoint is complete. The application must wait for the Endpoint
                                        @ disabled interrupt before treating the endpoint as disabled. The core clears this bit before
                                        @ setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint
                                        @ enable is already set for this endpoint.
.equ OTG_FS_DOEPCTLx_SD1PID  , 1<<29    @ Bit 29 SD1PID: Set DATA1 PID
                                        @ Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint
                                        @ data PID (DPID) field in this register to DATA1.
.equ OTG_FS_DOEPCTLx_SODDFRM  , 1<<29   @ Bit 29 SODDFRM: Set odd frame
                                        @ Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
                                        @ frame (EONUM) field to odd frame.
.equ OTG_FS_DOEPCTLx_SD0PID  , 1<<28    @ Bit 28 SD0PID: Set DATA0 PID
                                        @ Applies to interrupt/bulk OUT endpoints only.
                                        @ Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0.
.equ OTG_FS_DOEPCTLx_SEVNFRM  , 1<<28   @ Bit 28 SEVNFRM: Set even frame
                                        @ Applies to isochronous OUT endpoints only.
                                        @ Writing to this field sets the Even/Odd frame (EONUM) field to even frame.
.equ OTG_FS_DOEPCTLx_SNAK  , 1<<27      @ Bit 27 SNAK: Set NAK
                                        @ A write to this bit sets the NAK bit for the endpoint.
                                        @ Using this bit, the application can control the transmission of NAK handshakes on an
                                        @ endpoint. The core can also set this bit for OUT endpoints on a Transfer Completed
                                        @ interrupt, or after a SETUP is received on the endpoint.
.equ OTG_FS_DOEPCTLx_CNAK  , 1<<26      @ Bit 26 CNAK: Clear NAK
                                        @ A write to this bit clears the NAK bit for the endpoint.
.equ OTG_FS_DOEPCTLx_STALL  , 1<<21     @ Bit 21 STALL: STALL handshake
                                        @ Applies to non-control, non-isochronous OUT endpoints only (access type is rw).
                                        @ The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK
                                        @ bit, Global IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes
                                        @ priority. Only the application can clear this bit, never the core.
.equ OTG_FS_DOEPCTLx_SNPM  , 1<<20      @ Bit 20 SNPM: Snoop mode
                                        @ This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check
                                        @ the correctness of OUT packets before transferring them to application memory.
.equ OTG_FS_DOEPCTLx_EPTYP_N  , 18      @ Bits 19:18 EPTYP: Endpoint type
.equ OTG_FS_DOEPCTLx_EPTYP_L  , 2       @ This is the transfer type supported by this logical endpoint.
                                        @ 00: Control
                                        @ 01: Isochronous
                                        @ 10: Bulk
                                        @ 11: Interrupt
.equ OTG_FS_DOEPCTLx_NAKSTS  , 1<<17    @ Bit 17 NAKSTS: NAK status
                                        @ Indicates the following:
                                        @ 0: The core is transmitting non-NAK handshakes based on the FIFO status.
                                        @ 1: The core is transmitting NAK handshakes on this endpoint.
                                        @ When either the application or the core sets this bit:
                                        @ The core stops receiving any data on an OUT endpoint, even if there is space in the
                                        @ RxFIFO to accommodate the incoming packet.
                                        @ Irrespective of this bit’s setting, the core always responds to SETUP data packets with an
                                        @ ACK handshake.
.equ OTG_FS_DOEPCTLx_EONUM  , 1<<16     @ Bit 16 EONUM: Even/odd frame
                                        @ Applies to isochronous IN and OUT endpoints only.
                                        @ Indicates the frame number in which the core transmits/receives isochronous data for this
                                        @ endpoint. The application must program the even/odd frame number in which it intends to
                                        @ transmit/receive isochronous data for this endpoint using the SEVNFRM and SODDFRM
                                        @ fields in this register.
                                        @ 0: Even frame
                                        @ 1: Odd frame
.equ OTG_FS_DOEPCTLx_DPID  , 1<<16      @ Bit 16 DPID: Endpoint data PID
                                        @ Applies to interrupt/bulk OUT endpoints only.
                                        @ Contains the PID of the packet to be received or transmitted on this endpoint. The
                                        @ application must program the PID of the first packet to be received or transmitted on this
                                        @ endpoint, after the endpoint is activated. The application uses the SD0PID register field to
                                        @ program either DATA0 or DATA1 PID.
                                        @ 0: DATA0
                                        @ 1: DATA1
.equ OTG_FS_DOEPCTLx_USBAEP  , 1<<15    @ Bit 15 USBAEP: USB active endpoint
                                        @ Indicates whether this endpoint is active in the current configuration and interface. The core
                                        @ clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving
                                        @ the SetConfiguration and SetInterface commands, the application must program endpoint
                                        @ registers accordingly and set this bit.
.equ OTG_FS_DOEPCTLx_MPSIZ_N  , 0       @ Bits 10:0 MPSIZ: Maximum packet size
.equ OTG_FS_DOEPCTLx_MPSIZ_L  , 11      @ The application must program this field with the maximum packet size for the current logical
                                        @ endpoint. This value is in bytes.
@.end

@.item OTG_FS_DIEPINT0 OTG_FS_DIEPINT1 OTG_FS_DIEPINT2 OTG_FS_DIEPINT3
.equ OTG_FS_DIEPINTx_RSTVAL , 0x80      @
.equ OTG_FS_DIEPINTx_NAK , 1<<13        @ Bit 13 NAK: NAK input
                                        @ The core generates this interrupt when a NAK is transmitted or received by the device. In
                                        @ case of isochronous IN endpoints the interrupt gets generated when a zero length packet is
                                        @ transmitted due to unavailability of data in the Tx FIFO.
.equ OTG_FS_DIEPINTx_PKTDRPSTS , 1<<11  @ Bit 11 PKTDRPSTS: Packet dropped status
                                        @ This bit indicates to the application that an ISOC OUT packet has been dropped. This bit
                                        @ does not have an associated mask bit and does not generate an interrupt.
.equ OTG_FS_DIEPINTx_TXFE , 1<<7        @ Bit 7 TXFE: Transmit FIFO empty
                                        @ This interrupt is asserted when the TxFIFO for this endpoint is either half or completely
                                        @ empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in
                                        @ the OTG_FS_GAHBCFG register (TXFELVL bit in OTG_FS_GAHBCFG).
.equ OTG_FS_DIEPINTx_INEPNE , 1<<6      @ Bit 6 INEPNE: IN endpoint NAK effective
                                        @ This bit can be cleared when the application clears the IN endpoint NAK by writing to the
                                        @ CNAK bit in OTG_FS_DIEPCTLx.
                                        @ This interrupt indicates that the core has sampled the NAK bit set (either by the application
                                        @ or by the core). The interrupt indicates that the IN endpoint NAK bit set by the application
                                        @ has taken effect in the core.
                                        @ This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit
                                        @ takes priority over a NAK bit.
.equ OTG_FS_DIEPINTx_INEPNM , 1<<5      @ Bit 5 INEPNM: IN token received with EP mismatch.
                                        @ Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other
                                        @ than the one for which the IN token was received. This interrupt is asserted on the endpoint
                                        @ for which the IN token was received.
.equ OTG_FS_DIEPINTx_ITTXFE , 1<<4      @ Bit 4 ITTXFE: IN token received when TxFIFO is empty
                                        @ Applies to non-periodic IN endpoints only.
                                        @ Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic)
                                        @ was empty. This interrupt is asserted on the endpoint for which the IN token was received.
.equ OTG_FS_DIEPINTx_TOC , 1<<3         @ Bit 3 TOC: Timeout condition
                                        @ Applies only to Control IN endpoints.
                                        @ Indicates that the core has detected a timeout condition on the USB for the last IN token on
                                        @ this endpoint.
.equ OTG_FS_DIEPINTx_EPDISD , 1<<1      @ Bit 1 EPDISD: Endpoint disabled interrupt
                                        @ This bit indicates that the endpoint is disabled per the application’s request.
.equ OTG_FS_DIEPINTx_XFRC , 1           @ Bit 0 XFRC: Transfer completed interrupt
                                        @ This field indicates that the programmed transfer is complete on the AHB as well as on the
                                        @ USB, for this endpoint.
@.end

@.item OTG_FS_DOEPINT0 OTG_FS_DOEPINT1 OTG_FS_DOEPINT2 OTG_FS_DOEPINT3
.equ OTG_FS_DOEPINTx_RSTVAL , 0x80      @
.equ OTG_FS_DOEPINTx_NAK , 1<<13        @ Bit 13 NAK: NAK input
                                        @ The core generates this interrupt when a NAK is transmitted or received by the device. In
                                        @ case of isochronous IN endpoints the interrupt gets generated when a zero length packet is
                                        @ transmitted due to unavailability of data in the Tx FIFO.
.equ OTG_FS_DOEPINTx_BERR , 1<<12       @ Bit 12 BERR: Babble error interrupt
                                        @ The core generates this interrupt when babble is received for the endpoint.
.equ OTG_FS_DOEPINTx_OUTPKTERR , 1<<8   @ Bit 8 OUTPKTERR: OUT packet error
                                        @ This interrupt is asserted when the core detects an overflow or a CRC error for an OUT
                                        @ packet. This interrupt is valid only when thresholding is enabled.
.equ OTG_FS_DOEPINTx_STSPHSRX , 1<<5    @ Bit 5 STSPHSRX: Status phase received for control write
                                        @ This interrupt is generated only after the core has transferred all the data that the host has
                                        @ sent during the data phase of a control write transfer, to the system memory buffer. The
                                        @ interrupt indicates to the application that the host has switched from data phase to the status
                                        @ phase of a control write transfer. The application can use this interrupt to ACK or STALL the
                                        @ status phase, after it has decoded the data phase.
.equ OTG_FS_DOEPINTx_OTEPDIS , 1<<4     @ Bit 4 OTEPDIS: OUT token received when endpoint disabled
                                        @ Applies only to control OUT endpoints.
                                        @ Indicates that an OUT token was received when the endpoint was not yet enabled. This
                                        @ interrupt is asserted on the endpoint for which the OUT token was received.
.equ OTG_FS_DOEPINTx_STUP , 1<<3        @ Bit 3 STUP: SETUP phase done
                                        @ Applies to control OUT endpoint only.
                                        @ Indicates that the SETUP phase for the control endpoint is complete and no more back-to-
                                        @ back SETUP packets were received for the current control transfer. On this interrupt, the
                                        @ application can decode the received SETUP data packet.
.equ OTG_FS_DOEPINTx_EPDISD , 1<<1      @ Bit 1 EPDISD: Endpoint disabled interrupt
                                        @ This bit indicates that the endpoint is disabled per the application’s request.
.equ OTG_FS_DOEPINTx_XFRC , 1           @ Bit 0 XFRC: Transfer completed interrupt
                                        @ This field indicates that the programmed transfer is complete on the AHB as well as on the
                                        @ USB, for this endpoint.
@.end

@.item OTG_FS_DIEPTSIZ0
.equ OTG_FS_DIEPTSIZ0_PKTCNT_N , 19     @ Bits 20:19 PKTCNT: Packet count
.equ OTG_FS_DIEPTSIZ0_PKTCNT_L , 2      @ Indicates the total number of USB packets that constitute the Transfer Size amount of data
                                        @ for endpoint 0.
                                        @ This field is decremented every time a packet (maximum size or short packet) is read from
                                        @ the TxFIFO.
.equ OTG_FS_DIEPTSIZ0_XFRSIZ_N , 0      @ Bits 6:0 XFRSIZ: Transfer size
.equ OTG_FS_DIEPTSIZ0_XFRSIZ_L , 7      @ Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only
                                        @ after it has exhausted the transfer size amount of data. The transfer size can be set to the
                                        @ maximum packet size of the endpoint, to be interrupted at the end of each packet.
                                        @ The core decrements this field every time a packet from the external memory is written to
                                        @ the TxFIFO.
@.end

@.item OTG_FS_DOEPTSIZ0
.equ OTG_FS_DOEPTSIZ0_STUPCNT_N , 29    @ Bits 30:29 STUPCNT: SETUP packet count
.equ OTG_FS_DOEPTSIZ0_STUPCNT_L , 2     @ This field specifies the number of back-to-back SETUP data packets the endpoint can
                                        @ receive.
                                        @ 01: 1 packet
                                        @ 10: 2 packets
                                        @ 11: 3 packets
.equ OTG_FS_DOEPTSIZ0_PKTCNT , 1<<19    @ Bit 19 PKTCNT: Packet count
                                        @ This field is decremented to zero after a packet is written into the RxFIFO.
.equ OTG_FS_DOEPTSIZ0_XFRSIZ_N , 0      @ Bits 6:0 XFRSIZ: Transfer size
.equ OTG_FS_DOEPTSIZ0_XFRSIZ_L , 7      @ Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only
                                        @ after it has exhausted the transfer size amount of data. The transfer size can be set to the
                                        @ maximum packet size of the endpoint, to be interrupted at the end of each packet.
                                        @ The core decrements this field every time a packet is read from the RxFIFO and written to
                                        @ the external memory.
@.end

@.item OTG_FS_DIEPTSIZ1 OTG_FS_DIEPTSIZ2 OTG_FS_DIEPTSIZ3
.equ OTG_FS_DIEPTSIZx_PKTCNT_N , 19     @ Bit 28:19 PKTCNT: Packet count
.equ OTG_FS_DIEPTSIZx_PKTCNT_L , 2      @ Indicates the total number of USB packets that constitute the Transfer Size amount of data
                                        @ for this endpoint.
                                        @ This field is decremented every time a packet (maximum size or short packet) is read from
                                        @ the TxFIFO.
.equ OTG_FS_DIEPTSIZx_XFRSIZ_N , 0      @ Bits 18:0 XFRSIZ: Transfer size
.equ OTG_FS_DIEPTSIZx_XFRSIZ_L , 19     @ This field contains the transfer size in bytes for the current endpoint. The core only interrupts
                                        @ the application after it has exhausted the transfer size amount of data. The transfer size can
                                        @ be set to the maximum packet size of the endpoint, to be interrupted at the end of each
                                        @ packet.
                                        @ The core decrements this field every time a packet from the external memory is written to
                                        @ the TxFIFO.
@.end

@.item OTG_FS_DTXFSTS0 OTG_FS_DTXFSTS1 OTG_FS_DTXFSTS2 OTG_FS_DTXFSTS3
.equ OTG_FS_DTXFSTSx_INEPTFSAV_N , 0    @ 15:0 INEPTFSAV: IN endpoint TxFIFO space available
.equ OTG_FS_DTXFSTSx_INEPTFSAV_L , 16   @ Indicates the amount of free space available in the Endpoint TxFIFO.
                                        @ Values are in terms of 32-bit words:
                                        @ 0x0: Endpoint TxFIFO is full
                                        @ 0x1: 1 word available
                                        @ 0x2: 2 words available
                                        @ 0xn: n words available
                                        @ Others: Reserved
@.end

@.item OTG_FS_DOEPTSIZ1 OTG_FS_DOEPTSIZ2 OTG_FS_DOEPTSIZ3
.equ OTG_FS_DOEPTSIZx_RXDPID_N , 29     @ Bits 30:29 RXDPID: Received data PID
.equ OTG_FS_DOEPTSIZx_RXDPID_L , 2      @ Applies to isochronous OUT endpoints only.
                                        @ This is the data PID received in the last packet for this endpoint.
                                        @ 00: DATA0
                                        @ 01: DATA2
                                        @ 10: DATA1
                                        @ 11: MDATA
.equ OTG_FS_DOEPTSIZx_STUPCNT_N , 29    @ Bits 30:29 STUPCNT: SETUP packet count
.equ OTG_FS_DOEPTSIZx_STUPCNT_L , 2     @ Applies to control OUT Endpoints only.
                                        @ This field specifies the number of back-to-back SETUP data packets the endpoint can
                                        @ receive.
                                        @ 01: 1 packet
                                        @ 10: 2 packets
                                        @ 11: 3 packets
.equ OTG_FS_DOEPTSIZx_PKTCNT_N , 19     @ Bit 28:19 PKTCNT: Packet count
.equ OTG_FS_DOEPTSIZx_PKTCNT_L , 10     @ Indicates the total number of USB packets that constitute the Transfer Size amount of data
                                        @ for this endpoint.
                                        @ This field is decremented every time a packet (maximum size or short packet) is written to
                                        @ the RxFIFO.
.equ OTG_FS_DOEPTSIZx_XFRSIZ , 0        @ Bits 18:0 XFRSIZ: Transfer size
.equ OTG_FS_DOEPTSIZx_XFRSIZ , 19       @ This field contains the transfer size in bytes for the current endpoint. The core only interrupts
                                        @ the application after it has exhausted the transfer size amount of data. The transfer size can
                                        @ be set to the maximum packet size of the endpoint, to be interrupted at the end of each
                                        @ packet.
                                        @ The core decrements this field every time a packet is read from the RxFIFO and written to
                                        @ the external memory.
@.end

@.item OTG_FS_PCGCCTL
.equ OTG_FS_PCGCCTL_PHYSUSP , 1<<4      @ Bit 4 PHYSUSP: PHY Suspended
                                        @ Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
                                        @ after the application has set the STPPCLK bit (bit 0).
.equ OTG_FS_PCGCCTL_GATEHCLK , 1<<1     @ Bit 1 GATEHCLK: Gate HCLK
                                        @ The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
                                        @ and wakeup logic when the USB is suspended or the session is not valid. The application
                                        @ clears this bit when the USB is resumed or a new session starts.
.equ OTG_FS_PCGCCTL_STPPCLK , 1         @ Bit 0 STPPCLK: Stop PHY clock
                                        @ The application sets this bit to stop the PHY clock when the USB is suspended, the session
                                        @ is not valid, or the device is disconnected. The application clears this bit when the USB is
                                        @ resumed or a new session starts.
@.end

