@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы PWR                        |
@ |                           STM32F42x                              |
@ +------------------------------------------------------------------+
@.enddesc


.include       "/src/inc/base.inc"

@.item     APB1PERIPH_BASE
.equ  PWR_BASE                , ( APB1PERIPH_BASE + 0x7000 )
@.end

@.item     PWR_BASE
.equ  PWR_CR                  , 0x00
.equ  PWR_CSR                 , 0x04
@.end

@.item     PWR_CR
.equ  PWR_CR_RST_VAL          , 0x00004000    @ значение по умолчанию
.equ  PWR_CR_LPDS             , 0x01     @  Bit 0 LPDS: Low-power deepsleep
.equ  PWR_CR_PDDS             , 0x02     @  Bit 1 PDDS: Power-down deepsleep
.equ  PWR_CR_CWUF             , 0x04     @  Bit 2 CWUF: Clear wakeup flag
.equ  PWR_CR_CSBF             , 0x08     @  Bit 3 CSBF: Clear standby flag
.equ  PWR_CR_PVDE             , 0x10     @  Bit 4 PVDE: Power voltage detector enable
.equ  PWR_CR_VOS_N            , 14       @  Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
.EQU  PWR_CR_FPDS_N           , 9        @  Bits 9 FPDS: Flash power-down in Stop mode
.equ  PWR_CR_DBP_N            , 8        @  Bits 8 DBP: Disable backup domain write protection
.equ  PWR_CR_PLS_N            , 5        @  Bits 7:5 PLS[2:0]: PVD level selection
.equ  PWR_CR_PVDE_N           , 4        @  Bits PVDE: Power voltage detector enable
.equ  PWR_CR_CSBF_N           , 3        @  Bits CSBF: Clear standby flag
.equ  PWR_CR_CWUF_N           , 2        @  Bits CWUF: Clear wakeup flag
.equ  PWR_CR_PDDS_N           , 1        @  Bits PDDS: Power-down deepsleep
.equ  PWR_CR_LPDS_N           , 0        @  Bits LPDS: Low-power deepsleep
.equ  PWR_CR_PLS_2D0V         , 0 << 5
.equ  PWR_CR_PLS_2D1V         , 1 << 5
.equ  PWR_CR_PLS_2D3V         , 2 << 5
.equ  PWR_CR_PLS_2D5V         , 3 << 5
.equ  PWR_CR_PLS_2D6V         , 4 << 5
.equ  PWR_CR_PLS_2D7V         , 5 << 5
.equ  PWR_CR_PLS_2D8V         , 6 << 5
.equ  PWR_CR_PLS_2D9V         , 7 << 5
.equ  PWR_CR_DBP              , 1 << 8    @  Bit 8 DBP: Disable backup domain write protection
.equ  PWR_CR_FPDS             , 1 << 9    @  Bit 9 FPDS: Flash power-down in Stop mode
.equ  PWR_CR_LPUDS            , 1 << 10    @  Bit 10 LPUDS: Low-power regulator in deepsleep under-drive mode
.equ  PWR_CR_MRUDS            , 1 << 11    @  Bit 11 MRUDS: Main regulator in deepsleep under-drive mode
.equ  PWR_CR_ADCDC1           , 1 << 13    @  Bit 13 1: Refer to AN4073 for details on how to use this bit.
.equ  PWR_CR_VOS_0            , 1 << 14    @  01: Scale 3 mode
.equ  PWR_CR_VOS_1            , 2 << 14    @  10: Scale 2 mode
@.end

@.item     PWR_CSR
.equ  PWR_CSR_UDRDY_N         , 18       @ Bits 19:18 UDRDY[1:0]: Under-drive ready flag
.equ  PWR_CSR_UDRDY_0         , 1 << 18    @ 00: Under-drive is disabled
.equ  PWR_CSR_UDRDY_1         , 2 << 18    @ 11:Under-drive mode is activated in Stop mode.
.equ  PWR_CSR_ODSWRDY_N       , 17       @ Bit 17 ODSWRDY: Over-drive mode switching ready
.equ  PWR_CSR_ODSWRDY         , 1 << 17    @ Bit 17 ODSWRDY: Over-drive mode switching ready
.equ  PWR_CSR_ODRDY_N         , 16       @ Bit 16 ODRDY: Over-drive mode ready
.equ  PWR_CSR_ODRDY           , 1 << 16    @ 1: Over-drive mode ready
.equ  PWR_CSR_VOSRDY_N        , 14       @ Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
.equ  PWR_CSR_VOSRDY          , 1 << 14    @ 1: Ready
.equ  PWR_CSR_BRE_N           , 9        @ Bit 9 BRE: Backup regulator enable
.equ  PWR_CSR_BRE             , 1 << 9    @ 1: Backup regulator enabled
.equ  PWR_CSR_EWUP_N          , 8        @  Bit 8 EWUP: Enable WKUP pin
.equ  PWR_CSR_EWUP            , 1 << 8    @ 1: WKUP pin is used for wakeup from Standby mode
.equ  PWR_CSR_BRR_N           , 3        @  Bit 3 BRR: Backup regulator ready
.equ  PWR_CSR_BRR             , 1 << 3    @ 1: Backup Regulator ready
.equ  PWR_CSR_PVDO_N          , 2        @ Bit 2 PVDO: PVD output
.equ  PWR_CSR_PVDO            , 1 << 2    @ 1: VDD is lower than the PVD
.equ  PWR_CSR_SBF_N           , 1        @ Bit 1 SBF: Standby flag
.equ  PWR_CSR_SBF             , 1 << 1    @1: Device has been in Standby mode
.equ  PWR_CSR_WUF_N           , 0        @ Bit 0 WUF: Wakeup flag
.equ  PWR_CSR_WUF             , 1        @ 1: A wakeup event was received from the WKUP pin
@.end
