@.CHARSET CP1251

@ +----------------------------------------------------------+
@ |               Определения IWDG (Глава 19)                |
@ |                     STM32F0x0xxx                         |
@ +----------------------------------------------------------+

.INCLUDE "/src/inc/base.inc"

@.ITEM  APBPERIPH_BASE
.EQU  IWDG_BASE           , APBPERIPH_BASE + 0x3000
.EQU  IWDG                , PERIPH_BASE + IWDG_BASE
@.END

@.ITEM IWDG IWDG_BASE
.EQU IWDG_KR, 0x00                       @ Key register
.EQU IWDG_PR, 0x04                       @ Prescaler register
.EQU IWDG_RLR, 0x08                      @ Reload register
.EQU IWDG_SR, 0x0C                       @ Status register
.EQU IWDG_WINR, 0x10                     @ Window register
@.END

@.ITEM IWDG_KR
.EQU IWDG_KR_KEY_N, 0                   @ KEY[15:0]: Key value (write only, read 0x0000)
                                        @ These bits must be written by software at regular intervals with the key value 0xAAAA,
                                        @ otherwise the watchdog generates a reset when the counter reaches 0.
                                        @ Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
                                        @ IWDG_WINR registers (see Section 19.3.5: Register access protection)
                                        @ Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected)
@.END

@.ITEM IWDG_PR
.EQU IWDG_PR_PR_N, 0                    @ PR[2:0]: Prescaler divider
.EQU IWDG_PR_PR0, 0X00<<0               @ 000: divider /4
.EQU IWDG_PR_PR1, 0X01<<0               @ 001: divider /8
.EQU IWDG_PR_PR2, 0X02<<0               @ 010: divider /16
.EQU IWDG_PR_PR3, 0X03<<0               @ 011: divider /32
.EQU IWDG_PR_PR4, 0X04<<0               @ 100: divider /64
.EQU IWDG_PR_PR5, 0X05<<0               @ 101: divider /128
.EQU IWDG_PR_PR6, 0X06<<0               @ 110: divider /256
.EQU IWDG_PR_PR7, 0X07<<0               @ 111: divider /256
@.END

@.ITEM IWDG_RLR
.EQU IWDG_RLR_RL_N, 0                   @ RL[11:0]: Watchdog counter reload value
@.END

@.ITEM IWDG_SR
.EQU IWDG_SR_WVU, 1<<2                  @ Watchdog counter window value update
.EQU IWDG_SR_RVU, 1<<1                  @ Watchdog counter reload value update
.EQU IWDG_SR_PVU, 1<<0                  @ Watchdog prescaler value update
@.END

@.ITEM IWDG_WINR
.EQU IWDG_WINR_WIN_N, 0                 @ WIN[11:0]: Watchdog counter window value
                                        @ These bits contain the high limit of
                                        @ the window value to be compared to the downcounter.
                                        @ To prevent a reset, the downcounter must be reloaded when its value is lower than the
                                        @ window register value and greater than 0x0
                                        @ The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value.
@.END


