@GNU AS
@.CHARSET =CP1251 ( Cyrillic )

@.DESC     type=module
@ +------------------------------------------------------------------+
@ |  Базовые константы: Serial Peripheral Interface (SPI)            |
@ |                           STM32F303                              |
@ +------------------------------------------------------------------+
@.ENDDESC


.INCLUDE   "/src/inc/base.inc"

@ Peripheral memory map
@.ITEM     APB1PERIPH_BASE
.EQU  I2S2ext_BASE       , APB1PERIPH_BASE + 0x00003400
.EQU  SPI2_BASE          , APB1PERIPH_BASE + 0x00003800
.EQU  SPI2               , PERIPH_BASE + SPI2_BASE
.EQU  SPI3_BASE          , APB1PERIPH_BASE + 0x00003C00
.EQU  SPI3               , PERIPH_BASE + SPI3_BASE
.EQU  I2S3ext_BASE       , APB1PERIPH_BASE + 0x00004000
.EQU  I2C1_BASE          , APB1PERIPH_BASE + 0x00005400
.EQU  I2C2_BASE          , APB1PERIPH_BASE + 0x00005800
@.END

@.ITEM     APB2PERIPH_BASE
.EQU  SPI1_BASE          , APB2PERIPH_BASE + 0x00003000
.EQU  SPI1               , PERIPH_BASE + SPI1_BASE
@.END

@.ITEM     SPI1_BASE SPI2_BASE SPI3_BASE SPI1 SPI2 SPI3
.EQU  SPI_CR1            , 0x00           @ Control register 1
.EQU  SPI_CR2            , 0x04           @ Control register 2
.EQU  SPI_SR             , 0x08           @ Status register
.EQU  SPI_DR             , 0x0C           @ data register
.EQU  SPI_CRCPR          , 0x10           @ CRC polynomial register
.EQU  SPI_RXCRCR         , 0x14           @ Rx CRC register
.EQU  SPI_TXCRCR         , 0x18           @ Tx CRC register
.EQU  SPI_I2SCFGR        , 0x1C           @ I2S configuration register
.EQU  SPI_I2SPR          , 0x20           @ I2S prescaler register
@.END

@.ITEM     SPI_CR1
.EQU  SPI_CR1_CPHA_N     , 0              @ Clock Phase
.EQU  SPI_CR1_CPOL_N     , 1              @ Clock Polarity
.EQU  SPI_CR1_MSTR_N     , 2              @ Master Selection
.EQU  SPI_CR1_BR_N       , 3              @ BR [ 2 : 0 ] bits Baud Rate Control
.EQU  SPI_CR1_BR         , 7 << 3
.EQU  SPI_CR1_BR_0       , 1 << 3
.EQU  SPI_CR1_BR_1       , 2 << 3
.EQU  SPI_CR1_BR_2       , 4 << 3
.EQU  SPI_CR1_SPE_N      , 6              @  SPI Enable
.EQU  SPI_CR1_LSBFIRST_N , 7              @  Frame Format
.EQU  SPI_CR1_SSI_N      , 8              @  Internal slave select
.EQU  SPI_CR1_SSM_N      , 9              @  Software slave management
.EQU  SPI_CR1_RXONLY_N   , 10             @  Receive only
.EQU  SPI_CR1_CRCL_N     , 11             @  CRC Length
.EQU  SPI_CR1_CRCNEXT_N  , 12             @  Transmit CRC next
.EQU  SPI_CR1_CRCEN_N    , 13             @  Hardware CRC calculation enable
.EQU  SPI_CR1_BIDIOE_N   , 14             @  Output enable in bidirectional mode
.EQU  SPI_CR1_BIDIMODE_N , 15             @  Bidirectional data mode enable
@.END

@.ITEM     SPI_CR2
.EQU  SPI_CR2_RXDMAEN_N  , 0              @ Rx Buffer DMA Enable
.EQU  SPI_CR2_TXDMAEN_N  , 1              @ Tx Buffer DMA Enable
.EQU  SPI_CR2_SSOE_N     , 2              @  SS Output Enable
.EQU  SPI_CR2_SSOE_M     , 1 << 2
.EQU  SPI_CR2_NSSP_N     , 3              @  NSS pulse management Enable
.EQU  SPI_CR2_FRF_N      , 4              @  Frame Format Enable
.EQU  SPI_CR2_ERRIE_N    , 5              @ Error Interrupt Enable
.EQU  SPI_CR2_RXNEIE_N   , 6              @ RX buffer Not Empty Interrupt Enable
.EQU  SPI_CR2_TXEIE_N    , 7              @ Tx buffer Empty Interrupt Enable
.EQU  SPI_CR2_DS_N       , 8              @  DS[3:0] Data Size
.EQU  SPI_CR2_DS_M       , 0xF << 8
.EQU  SPI_CR2_DS_0       , 1 << 8
.EQU  SPI_CR2_DS_1       , 2 << 8
.EQU  SPI_CR2_DS_2       , 4 << 8
.EQU  SPI_CR2_DS_3       , 8 << 8
.EQU  SPI_CR2_FRXTH_N    , 12             @  FIFO reception Threshold
.EQU  SPI_CR2_LDMARX_N   , 13             @ Last DMA transfer for reception
.EQU  SPI_CR2_LDMATX_N   , 14             @  Last DMA transfer for transmission
@.END

@.ITEM     SPI_SR
.EQU  SPI_SR_RXNE_N      , 0              @ Receive buffer Not Empty
.EQU  SPI_SR_TXE_N       , 1              @ Transmit buffer Empty
.EQU  SPI_SR_CHSIDE_N    , 2              @ Channel side
.EQU  SPI_SR_UDR_N       , 3              @ Underrun flag
.EQU  SPI_SR_CRCERR_N    , 4              @ CRC Error flag
.EQU  SPI_SR_MODF_N      , 5              @ Mode fault
.EQU  SPI_SR_OVR_N       , 6              @ Overrun flag
.EQU  SPI_SR_BSY_N       , 7              @ Busy flag
.EQU  SPI_SR_FRE_N       , 8              @ TI frame format error
.EQU  SPI_SR_FRLVL_N     , 9              @  FIFO Reception Level
.EQU  SPI_SR_FRLVL_M     , 3 << 9
.EQU  SPI_SR_FRLVL_0     , 1 << 9
.EQU  SPI_SR_FRLVL_1     , 2 << 9
.EQU  SPI_SR_FTLVL_N     , 11             @ FIFO Transmission Level
.EQU  SPI_SR_FTLVL_M     , 3 << 11
.EQU  SPI_SR_FTLVL_0     , 1 << 11
.EQU  SPI_SR_FTLVL_1     , 2 << 11
@.END

@.ITEM     SPI_DR
.EQU  SPI_DR_N           , 0              @  Data register
.EQU  SPI_DR_M           , 0xFFFF << 0    @  x0000FFFF
@.END

@.ITEM     SPI_CRCPR
.EQU  SPI_CRCPR_CRCPOLY_N, 0              @  CRC polynomial register
.EQU  SPI_CRCPR_CRCPOLY_M, 0xFFFF << 0    @  x0000FFFF
@.END

@.ITEM     SPI_RXCRCR
.EQU  SPI_RXCRCR_RXCRC_N , 0              @ Rx CRC Register
.EQU  SPI_RXCRCR_RXCRC_M , 0xFFFF << SPI_0    @   0x0000FFFF
@.END

@.ITEM     SPI_TXCRCR
.EQU  SPI_TXCRCR_TXCRC_N , 0              @ Tx CRC Register
.EQU  SPI_TXCRCR_TXCRC_M , 0xFFFF << SPI_0
@.END

@.ITEM     SPI_I2SCFGR
.EQU  SPI_I2SCFGR_CHLEN_N, 0              @  Channel length (number of bits per audio channel
.EQU  SPI_I2SCFGR_DATLEN_N, 1             @   DATLEN[1:0] bits (Data length to be transferred)
.EQU  SPI_I2SCFGR_DATLEN_M, 0x3 << 1
.EQU  SPI_I2SCFGR_DATLEN_0, 0x1 << 1
.EQU  SPI_I2SCFGR_DATLEN_1, 0x2 << 1
.EQU  SPI_I2SCFGR_CKPOL_N, 3              @ steady state clock polarity
.EQU  SPI_I2SCFGR_I2SSTD_N, 4             @ I2SSTD[1:0] bits (I2S standard selection)
.EQU  SPI_I2SCFGR_I2SSTD_M, 3 << 4        @ 0x00000030
.EQU  SPI_I2SCFGR_I2SSTD_0, 0x1 << 4
.EQU  SPI_I2SCFGR_I2SSTD_1, 0x2 << 4
.EQU  SPI_I2SCFGR_PCMSYNC_N, 7            @ PCM frame synchronization
.EQU  SPI_I2SCFGR_I2SCFG_N, 8             @ I2SCFG[1:0] bits (I2S configuration mode)
.EQU  SPI_I2SCFGR_I2SCFG_M, 0x3 << 8      @ x00000300
.EQU  SPI_I2SCFGR_I2SCFG_0, 0x1 << 8
.EQU  SPI_I2SCFGR_I2SCFG_1, 0x2 << 8
.EQU  SPI_I2SCFGR_I2SE_N , 10             @ I2S Enable
.EQU  SPI_I2SCFGR_I2SE_M , 0x1 << 10      @ x00000400 */
.EQU  SPI_I2SCFGR_I2SMOD_N, 11            @ I2S mode selection
.EQU  SPI_I2SCFGR_I2SMOD_M, 0x1 << 11     @ 0x00000800
@.END

@.ITEM     SPI_I2SPR
.EQU  SPI_I2SPR_I2SDIV_N , 0              @  I2S Linear prescaler
.EQU  SPI_I2SPR_I2SDIV_M , 0xFF << 0      @ 0x000000FF
.EQU  SPI_I2SPR_ODD_N    , 8              @  Odd factor for the prescaler
.EQU  SPI_I2SPR_MCKOE_N  , 9              @  Master Clock Output Enable
@.END

