@.CHARSET CP1251

@ +-------------------------------------------------------------------+
@ |                        Îďđĺäĺëĺíč˙ FLASH                          |
@ |                            STM32L1xxx                             |
@ +-------------------------------------------------------------------+

.include "/src/inc/base.inc"

@.item AHBPERIPH_BASE
.EQU  FLASH         ,  AHBPERIPH_BASE + 0x3C00
@.end

@.item FLASH
.EQU  FLASH_ACR     , 0X00    @ Access co ntrol re gister (FLASH_ACR)
.EQU  FLASH_PECR    , 0x04    @ Program/erase control register (FLASH_PECR)
.EQU  FLASH_PDKEYR  , 0X08    @ Power down key register (FLASH_PDKEYR)
.EQU  FLASH_PEKEYR  , 0x0C    @ Program/erase key register (FLASH_PEKEYR)
.EQU  FLASH_PRGKEYR , 0x10    @ Program memory key register (FLASH_PRGKEYR)
.EQU  FLASH_OPTKEYR , 0x14    @ Option byte key register (FLASH_OPTKEYR)
.EQU  FLASH_SR      , 0X18    @ Status register (FLASH_SR)
.EQU  FLASH_OBR     , 0x1C    @ Option byte register (FLASH_OBR)
.EQU  FLASH_WRPR1   , 0x20    @ Write protection register (FLASH_WRPR1)
.EQU  FLASH_WRPR2   , 0x80    @ Write protection register (FLASH_WRPR2)
.EQU  FLASH_WRPR3   , 0x84    @ Write protection register (FLASH_WRPR3)
.EQU  FLASH_WRPR4   , 0x88    @ Write protection register (FLASH_WRPR4)
@.END

@.ITEM FLASH_ACR
.EQU  FLASH_ACR_RUN_PD_N, 4   @ Bit 4  RUN_PD: Power saving mode during Run
                              @ This bit can be written only when it is unlocked by writing to FLASH_PDKEYR.
                              @ This bit determines whether the Flash memory module is in Power down mode or Idle mode
                              @ when the STM32L1xxxx is in Run mode.
                              @ The Flash memory module can be placed in Power down mode only when the code is
                              @ executed from SRAM).
                              @ 0: Flash module in Idle mode
.EQU  FLASH_ACR_RUN_PD, 1<<4  @ 1: Flash modulein Power down mode
.EQU  FLASH_ACR_SLEEP_PD_N, 3 @ Bit 3  SLEEP_PD: Power saving mode during Sleep
                               @ This bit is used to put the Flash memory module in Power down mode or Idle mode when
                               @ the STM32L1xxxx is in Sleep mode.
                               @ 0: Flash module in Idle mode
.EQU  FLASH_ACR_SLEEP_PD, 1<<3 @ 1: Flash module in Power down mode
.EQU  FLASH_ACR_ACC64_N, 2     @ Bit 2  ACC64: 64-bit access
                               @ This bit is used to read data from the memory 64 bits or 32 bits at a time. 32-bit access is
                               @ used to decreases the memory consumption. On the contrary, 64-bit access is used to
                               @ improve the performance. In this case it is useful to enable prefetch.
                               @ 0: 32-bit access
.EQU  FLASH_ACR_ACC64, 1<<2    @ 1: 64-bit access
                         @ Note: 32-bit access is a low-power mode. It is used only at low frequencies, that is with 0 wait
                               @ state of latency and prefetch off.
                               @ Note: This bit cannot be written at the same time as the LATENCY and PRFTEN bits.
.EQU  FLASH_ACR_PRFTEN_N, 1    @ Bit 1  PRFTEN: Prefetch enable
                               @ 0: prefetch disabled
.EQU  FLASH_ACR_PRFTEN, 1<<1   @ 1: prefetch enabled
                         @ Note: Prefetch can be enabled only when ACC64 is set.
                               @ This bit can be set or cleared only if ACC64 is set.
.EQU  FLASH_ACR_LATENCY_N, 0   @ Bit 0  LATENCY: Latency
                               @ This bit represents the ratio of the CPU clock period to the memory access time.
                               @ 0: zero wait state
.EQU  FLASH_ACR_LATENCY, 1     @ 1: one wait state
                         @ Note: Latency can be set only when ACC64 is set.
                               @ This bit can be set or cleared only if ACC64 is set.
@.END

 @.ITEM FLASH_PECR
.EQU FLASH_PECR_OBL_LAUNCH_N, 18 @ Bit 18 OBL_LAUNCH: Launch the option byte loading
                                 @ This bit is set by software to launch the option byte loading. This bit is cleared only when the
                                 @ option byte loading has completed. It cannot be written if OPTLOCK is set.
                                 @ When this bit is set, a reset is generated.
                                 @ 0: Option byte loading complete
.EQU FLASH_PECR_OBL_LAUNCH, 1<<18 @ 1: Option byte has to be loaded
.EQU FLASH_PECR_ERRIE_N, 17      @ Bit 17  ERRIE: Error interrupt enable
                                 @ 0: interrupt disabled
.EQU FLASH_PECR_ERRIE, 1<<17     @ 1: interrupt enabled
.EQU FLASH_PECR_EOPIE_N, 16      @ Bit 16  EOPIE: End of programming interrupt enable
                                 @ 0: interrupt disabled
.EQU FLASH_PECR_EOPIE, 1<<16     @ 1: interrupt enabled
.EQU FLASH_PECR_PARALLBANK_N, 15 @ Bit 15  PARALLBANK: Parallel bank mode.
                                 @ This bit can be set and cleared by software when no program or erase process is on-going.
                                 @ When this bit is set, 2 half pages can be programmed or 2 pages can be erased in parallel
                                 @ (the first one in the first bank and the second one in the second bank).
                                 @ 0: Parallel bank mode disabled
.EQU FLASH_PECR_PARALLBANK, 1<<15 @ 1: Parallel bank mode enabled
                            @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU FLASH_PECR_FPRG_N, 10       @ Bit 10  FPRG: Half Page/Double Word programming mode
                                 @ This bit can be written by software when no program or erase process is ongoing.
                                 @ It is used to enable/disable Half Page Programming to the program memory or Double Word
                                 @ Programming to the data EEPROM.
                                 @ 32 loadings are required to program half a page to the program memory.
                                 @ 2 loadings are required to program a double word to the data EEPROM.
                                 @ This bit is cleared when PELOCK is set.
                                 @ 0: Half Page/Double Word programming disabled
.EQU FLASH_PECR_FPRG, 1<<10      @ 1: Half Page/Double Word programming enabled
.EQU FLASH_PECR_ERASE_N, 9       @ Bit 9  ERASE: Page or Double Word erase mode
                                 @ This bit can be written by software when no program or erase process is on going.
                                 @ It is used to enable/disable Page Erase on the program memory or Double Word Erase on
                                 @ the data EEPROM and the option byte block.
                                 @ This bit is cleared when PELOCK is set.
                                 @ 0: Page or Double Word Erase disabled
.EQU FLASH_PECR_ERASE, 1<<9      @ 1: Page or Double Word Erase enabled
.EQU FLASH_PECR_FTDW_N, 8        @ Bit 8 FTDW: Fixed time data write for Byte, Half Word and Word programming
                                 @ This bit is writable by software when no program or erase process is ongoing.
                                 @ This bit is used for the data EEPROM only.
                                 @ It is cleared when PELOCK is set.
                                 @ 0: Programming of a Byte, Half Word or word is performed without any previous erase
                                 @ operation. This is possible if the word being written to is 0x0000 0000.
.EQU  FLASH_PECR_FTDW, 1 << 8    @ 1: Before the programming of a Byte, Half Word and word an erase phase is automatically
                                 @ performed. So the time of programming is fixed and lasts two tprog
.EQU FLASH_PECR_DATA_N, 4        @ Bit 4 DATA: Data EEPROM selection
                                 @ This bit is writable by software when no program or erase process is ongoing.
                                 @ This bit has to be set prior to data EEPROM double word erase/programming.
                                 @ This bit is cleared when PELOCK is set.
                                 @ 0: Data EEPROM not selected
.EQU  FLASH_PECR_DATA, 1 << 4    @ 1: Data EEPROM selected
.EQU FLASH_PECR_PROG_N, 3        @ Bit 3  PROG: Program memory selection
                                 @ This bit is writable by software when no program or erase process is ongoing.
                                 @ This bit has to be set to gain write access to the program memory, except in the case of
                                 @ word programming.
                                 @ This bit is cleared when PELOCK is set.
                                 @ 0: Program memory not selected
.EQU FLASH_PECR_PROG, 1<<3       @ 1: Program memory selected
.EQU FLASH_PECR_OPTLOCK_N, 2     @ Bit 2  OPTLOCK: Option bytes block lock
                                 @ This bit can only be written to 1. When it is set, it indicates that the option byte block is
                                 @ locked.
                                 @ It is cleared by hardware after detecting the unlock sequence. In the event of an
                                 @ unsuccessful unlock operation or a third access to OPTKEYR, a bus error (Cortex®-M3
                                 @ hardfault or Busfault) is generated and this bit remains set until the next reset.
                                 @ This bit is set when PELOCK is set.
                                 @ 0: option unlocked
.EQU FLASH_PECR_OPTLOCK, 1<<2    @ 1: option locked
.EQU FLASH_PECR_PRGLOCK_N, 1     @ Bit 1  PRGLOCK: Program memory lock
                                 @ This bit can only be written to 1. When it is set, it indicates that the program memory cannot
                                 @ be written. It is cleared by hardware after detecting the unlock sequence. In the event of an
                                 @ unsuccessful unlock operation or a third access to PRGKEYR, a bus error (Cortex®-M3
                                 @ hardfault or Busfault) is generated and this bit remains set until the next reset.
                                 @ This bit is set when PELOCK is set.
                                 @ 0: program memory unlocked
.EQU FLASH_PECR_PRGLOCK, 1<<1    @ 1: program memory locked
.EQU FLASH_PECR_PELOCK_N, 0      @ Bit 0  PELOCK: FLASH_PECR and data EEPROM lock
                                 @ This bit can only be written to 1. When it is set, it indicates that the FLASH_PECR register
                                 @ and data EEPROM are locked. It is cleared by hardware after detecting the unlock
                                 @ sequence. In the event of unsuccessful unlock operation or a third access to PEKEYR, a
                                 @ bus error (Cortex®-M3 hardfault or Busfault) is generated and this bit remains set until the
                                 @ next reset.
                                 @ When this bit is cleared, write access to the data EEPROM is allowed.
                                 @ 0: FLASH_PECR is unlocked
.EQU FLASH_PECR_PELOCK, 1        @ 1: FLASH_PECR is locked
@.END

@.ITEM FLASH_PDKEYR
@ Bits 31:0 PDKEYR[31:0]: RUN_PD in FLASH_ACR key
@ These bits represent the keys used to set the RUN_PD bit in the FLASH_ACR register.
.EQU FLASH_PDKEYR_PRKEY1, 0x04152637
.EQU FLASH_PDKEYR_PRKEY2, 0xFAFBFCFD
@.END

@.ITEM FLASH_PEKEYR
@ Bits 31:0 PEKEYR[31:0]: FLASH_PEC and data EEPROM key
@ These bits represent the keys to unlock the write access to the FLASH_PECR register and
@ data EEPROM.
.EQU FLASH_PEKEYR_PEKEY1, 0x89ABCDEF
.EQU FLASH_PEKEYR_PEKEY2, 0x02030405
@.END

@.ITEM FLASH_PRGKEYR
@ Bits 31:0 PRGKEYR[31:0]: Program memory key
@ These bits represent the keys to unlock the program memory.
.EQU FLASH_PRGKEYR_PRGKEY1, 0x8C9DAEBF
.EQU FLASH_PRGKEYR_PRGKEY2, 0x13141516
@.END

@.ITEM FLASH_OPTKEYR
@ Bits 31:0 OPTKEYR: Option byte key
@ These bits represent the keys to unlock the write access to the option byte block.
.EQU FLASH_OPTKEYR_OPTKEY1, 0xFBEAD9C8
.EQU FLASH_OPTKEYR_OPTKEY2, 0x24252627
@.END

@.ITEM FLASH_SR
.EQU  FLASH_SR_RDERR_N, 13       @ Bit 13 RDERR: Read protected error
.EQU  FLASH_SR_RDERR, 1 << 13    @ Set by hardware when an address to be read through the Dbus belongs to a read-protected
                                 @ (PCROP) part of the memory.
                                 @ Cleared by writing 1.
.EQU  FLASH_SR_OPTERRUSR_N, 12   @ Bit 12 OPTVERRUSR: Option UserValidity Error.
                                 @ Set by hardware when the option byte USER has an incorrect complement nUSER when
                                 @ loading option bytes into FLASH_OBR register (see Section 3.5: Option byte description).
.EQU  FLASH_SR_OPTERRUSR, 1 << 12    @ Cleared by writing 1.
                                 @ If user option byte USER/nUSER has not been properly loaded
                                 @ OPTVERRUSR is set again. Consequently, an interrupt is generated as soon as ERRIE is
                                 @ set.
                           @ Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.
.EQU  FLASH_SR_OPTVERR_N, 11     @ Bit 11 OPTVERR: Option validity error
                                 @ Set by hardware when some option byte has an incorrect complement when loading option
                                 @ bytes into FLASH_OBR register (see Section 3.5: Option byte description).
.EQU  FLASH_SR_OPTVERR, 1<<11    @ Cleared by writing 1.
                                 @ If some option byte has not been properly loaded
                                 @ OPTVERR is set again. Consequently, an interrupt is generated as soon as ERRIE is set.
.EQU  FLASH_SR_SIZEERR_N, 10     @ Bit 10  SIZERR: Size error
                                 @ Set by hardware when the size of the data to program is prohibited.
.EQU  FLASH_SR_SIZEERR, 1 << 10    @ Cleared by writing it to 1.
.EQU  FLASH_SR_PGAERR_N, 9       @ Bit 9  PGAERR: Programming alignment error
                                 @ Set by hardware when the data to program cannot be contained in a given half page or
                                 @ double word.
.EQU  FLASH_SR_PGAERR, 1 << 9    @ Cleared by writing it to 1.
.EQU  FLASH_SR_WRPERR_N, 8       @ Bit 8  WRPERR: Write protected error
                                 @ Set by hardware when an address to be erased/programmed belongs to a write-protected
                                 @ part of the memory.
.EQU  FLASH_SR_WRPERR, 1 << 8    @ Cleared by writing it to 1.
.EQU  FLASH_SR_READY_N, 3        @ Bit 3 READY: Flash memory module ready after low-power mode
                                 @ This bit is set and cleared by hardware.
                                 @ 0: Flash memory module is not ready
.EQU  FLASH_SR_READY, 1 << 3     @ 1: Flash memory module is ready
.EQU  FLASH_SR_ENDHV_N, 2        @ Bit 2 ENDHV: End of high voltage
                                 @ This bit is set and cleared by hardware.
                                 @ 0: High voltage still applied during write/erase operations
.EQU  FLASH_SR_ENDHV, 1 << 2     @ 1: End of high voltage
.EQU  FLASH_SR_EOP_N, 1          @ Bit 1  EOP: End of operation
                                 @ This bit is set by hardware if the high voltage stops being applied and programming has not
                                 @ been aborted. It is cleared by software (by writing it to 1).
                                 @ 0: No EOP event occurred
.EQU  FLASH_SR_EOP, 1<<1         @ 1: An EOP event occured. An interrupt is generated if EOPIE is set
.EQU  FLASH_SR_BSY_N, 0          @ Bit 0  BSY: Write/erase operations in progress
                                 @ 0: Write/erase operation not in progress
.EQU  FLASH_SR_BSY  , 1          @ 1: Write/erase operation in progress
@.END

@.ITEM FLASH_OBR
.EQU  FLASH_OBR_nBFB2_N, 23      @ Bit 2 3 nBFB2:   Boot from Bank2. This bit contains the user option byte loaded by the OBL.
                                 @ This bit is used to select the boot space between Flash Bank2/Bank1 and another boot
                                 @ sources.
                                 @ 0: System bootloader is started after reset (boot from system memory). Bootloader in next
                                 @ executes checks in following order:
                                 @ - If content of first word of Bank2 is valid SRAM address then is jumped to Bank2 (boot from
                                 @ Bank2).
                                 @ - If content of first word of Bank1 is valid SRAM address then is jumped to Bank1 (boot from
                                 @ Bank1).
                                 @ - Otherwise system bootloader is executed.
.EQU  FLASH_OBR_nBFB2, 1<<23     @ 1: Boot space is selected by BOOT0 and BOOT1 pins (see Table 6: Boot modes).
                                 @ This bit is read only.
                           @ Note: This bit is available in Cat.4, Cat.5 and Cat.6 devices only.
.EQU  FLASH_OBR_nRST_STDBY_N, 22
.EQU  FLASH_OBR_nRST_STOP_N, 21
.EQU  FLASH_OBR_IWDG_SW_N, 20
.EQU  FLASH_OBR_BOR_LEV_N, 16      @ Bits 19:16:BOR_LEV[3:0]: Brownout reset threshold level
                                   @ 0xxx: BOR OFF: Reset threshold level for the 1.45 V-1.55 V voltage range (power down
                                   @ only)
                                   @ In this particular case, VDD33 must have been above BOR LEVEL 1 to start the device OBL
                                   @ sequence in order to disable the BOR. The power-down is then monitored by the PDR.
                             @ Note: If the BOR is disabled, a “grey zone” exists between 1.65 V and the VPDR threshold
                                   @ (this means that VDD33 may be below the minimum operating voltage (1.65 V) without
                                   @ causing a reset until it crosses the VPDR threshold)
.EQU  FLASH_OBR_BOR_LEV_1, 8<<16   @ 1000: BOR LEVEL 1: Reset threshold level for 1.69 V-1.8 V voltage range (power on)
.EQU  FLASH_OBR_BOR_LEV_2, 9<<16   @ 1001: BOR LEVEL 2: Reset threshold level for 1.94 V-2.1 V voltage range (power on)
.EQU  FLASH_OBR_BOR_LEV_3, 10<<16  @ 1010: BOR LEVEL 3: Reset threshold level for 2.3 V-2.49 V voltage range (power on)
.EQU  FLASH_OBR_BOR_LEV_4, 11<<16  @ 1011: BOR LEVEL 4: Reset threshold level for 2.54 V-2.74 V voltage range (power on)
.EQU  FLASH_OBR_BOR_LEV_5, 12<<16  @ 1100: BOR LEVEL 5: Reset threshold level for 2.77 V-3.0 V voltage range (power on)
                                   @ These bits are read only.
.EQU  FLASH_OBR_SPRMOD_N, 8      @ Bit 8 SPRMOD: Sector protection mode selection
                                 @ 0: WRP[i]=1 bit in FLASH_WRPRx registers defines sector write protection
.EQU  FLASH_OBR_SPRMOD, 1<<8     @ 1: WRP[i]=0 bit in FLASH_WRPRx registers defines sector write and read (PCROP)
                                 @ protection.
                                 @ See Section 3.7.4: PCROP for details.
.EQU  FLASH_OBR_RDPRT_N, 0       @ Bits 7:0 RDPRT[7:0]: Read protection
                                 @ These bits contain the read protection option level loaded by the OBL.
.EQU  FLASH_OBR_RDPRT_NOACT, 0xAA    @ 0xAA: Level 0, read protection not active
.EQU  FLASH_OBR_RDPRT_ACTM, 0xCC     @ 0xCC: Level 2, read protection active
                                 @ Others: Level 1, read protection of memories active. Default configuration after option byte
                                 @ erase.
@.END

