@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module

@ +------------------------------------------------------------------+
@ |                     มเ็๎โ๛ๅ ๊๎ํ๑๒เํ๒๛ USART ่ UART               |
@ |                              STM32L1xxx                          |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.item     APB1PERIPH_BASE
.EQU  USART2_BASE   , APB1PERIPH_BASE + 0x4400
.EQU  USART3_BASE   , APB1PERIPH_BASE + 0x4800
.EQU  USART4_BASE   , APB1PERIPH_BASE + 0x4C00
.EQU  USART5_BASE   , APB1PERIPH_BASE + 0x5000
.EQU  USART2        , PERIPH_BASE + USART2_BASE
.EQU  USART3        , PERIPH_BASE + USART3_BASE
.EQU  USART4        , PERIPH_BASE + USART4_BASE
.EQU  USART5        , PERIPH_BASE + USART5_BASE
@.END

@.ITEM     APB2PERIPH_BASE
.EQU  USART1_BASE   , APB2PERIPH_BASE + 0x3800
.EQU  USART1        , PERIPH_BASE + USART1_BASE
@.END

@.item    USART1 USART1_BASE  USART2 USART2_BASE USART3 USART3_BASE USART4 UART4_BASE USART5 UART5_BASE
.equ  USART_SR           , 0x00    @ USART Status register
.equ  USART_DR           , 0x04    @ USART Data register
.equ  USART_BRR          , 0x08    @ USART Baud rate register
.equ  USART_CR1          , 0x0C    @ USART Control register 1
.equ  USART_CR2          , 0x10    @ USART Control register 2
.equ  USART_CR3          , 0x14    @ USART Control register 3
.equ  USART_GTPR         , 0x18    @ USART Guard time and prescaler register
@.END

@.item     USART_SR
.EQU  USART_SR_PE_N , 0          @ Bit 0 PE: Parity error
                                 @ This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a
                                 @ software sequence (a read from the status register followed by a read or write access to the
                                 @ USART_DR data register). The software must wait for the RXNE flag to be set before
                                 @ clearing the PE bit.
                                 @ An interrupt is generated if PEIE = 1 in the USART_CR1 register.
                                 @ 0: No parity error
.EQU  USART_SR_PE , 1            @ 1: Parity error
.EQU  USART_SR_FE_N , 1          @ Bit 1 FE: Framing error
                                 @ This bit is set by hardware when a de-synchronization, excessive noise or a break character
                                 @ is detected. It is cleared by a software sequence (an read to the USART_SR register
                                 @ followed by a read to the USART_DR register).
                                 @ 0: No Framing error is detected
.EQU  USART_SR_FE_N , 1 << 1     @ 1: Framing error or break character is detected
                                 @ Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit
                                 @ which itself generates an interrupt. If the word currently being transferred causes both
                                 @ frame error and overrun error, it is transferred and only the ORE bit is set.
                                 @ An interrupt is generated on FE flag in case of Multi Buffer communication if the EIE bit
                                 @ is set.
.EQU  USART_SR_NE_N , 2          @ Bit 2 NF: Noise detected flag
                                 @ This bit is set by hardware when noise is detected on a received frame. It is cleared by a
                                 @ software sequence (an read to the USART_SR register followed by a read to the
                                 @ USART_DR register).
                                 @ 0: No noise is detected
.EQU  USART_SR_NE   , 1 << 2     @ 1: Noise is detected
                                 @ Note: This bit does not generate interrupt as it appears at the same time as the RXNE bit
                                 @ which itself generates an interrupting interrupt is generated on NF flag in case of Multi
                                 @ Buffer communication if the EIE bit is set.
                           @ Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT
                                 @ bit to 1 to increase the USART tolerance to deviations (Refer to Section 27.3.5: USART
                                 @ receiver tolerance to clock deviation on page 714).
.EQU  USART_SR_ORE_N, 3          @ Bit 3 ORE: Overrun error
                                 @ This bit is set by hardware when the word currently being received in the shift register is
                                 @ ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if
                                 @ RXNEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the
                                 @ USART_SR register followed by a read to the USART_DR register).
                                 @ 0: No Overrun error
.EQU  USART_SR_ORE  , 1 << 3     @ 1: Overrun error is detected
                                 @ Note: When this bit is set, the RDR register content is not lost but the shift register is
                                 @ overwritten. An interrupt is generated on ORE flag in case of Multi Buffer
                                 @ communication if the EIE bit is set.
.EQU  USART_SR_IDLE_N, 4         @ Bit 4 IDLE: IDLE line detected
                                 @ This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the
                                 @ IDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the
                                 @ USART_SR register followed by a read to the USART_DR register).
                                 @ 0: No Idle Line is detected
.EQU  USART_SR_IDLE , 1 << 4     @ 1: Idle Line is detected
                           @ Note: The IDLE bit is not set again until the RXNE bit has been set itself (a new idle line
                                 @ occurs).
.EQU  USART_SR_RXNE_N, 5         @  RXNE: Read data register not empty
                                 @ This bit is set by hardware when the content of the RDR shift register has been transferred
                                 @ to the USART_DR register. An interrupt is generated if RXNEIE=1 in the USART_CR1
                                 @ register. It is cleared by a read to the USART_DR register. The RXNE flag can also be
                                 @ cleared by writing a zero to it. This clearing sequence is recommended only for multibuffer
                                 @ communication.
                                 @ 0: Data is not received
.EQU  USART_SR_RXNE , 1 << 5     @ 1: Received data is ready to be read.
.EQU  USART_SR_TC_N , 6          @ Bit 6 TC: Transmission complete
                                 @ This bit is set by hardware if the transmission of a frame containing data is complete and if
                                 @ TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by
                                 @ a software sequence (a read from the USART_SR register followed by a write to the
                                 @ USART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing
                                 @ sequence is recommended only for multibuffer communication.
                                 @ 0: Transmission is not complete
.EQU  USART_SR_TC   , 1 << 6     @ 1: Transmission is complete
.EQU  USART_SR_TXE_N, 7          @ Bit 7 TXE: Transmit data register empty
                                 @ This bit is set by hardware when the content of the TDR register has been transferred into
                                 @ the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It
                                 @ is cleared by a write to the USART_DR register.
                                 @ 0: Data is not transferred to the shift register
.EQU  USART_SR_TXE  , 1 << 7     @ 1: Data is transferred to the shift register)
                           @ Note: This bit is used during single buffer transmission.
.equ  USART_SR_LBD_N     , 8     @ Bit 8 LBD: LIN break detection flag
                                 @ This bit is set by hardware when the LIN break is detected. It is cleared by software (by
                                 @ writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
                                 @ 0: LIN Break not detected
.EQU  USART_SR_LBD  , 1 << 8     @ 1: LIN break detected
@ Note: An interrupt is generated when LBD=1 if LBDIE=1
.EQU  USART_SR_CTS_N, 9          @ Bit 9 CTS: CTS flag
                                 @ This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by
                                 @ software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3
                                 @ register.
                                 @ 0: No change occurred on the CTS status line
.EQU  USART_SR_CTS  , 1 << 9     @ 1: A change occurred on the CTS status line
@.END

@.item     USART_DR
.equ  USART_DR_DR        , 0x01FF    @Data value
@.END

@.item     USART_BRR
.equ  USART_BRR_DIV_Fraction, 0x000F    @ Bits 3:0 DIV_Fraction[3:0]: fraction of USARTDIV
.equ  USART_BRR_DIV_Fraction_N, 0       @ These 4 bits define the fraction of the USART Divider (USARTDIV). When OVER8=1, the
                                        @ DIV_Fraction3 bit is not considered and must be kept cleared.
.equ  USART_BRR_DIV_Mantissa, 0xFFF0    @ Bits 15:4 DIV_Mantissa[11:0]: mantissa of USARTDIV
.equ  USART_BRR_DIV_Mantissa_N, 4       @ These 12 bits define the mantissa of the USART Divider (USARTDIV)
@.END

@.item     USART_CR1
.equ  USART_CR1_SBK      , 1         @ Bit 0 SBK: Send break
                                     @ This bit set is used to send break characters. It can be set and cleared by software. It should
                                     @ be set by software, and is reset by hardware during the stop bit of break.
                                     @ 0: No break character is transmitted.
                                     @ 1: Break character is transmitted.
.equ  USART_CR1_RWU      , 1<<1      @ Bit 1 RWU: Receiver wakeup
                                     @ This bit determines if the USART is in mute mode or not. It is set and cleared by software
                                     @ and can be cleared by hardware when a wakeup sequence is recognized.
                                     @ 0: Receiver in active mode
                                     @ 1: Receiver in mute mode
                               @ Note: Before selecting Mute mode (by setting the RWU bit) the USART must first receive a
                                     @ data byte, otherwise it cannot function in Mute mode with wakeup by Idle line detection.
                                     @ In Address Mark Detection wakeup configuration (WAKE bit=1) the RWU bit cannot be
                                     @ modified by software while the RXNE bit is set.
.equ  USART_CR1_RE       , 1<<2      @ Bit 2 RE: Receiver enable
                                     @ This bit enables the receiver. It is set and cleared by software.
                                     @ 0: Receiver is disabled
                                     @ 1: Receiver is enabled and begins searching for a start bit
.equ  USART_CR1_TE       , 1<<3      @ Bit 3 TE: Transmitter enable
                                     @ This bit enables the transmitter. It is set and cleared by software.
                                     @ 0: Transmitter is disabled
                                     @ 1: Transmitter is enabled
                                     @ Note: During transmission, a 0 pulse on the TE bit (0 followed by 1) sends a preamble
                                     @ (idle line) after the current word, except in smartcard mode.
                                     @ When TE is set, there is a 1 bit-time delay before the transmission starts.
.equ  USART_CR1_IDLEIE   , 1<<4      @ Bit 4 IDLEIE: IDLE interrupt enable
                                     @ This bit is set and cleared by software.
                                     @ 0: Interrupt is inhibited
                                     @ 1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register
.equ  USART_CR1_RXNEIE   , 1<<5      @ Bit 5 RXNEIE: RXNE interrupt enable
                                     @ This bit is set and cleared by software.
                                     @ 0: Interrupt is inhibited
                                     @ 1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_SR
                                     @ register
.equ  USART_CR1_TCIE     , 1<<6      @ Bit 6 TCIE: Transmission complete interrupt enable
                                     @ This bit is set and cleared by software.
                                     @ 0: Interrupt is inhibited
                                     @ 1: An USART interrupt is generated whenever TC=1 in the USART_SR register
.equ  USART_CR1_TXEIE    , 1<<7      @ Bit 7 TXEIE: TXE interrupt enable
                                     @ This bit is set and cleared by software.
                                     @ 0: Interrupt is inhibited
                                     @ 1: An USART interrupt is generated whenever TXE=1 in the USART_SR register
.equ  USART_CR1_PEIE     , 1<<8      @ Bit 8 PEIE: PE interrupt enable
                                     @ This bit is set and cleared by software.
                                     @ 0: Interrupt is inhibited
                                     @ 1: An USART interrupt is generated whenever PE=1 in the USART_SR register
.equ  USART_CR1_PS       , 1<<9      @ Bit 9 PS: Parity selection
                                     @ This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
                                     @ bit set). It is set and cleared by software. The parity is selected after the current byte.
                                     @ 0: Even parity
                                     @ 1: Odd parity
.equ  USART_CR1_PCE      , 1<<10     @ Bit 10 PCE: Parity control enable
                                     @ This bit selects the hardware parity control (generation and detection). When the parity
                                     @ control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
                                     @ if M=0) and parity is checked on the received data. This bit is set and cleared by software.
                                     @ Once it is set, PCE is active after the current byte (in reception and in transmission).
                                     @ 0: Parity control disabled
                                     @ 1: Parity control enabled
.equ  USART_CR1_WAKE     , 1<<11     @ Bit 11 WAKE: Wakeup method
                                     @ This bit determines the USART wakeup method, it is set or cleared by software.
                                     @ 0: Idle Line
                                     @ 1: Address Mark
.equ  USART_CR1_M        , 1<<12     @ Bit 12 M: Word length
                                     @ This bit determines the word length. It is set or cleared by software.
                                     @ 0: 1 Start bit, 8 Data bits, n Stop bit
                                     @ 1: 1 Start bit, 9 Data bits, n Stop bit
                                     @ Note: The M bit must not be modified during a data transfer (both transmission and reception)
.equ  USART_CR1_UE       , 1<<13     @ Bit 13 UE: USART enable
                                     @ When this bit is cleared, the USART prescalers and outputs are stopped and the end of the
                                     @ current byte transfer in order to reduce power consumption. This bit is set and cleared by
                                     @ software.
                                     @ 0: USART prescaler and outputs disabled
                                     @ 1: USART enabled
.equ  USART_CR1_OVER8    , 1<<15     @ Bit 15 OVER8: Oversampling mode
                                     @ 0: oversampling by 16
                                     @ 1: oversampling by 8
                                     @ Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when
                                     @ SCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to 0 by hardware.
@.END

@.item     USART_CR2
.equ  USART_CR2_ADD_N    , 0         @ Bits 3:0 ADD[3:0]: Address of the USART node
                                     @ This bit-field gives the address of the USART node.
                                     @ This is used in multiprocessor communication during mute mode, for wake up with address mark
                                     @ detection.
.equ  USART_CR2_LBDL     , 1<<5      @ Bit 5 LBDL: lin break detection length
                                     @ This bit is for selection between 11 bit or 10 bit break detection.
                                     @ 0: 10-bit break detection
                                     @ 1: 11-bit break detection
.equ  USART_CR2_LBDIE    , 1<<6      @ Bit 6 LBDIE: LIN break detection interrupt enable
                                     @ Break interrupt mask (break detection using break delimiter).
                                     @ 0: Interrupt is inhibited
                                     @ 1: An interrupt is generated whenever LBD=1 in the USART_SR register
.equ  USART_CR2_LBCL     , 1<<8      @ Bit 8 LBCL: Last bit clock pulse
                                     @ This bit allows the user to select whether the clock pulse associated with the last data bit
                                     @ transmitted (MSB) has to be output on the CK pin in synchronous mode.
                                     @ 0: The clock pulse of the last data bit is not output to the CK pin
                                     @ 1: The clock pulse of the last data bit is output to the CK pin
                                     @ 1: The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected
                                     @ by the M bit in the USART_CR1 register.
.equ  USART_CR2_CPHA     , 1<<9      @ Bit 9 CPHA: Clock phase
                                     @ This bit allows the user to select the phase of the clock output on the CK pin in synchronous mode.
                                     @ It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see figures
                                     @ 227 to 228)
                            @ Note: 0: The first clock transition is the first data capture edge
                                     @ 1: The second clock transition is the first data capture edge
.equ  USART_CR2_CPOL     , 1<<10     @ Bit 10 CPOL: Clock polarity
                                     @ This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode.
                                     @ It works in conjunction with the CPHA bit to produce the desired clock/data relationship
                                     @ 0: Steady low value on CK pin outside transmission window.
                                     @ 1: Steady high value on CK pin outside transmission window
.equ  USART_CR2_CLKEN    , 1<<11     @ Bit 11 CLKEN: Clock enable
                                     @ This bit allows the user to enable the CK pin.
                                     @ 0: CK pin disabled
                                     @ 1: CK pin enabled
.equ  USART_CR2_STOP_N   , 12        @ Bits 13:12 STOP: STOP bits
                                     @ These bits are used for programming the stop bits.
.EQU  USART_CR2_STOP_1, 0            @ 00: 1 Stop bit
.EQU  USART_CR2_STOP_0D5, 1 << 12    @ 01: 0.5 Stop bit
.EQU  USART_CR2_STOP_2, 2 << 12      @ 10: 2 Stop bits
.EQU  USART_CR2_STOP_1D5, 3 << 12    @ 11: 1.5 Stop bit
.equ  USART_CR2_STOP_0   , 0x1000    @Bit 0
.equ  USART_CR2_STOP_1   , 0x2000    @Bit 1
.equ  USART_CR2_LINEN    , 1<<14     @ Bit 14 LINEN: LIN mode enable
                                     @ This bit is set and cleared by software.
                                     @ 0: LIN mode disabled
                                     @ 1: LIN mode enabled
                                     @ The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBK bit in
                                     @ the USART_CR1 register, and to detect LIN Sync breaks.
@.END

@.item     USART_CR3
.equ  USART_CR3_EIE      , 1         @ Bit 0 EIE: Error interrupt enable
                                     @ Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
                                     @ error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_SR register) in
                                     @ case of Multi Buffer Communication (DMAR=1 in the USART_CR3 register).
                                     @ 0: Interrupt is inhibited
                                     @ 1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and FE=1 or
                                     @ ORE=1 or NF=1 in the USART_SR register.
.equ  USART_CR3_IREN     , 1<<1      @ Bit 1 IREN: IrDA mode enable
                                     @ This bit is set and cleared by software.
                                     @ 0: IrDA disabled
                                     @ 1: IrDA enabled
.equ  USART_CR3_IRLP     , 1<<2      @ Bit 2 IRLP: IrDA low-power
                                     @ This bit is used for selecting between normal and low-power IrDA modes
                                     @ 0: Normal mode
                                     @ 1: Low-power mode
.equ  USART_CR3_HDSEL    , 1<<3      @ Bit 3 HDSEL: Half-duplex selection
                                     @ Selection of Single-wire Half-duplex mode
                                     @ 0: Half duplex mode is not selected
                                     @ 1: Half duplex mode is selected
.equ  USART_CR3_NACK     , 1<<4      @ Bit 4 NACK: Smartcard NACK enable
                                     @ 0: NACK transmission in case of parity error is disabled
                                     @ 1: NACK transmission during parity error is enabled
.equ  USART_CR3_SCEN     , 1<<5      @ Bit 5 SCEN: Smartcard mode enable
                                     @ This bit is used for enabling Smartcard mode.
                                     @ 0: Smartcard Mode disabled
                                     @ 1: Smartcard Mode enabled
.equ  USART_CR3_DMAR     , 1<<6      @ Bit 6 DMAR: DMA enable receiver
                                     @ This bit is set/reset by software
                                     @ 1: DMA mode is enabled for reception
                                     @ 0: DMA mode is disabled for reception
.equ  USART_CR3_DMAT     , 1<<7      @ Bit 7 DMAT: DMA enable transmitter
                                     @ This bit is set/reset by software
                                     @ 1: DMA mode is enabled for transmission
                                     @ 0: DMA mode is disabled for transmission
.equ  USART_CR3_RTSE     , 1<<8      @ Bit 8 RTSE: RTS enable
                                     @ 0: RTS hardware flow control disabled
                                     @ 1: RTS interrupt enabled, data is only requested when there is space in the receive buffer.
                                     @ The transmission of data is expected to cease after the current character has been
                                     @ transmitted. The RTS output is asserted (tied to 0) when a data can be received.
.equ  USART_CR3_CTSE     , 1<<9      @ Bit 9 CTSE: CTS enable
                                     @ 0: CTS hardware flow control disabled
                                     @ 1: CTS mode enabled, data is only transmitted when the CTS input is asserted (tied to 0). If
                                     @ the CTS input is deasserted while a data is being transmitted, then the transmission is
                                     @ completed before stopping. If a data is written into the data register while CTS is asserted,
                                     @ the transmission is postponed until CTS is asserted.
.equ  USART_CR3_CTSIE    , 1<<10     @ Bit 10 CTSIE: CTS interrupt enable
                                     @ 0: Interrupt is inhibited
                                     @ 1: An interrupt is generated whenever CTS=1 in the USART_SR register
.equ  USART_CR3_ONEBIT   , 1<<11     @ Bit 11 ONEBIT: One sample bit method enable
                                     @ This bit allows the user to select the sample method. When the one sample bit method is
                                     @ selected the noise detection flag (NF) is disabled.
                                     @ 0: Three sample bit method
                                     @ 1: One sample bit method
                               @ Note: The ONEBIT feature applies only to data bits. It does not apply to START bit.
@.END

@.item     USART_GTPR
.equ  USART_GTPR_PSC_N   , 0         @ Bits 7:0 PSC[7:0]: Prescaler value
                                     @  In IrDA Low-power mode:
                                     @ PSC[7:0] = IrDA Low-Power Baud Rate
                                     @ Used for programming the prescaler for dividing the system clock to achieve the low-power
                                     @ frequency:
                                     @ The source clock is divided by the value given in the register (8 significant bits):
                                     @ 00000000: Reserved - do not program this value
                                     @ 00000001: divides the source clock by 1
                                     @ 00000010: divides the source clock by 2
                                     @ ...
                                     @  In normal IrDA mode: PSC must be set to 00000001.
                                     @  In smartcard mode:
                                     @ PSC[4:0]: Prescaler value
                                     @ Used for programming the prescaler for dividing the system clock to provide the smartcard
                                     @ clock.
                                     @ The value given in the register (5 significant bits) is multiplied by 2 to give the division factor
                                     @ of the source clock frequency:
                                     @ 00000: Reserved - do not program this value
                                     @ 00001: divides the source clock by 2
                                     @ 00010: divides the source clock by 4
                                     @ 00011: divides the source clock by 6
                                     @ ...
                                     @ Note: 1: Bits [7:5] have no effect if Smartcard mode is used.
.equ  USART_GTPR_GT_N    , 8         @ Bits 15:8 GT[7:0]: Guard time value
                                     @ This bit-field gives the Guard time value in terms of number of baud clocks.
                                     @ This is used in Smartcard mode. The Transmission Complete flag is set after this guard time
                                     @ value.
@.END

