@.CHARSET CP1251

@ +------------------------------------------------------------------+
@ |                       Оределения ADC (раздел 12)                  |
@ |                      STM32F030xxx \ STM32F070xxx                 |
@ +------------------------------------------------------------------+
.INCLUDE            "/src/inc/base.inc"

@.ITEM     APBPERIPH_BASE
.EQU  ADC_BASE      , APBPERIPH_BASE + 0x12400
.EQU  ADC           , PERIPH_BASE + ADC_BASE
@.END

@.ITEM     ADC ADC_BASE
.EQU  ADC_ISR       , 0x00    @ ADC interrupt and status register
.EQU  ADC_IER       , 0x04    @ ADC interrupt enable register
.EQU  ADC_CR        , 0x08    @ ADC control register
.EQU  ADC_CFGR1     , 0x0C    @ ADC configuration register 1
.EQU  ADC_CFGR2     , 0x10    @ ADC configuration register 2
.EQU  ADC_SMPR      , 0X14    @ ADC sampling time register
.EQU  ADC_TR        , 0x20    @ ADC watchdog threshold register
.EQU  ADC_CHSELR    , 0x28    @ ADC channel selection register
.EQU  ADC_DR        , 0x40    @ ADC data register
.EQU  ADC_CCR       , 0X308    @ ADC common configuration register
@.END

@.ITEM     ADC_ISR
.EQU  ADC_ISR_AWD   , 1 << 7    @ Analog watchdog flag
.EQU  ADC_ISR_OVR   , 1 << 4    @ ADC overrun
.EQU  ADC_ISR_EOSEQ , 1 << 3    @ End of sequence flag
.EQU  ADC_ISR_EOC   , 1 << 2    @ End of conversion flag
.EQU  ADC_ISR_EOSMP , 1 << 1    @ End of sampling flag
.EQU  ADC_ISR_ADRDY , 1 << 0    @ ADC ready
@.END

@.ITEM     ADC_IER
.EQU  ADC_IER_AWDIE , 1 << 7    @ Analog watchdog interrupt enable
.EQU  ADC_IER_OVRIE , 1 << 4    @ Overrun interrupt enable
.EQU  ADC_IER_EOSEQIE, 1 << 3    @ End of conversion sequence interrupt enable
.EQU  ADC_IER_EOCIE , 1 << 2    @ End of conversion interrupt enable
.EQU  ADC_IER_EOSMPIE, 1 << 1    @ End of sampling flag interrupt enable
.EQU  ADC_IER_ADRDYIE, 1 << 0    @ ADC ready interrupt enable
@.END

@.ITEM     ADC_CR
.EQU  ADC_CR_ADCAL  , 1 << 31    @ ADC calibration
.EQU  ADC_CR_ADSTP  , 1 << 4    @ ADC stop conversion command
.EQU  ADC_CR_ADSTART, 1 << 2    @ ADC start conversion command
.EQU  ADC_CR_ADDIS  , 1 << 1    @ ADC disable command
.EQU  ADC_CR_ADEN   , 1 << 0    @ ADC enable command
@.END

@.ITEM     ADC_CFGR1
.EQU  ADC_CFGR1_AWDCH_N, 26    @ AWDCH[4:0]: Analog watchdog channel selection
.EQU  ADC_CFGR1_AWDCH0, 0x00 << 26    @ ADC analog input Channel 0 monitored by AWD
.EQU  ADC_CFGR1_AWDCH1, 0x01 << 26    @ ADC analog input Channel 1 monitored by AWD
.EQU  ADC_CFGR1_AWDCH2, 0x02 << 26    @ ADC analog input Channel 2 monitored by AWD
.EQU  ADC_CFGR1_AWDCH3, 0x03 << 26    @ ADC analog input Channel 3 monitored by AWD
.EQU  ADC_CFGR1_AWDCH4, 0x04 << 26    @ ADC analog input Channel 4 monitored by AWD
.EQU  ADC_CFGR1_AWDCH5, 0x05 << 26    @ ADC analog input Channel 5 monitored by AWD
.EQU  ADC_CFGR1_AWDCH6, 0x06 << 26    @ ADC analog input Channel 6 monitored by AWD
.EQU  ADC_CFGR1_AWDCH7, 0x07 << 26    @ ADC analog input Channel 7 monitored by AWD
.EQU  ADC_CFGR1_AWDCH8, 0x08 << 26    @ ADC analog input Channel 8 monitored by AWD
.EQU  ADC_CFGR1_AWDCH9, 0x09 << 26    @ ADC analog input Channel 9 monitored by AWD
.EQU  ADC_CFGR1_AWDCH10, 0x0A << 26    @ ADC analog input Channel 10 monitored by AWD
.EQU  ADC_CFGR1_AWDCH11, 0x0B << 26    @ ADC analog input Channel 11 monitored by AWD
.EQU  ADC_CFGR1_AWDCH12, 0x0C << 26    @ ADC analog input Channel 12 monitored by AWD
.EQU  ADC_CFGR1_AWDCH13, 0x0D << 26    @ ADC analog input Channel 13 monitored by AWD
.EQU  ADC_CFGR1_AWDCH14, 0x0E << 26    @ ADC analog input Channel 14 monitored by AWD
.EQU  ADC_CFGR1_AWDCH15, 0x0F << 26    @ ADC analog input Channel 15 monitored by AWD
.EQU  ADC_CFGR1_AWDCH16, 0x10 << 26    @ ADC analog input Channel 16 monitored by AWD
.EQU  ADC_CFGR1_AWDCH17, 0x11 << 26    @ ADC analog input Channel 17 monitored by AWD
.EQU  ADC_CFGR1_AWDCH18, 0x12 << 26    @ ADC analog input Channel 18 monitored by AWD
.EQU  ADC_CFGR1_AWDEN, 1 << 23    @ Analog watchdog enable
.EQU  ADC_CFGR1_AWDSGL, 1 << 22    @ Enable the watchdog on a single channel or on all channels
.EQU  ADC_CFGR1_DISCEN, 1 << 16    @ Discontinuous mode
.EQU  ADC_CFGR1_AUTOFF, 1 << 15    @ Auto-off mode
.EQU  ADC_CFGR1_WAIT, 1 << 14    @ Wait conversion mode
.EQU  ADC_CFGR1_CONT, 1 << 13    @ Single / continuous conversion mode
.EQU  ADC_CFGR1_OVRMOD, 1 << 12    @ Overrun management mode
.EQU  ADC_CFGR1_EXTEN_N, 10    @ EXTEN[1:0]: External trigger enable and polarity selection
.EQU  ADC_CFGR1_EXTEN0, 0x00 << 10    @ 00: Hardware trigger detection disabled (conversions can be started by software)
.EQU  ADC_CFGR1_EXTEN1, 0x01 << 10    @ 01: Hardware trigger detection on the rising edge
.EQU  ADC_CFGR1_EXTEN2, 0x02 << 10    @ 10: Hardware trigger detection on the falling edge
.EQU  ADC_CFGR1_EXTEN3, 0x03 << 10    @ 11: Hardware trigger detection on both the rising and falling edges
.EQU  ADC_CFGR1_EXTSEL_N, 6    @ EXTSEL[2:0]: External trigger selection
.EQU  ADC_CFGR1_EXTSEL0, 0x00 << 6    @ 000: TRG0
.EQU  ADC_CFGR1_EXTSEL1, 0x01 << 6    @ 001: TRG1
.EQU  ADC_CFGR1_EXTSEL2, 0x02 << 6    @ 010: TRG2
.EQU  ADC_CFGR1_EXTSEL3, 0x03 << 6    @ 011: TRG3
.EQU  ADC_CFGR1_EXTSEL4, 0x04 << 6    @ 100: TRG4
.EQU  ADC_CFGR1_EXTSEL5, 0x05 << 6    @ 101: TRG5
.EQU  ADC_CFGR1_EXTSEL6, 0x06 << 6    @ 110: TRG6
.EQU  ADC_CFGR1_EXTSEL7, 0x07 << 6    @ 111: TRG7
.EQU  ADC_CFGR1_ALIGN, 1 << 5    @ Data alignment
.EQU  ADC_CFGR1_RES_N, 3      @ RES[1:0]: Data resolution
.EQU  ADC_CFGR1_RES0, 0x00 << 3    @ 00: 12 bits
.EQU  ADC_CFGR1_RES1, 0x01 << 3    @ 01: 10 bits
.EQU  ADC_CFGR1_RES2, 0x02 << 3    @ 10: 8 bits
.EQU  ADC_CFGR1_RES3, 0x03 << 3    @ 11: 6 bits
.EQU  ADC_CFGR1_SCANDIR, 1 << 2    @ Scan sequence direction
.EQU  ADC_CFGR1_DMACFG, 1 << 1    @ Direct memory access configuration
.EQU  ADC_CFGR1_DMAEN, 1 << 0    @ Direct memory access enable
@.END

@.ITEM     ADC CFGR2
.EQU  ADC_CFGR2_CKMODE_N, 30    @ CKMODE[1:0]: ADC clock mode
.EQU  ADC_CFGR2_CKMODE0, 0x00 << 30    @ 00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
.EQU  ADC_CFGR2_CKMODE1, 0x01 << 30    @ 01: PCLK/2 (Synchronous clock mode)
.EQU  ADC_CFGR2_CKMODE2, 0x02 << 30    @ 10: PCLK/4 (Synchronous clock mode)
.EQU  ADC_CFGR2_CKMODE3, 0x03 << 30    @ 11: Reserved
@.END

@.ITEM     ADC_SMPR
.EQU  ADC_SMPR_SMP_N, 0       @ SMP[2:0]: Sampling time selection
.EQU  ADC_SMPR_SMP0 , 0X00 << 0    @ 000: 1.5 ADC clock cycles
.EQU  ADC_SMPR_SMP1 , 0X01 << 0    @ 001: 7.5 ADC clock cycles
.EQU  ADC_SMPR_SMP2 , 0X02 << 0    @ 010: 13.5 ADC clock cycles
.EQU  ADC_SMPR_SMP3 , 0X03 << 0    @ 011: 28.5 ADC clock cycles
.EQU  ADC_SMPR_SMP4 , 0X04 << 0    @ 100: 41.5 ADC clock cycles
.EQU  ADC_SMPR_SMP5 , 0X05 << 0    @ 101: 55.5 ADC clock cycles
.EQU  ADC_SMPR_SMP6 , 0X06 << 0    @ 110: 71.5 ADC clock cycles
.EQU  ADC_SMPR_SMP7 , 0X07 << 0    @ 111: 239.5 ADC clock cycles
@.END

@.ITEM     ADC_TR
.EQU  ADC_TR_HT_N   , 16      @ HT[11:0]: Analog watchdog higher threshold
.EQU  ADC_TR_LT_N   , 0       @ LT[11:0]: Analog watchdog lower threshold
@.END

@.ITEM     ADC_CHSELR
.EQU  ADC_CHSELR_CHSEL_N, 0    @ Channel selection
.EQU  ADC_CHSELR_CHSEL0, 1 << 0    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL1, 1 << 1    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL2, 1 << 2    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL3, 1 << 3    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL4, 1 << 4    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL5, 1 << 5    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL6, 1 << 6    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL7, 1 << 7    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL8, 1 << 8    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL9, 1 << 9    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL10, 1 << 10    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL11, 1 << 11    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL12, 1 << 12    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL13, 1 << 13    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL14, 1 << 14    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL15, 1 << 15    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL16, 1 << 16    @ CHSEL: Channel selection
.EQU  ADC_CHSELR_CHSEL17, 1 << 17    @ CHSEL: Channel selection
@.END

@.ITEM     ADC_DR
.EQU  ADC_DR_DATA_N , 0       @ DATA[15:0]: Converted data
@.END

@.ITEM     ADC_CCR
.EQU  ADC_CCR_TSEN  , 1 << 23    @ Temperature sensor enable
.EQU  ADC_CCR_VREFEN, 1 << 22    @ Vrefint enable
@.END




