@GNU AS
@.CHARSET =CP1251 ( Cyrillic )

@.DESC     type=module
@ +------------------------------------------------------------------+
@ |               Константы  System control block (SCB)              |
@ |                             Cortex-M0                            |
@ +------------------------------------------------------------------+
@.ENDDESC

.INCLUDE            "/src/inc/base.inc"

@.ITEM     CORE
.EQU  SCB_BASE      , CORE_BASE + 0xED00    @ System control block ( SCB )
@.END

@.ITEM     SCB_BASE
.EQU  SCB_CPUID     , 0x00     @ CPUID base register (SCB_CPUID)
.EQU  SCB_ICSR      , 0x04     @ Interrupt control and state register (ICSR)
.EQU  SCB_AIRCR     , 0x0C     @ Application interrupt and reset control register (AIRCR)
.EQU  SCB_SCR       , 0x10     @ System control register (SCR)
.EQU  SCB_CCR       , 0x14     @ Configuration an d co ntrol register (CCR)
.EQU  SCB_SHPR2     , 0x1C     @ System handler priority registers (SHPR2)
.EQU  SCB_SHPR3     , 0x20     @ System handler priority registers (SHPR3)
@.END

@.ITEM     SCB_CPUID
.EQU  SCB_CPUID_IMPLEMENTER_N, 24                  @ Bits 31:24 Implementer: Implementer code
.EQU  SCB_CPUID_IMPLEMENTER, 0X41 << 24            @ 0x41: Arm
.EQU  SCB_CPUID_VARIANT_N, 20                      @ Bits 23:20 Variant: Variant number: The r value in the rnpn product revision identifier
.EQU  SCB_CPUID_VARIANT, 0X00 << 20                @ 0x00: REVISION 0
.EQU  SCB_CPUID_CONSANT_N, 16                      @ Bits 19:16 Constant: Reads as 0xC
.EQU  SCB_CPUID_CONSTANT, 0xF << 16                @ 0xC
.EQU  SCB_CPUID_PARTNO_N, 4                        @ Bits 15:4 PartNo: Part number of the processor
.EQU  SCB_CPUID_CONSTANT, 0xC24 << 4               @ 0xC20 = Cortex-M0
.EQU  SCB_CPUID_REVISION_N, 0                      @ Bits 3:0 Revision: Revision number The p value in the rnpn product revision identifier, indicates patch release
.EQU  SCB_CPUID_REVISION, 1                        @ 0x0: = patch 0
@.END

@.ITEM     SCB_ICSR
.EQU  SCB_ICSR_NMIPENDSET, 1 << 31                 @ Bit 31 NMIPENDSET: NMI set-pending bit.
                                                   @ Write:
                                                   @ 0: No effect
                                                   @ 1: Change NMI exception state to pending.
                                                   @ Read:
                                                   @ 0: NMI exception is not pending
                                                   @ 1: NMI exception is pending
                                                   @ Because NMI is the highest-priority exception, normally the processor enter the NMI
                                                   @ exception handler as soon as it registers a write of 1 to this bit, and entering the handler clears
                                                   @ this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is
                                                   @ reasserted while the processor is executing that handler.
.EQU  SCB_ICSR_PENDSVSET, 1 << 28                  @ Bit 28 PENDSVSET: PendSV set-pending bit.
                                                   @ Write:
                                                   @ 0: No effect
                                                   @ 1: Change PendSV exception state to pending.
                                                   @ Read:
                                                   @ 0: PendSV exception is not pending
                                                   @ 1: PendSV exception is pending
                                                   @ Writing 1 to this bit is the only way to set the PendSV exception state to pending.
.EQU  SCB_ICSR_PENDSVCLR, 1 << 27                  @ Bit 27 PENDSVCLR: PendSV clear-pending bit. This bit is write-only. On a read, value is unknown.
                                                   @ 0: No effect
                                                   @ 1: Removes the pending state from the PendSV exception.
.EQU  SCB_ICSR_PENDSTSET, 1 << 26                  @ Bit 26 PENDSTSET: SysTick exception set-pending bit.
                                                   @ Write:
                                                   @ 0: No effect
                                                   @ 1: Change SysTick exception state to pending
                                                   @ Read:
                                                   @ 0: SysTick exception is not pending
                                                   @ 1: SysTick exception is pending
.EQU  SCB_ICSR_PENDSTCLR, 1 << 25                  @ Bit 25 PENDSTCLR: SysTick exception clear-pending bit. Write-only. On a read, value is unknown.
                                                   @ 0: No effect
                                                   @ 1: Removes the pending state from the SysTick exception.
.EQU  SCB_ICSR_ISRPENDING, 1 << 22                 @ Bit 22 ISRPENDING: Interrupt pending flag, excluding NMI and Faults.
                                                   @ 0: Interrupt not pending
                                                   @ 1: Interrupt pending
.EQU  SCB_ICSR_VECTPENDING_N, 12                   @ Bits 17:12 VECTPENDING: Pending vector. Indicates the exception number of the highest priority
                                                   @ pending enabled exception.
                                                   @ 0: No pending exceptions
                                                   @ Other values: The exception number of the highest priority pending enabled exception
.EQU  SCB_ICSR_VECTACTIVE_N, 0                     @ Bits 5:0 VECTACTIVE Active vector. Contains the active exception number:
                                                   @ 0: Thread mode
                                                   @ Other values: The exception number(1) of the currently active exception.
                                                   @ Note: Subtract 16 from this value to obtain CMSIS IRQ number required to index into the
                                                   @ Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending, or Priority Registers,
                                                   @ see Table 6 on page 14.
@.END

@.ITEM     SCB_AIRCR
.EQU  SCB_AIRCR_VECTKEYSTAT_N, 16                  @ Bits 31:16 Reserved / VECTKEY Register key
                                                   @ Reads as unknown
.EQU  SCB_AIRCR_ENDIANESS, 1<<15                   @ Bit 15 ENDIANESS Data endianness bit
                                                   @ Reads as 0.
                                                   @ 0: Little-endian
.EQU  SCB_AIRCR_SYSRESETREQ, 1 << 2                @ Bit 2 SYSRESETREQ System reset request
                                                   @ Reads as 0.
                                                   @ 0: No system reset request
                                                   @ 1: Asserts a signal to the outer system that requests a reset.
.EQU  SCB_AIRCR_VECTCLRACTIVE, 1 << 1              @ Bit 1 VECTCLRACTIVE
                                                   @ Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to
                                                   @this bit, otherwise behavior is unpredictable.
@.END

@.ITEM     SCB_SCR
.EQU  SCB_SCR_SEVEONPEND, 1 << 4                   @ Bit 4 SEVEONPEND Send Event on Pending bit
                                                   @ When an event or interrupt enters pending state, the event signal wakes up the processor from
                                                   @ WFE. If the processor is not waiting for an event, the event is registered and affects the next
                                                   @ WFE.
                                                   @ The processor also wakes up on execution of an SEV instruction or an external event
                                                   @ 0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are
                                                   @ excluded
                                                   @ 1: Enabled events and all interrupts, including disabled interrupts, can wakeup the
                                                   @ processor
.EQU  SCB_SCR_SLEEPDEEP, 1 << 2                    @ Bit 2 SLEEPDEEP
                                                   @ Controls whether the processor uses sleep or deep sleep as its low power mode:
                                                   @ 0: Sleep
                                                   @ 1: Deep sleep
.EQU  SCB_SCR_SLEEPONEXIT, 1 << 1                  @ Bit 1 SLEEPONEXIT
                                                   @ Configures sleep-on-exit when returning from Handler mode to Thread mode. Setting this bit to
                                                   @ 1 enables an interrupt-driven application to avoid returning to an empty main application.
                                                   @ 0: Do not sleep when returning to Thread mode.
                                                   @ 1: Enter sleep, or deep sleep, on return to Thread mode from an interrupt service routine.
@.END

@.ITEM     SCB_CCR
.EQU  SCB_CCR_STKALIGN, 1 << 9                     @ Bit 9 STKALIGN
                                                   @ Always reads as one, indicates 8-byte stack alignment on exception entry.
                                                   @ On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack
                                                   @ alignment. On return from the exception it uses this stacked bit to restore the correct stack
                                                   @ alignment.
.EQU  SCB_CCR_UNALIGN_TRP, 1 << 3                  @ Bit 3 UNALIGN_ TRP
                                                   @ Always reads as one, indicates that all unaligned accesses generate a HardFault.
@.END

@.ITEM     SCB_SHPR2
.EQU  SCB_SHPR1_PRI_11_N, 24                       @ Bits 31:24 PRI_11[7:0]: Priority of system handler 11, SVCall
@.END

@.ITEM     SCB_SHPR3
.EQU  SCB_SHPR1_PRI_15_N, 24                       @ Bits 31:24 PRI_15[7:0]: Priority of system handler 15, SysTick exception
.EQU  SCB_SHPR1_PRI_14_N, 16                       @ Bits 23:16 PRI_14[7:0]: Priority of system handler 14, PendSV
@.END

