@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                        Базовые константы ADC                     |
@ |                          STM32F401xB/C/D/E                       |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APB2PERIPH_BASE
.equ ADC1_BASE          , APB2PERIPH_BASE + 0x2000
.EQU ADC1               , PERIPH_BASE + ADC1_BASE

@****************************************************************************
@
@ Analog to Digital Converter
@
@****************************************************************************

@.item  ADC1_BASE
.equ ADC_SR             , 0x00 @ ADC status register
.equ ADC_CR1            , 0x04 @ ADC control register 1
.equ ADC_CR2            , 0x08 @ ADC control register 2
.equ ADC_SMPR1          , 0x0C @ ADC sample time register 1
.equ ADC_SMPR2          , 0x10 @ ADC sample time register 2
.equ ADC_JOFR1          , 0x14 @ ADC injected channel data offset register 1
.equ ADC_JOFR2          , 0x18 @ ADC injected channel data offset register 2
.equ ADC_JOFR3          , 0x1C @ ADC injected channel data offset register 3
.equ ADC_JOFR4          , 0x20 @ ADC injected channel data offset register 4
.equ ADC_HTR            , 0x24 @ ADC watchdog higher threshold register
.equ ADC_LTR            , 0x28 @ ADC watchdog lower threshold register
.equ ADC_SQR1           , 0x2C @ ADC regular sequence register 1
.equ ADC_SQR2           , 0x30 @ ADC regular sequence register 2
.equ ADC_SQR3           , 0x34 @ ADC regular sequence register 3
.equ ADC_JSQR           , 0x38 @ ADC injected sequence register
.equ ADC_JDR1           , 0x3C @ ADC injected data register 1
.equ ADC_JDR2           , 0x40 @ ADC injected data register 2
.equ ADC_JDR3           , 0x44 @ ADC injected data register 3
.equ ADC_JDR4           , 0x48 @ ADC injected data register 4
.equ ADC_DR             , 0x4C @ ADC regular data register
.equ ADC_CSR            , 0x0300 @ ADC Common status register
.equ ADC_CCR            , 0x0304 @ ADC common control register
.equ ADC_CDR            , 0x0308 @ ADC common regular data register for dual AND triple modes


@******************* Bit definition for ADC_SR register *******************
@.ITEM     ADC_SR
.EQU  ADC_SR_AWD         , 0x01  @ Analog watchdog flag
.EQU  ADC_SR_EOC         , 0x02  @ End of conversion
.EQU  ADC_SR_JEOC        , 0x04  @ Injected channel end of conversion
.EQU  ADC_SR_JSTRT       , 0x08  @ Injected channel Start flag
.EQU  ADC_SR_STRT        , 0x10  @ Regular channel Start flag
.EQU  ADC_SR_OVR         , 0x20  @ Overrun flag
@.END

@****************** Bit definition for ADC_CR1 register *******************
@.ITEM     ADC_CR1
.EQU  ADC_CR1_AWDCH_N    , 0           @ Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
                                       @ These bits are set and cleared by software. They select the input channel to be guarded by
                                       @ the analog watchdog.
                                 @ Note: 00000: ADC analog input Channel 0
                                       @ 00001: ADC analog input Channel 1
                                       @ ...
                                       @ 01111: ADC analog input Channel 15
                                       @ 10000: ADC analog input Channel 16
                                       @ 10001: ADC analog input Channel 17
                                       @ 10010: ADC analog input Channel 18
                                       @ Other values reserved
.EQU  ADC_CR1_EOCIE      , 1<<5        @ Bit 5 EOCIE: Interrupt enable for EOC
                                       @ This bit is set and cleared by software to enable/disable the end of conversion interrupt.
                                       @ 0: EOC interrupt disabled
                                       @ 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
.EQU  ADC_CR1_AWDIE      , 1<<6        @ Bit 6 AWDIE: Analog watchdog interrupt enable
                                       @ This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
                                       @ 0: Analog watchdog interrupt disabled
                                       @ 1: Analog watchdog interrupt enabled
.EQU  ADC_CR1_JEOCIE     , 1<<7        @ Bit 7 JEOCIE: Interrupt enable for injected channels
                                       @ This bit is set and cleared by software to enable/disable the end of conversion interrupt for
                                       @ injected channels.
                                       @ 0: JEOC interrupt disabled
                                       @ 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
.EQU  ADC_CR1_SCAN       , 1<<8        @ Bit 8 SCAN: Scan mode
                                       @ This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the
                                       @ inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
                                       @ 0: Scan mode disabled
                                       @ 1: Scan mode enabled
                                 @ Note: An EOC interrupt is generated if the EOCIE bit is set:
                                       @ – At the end of each regular group sequence if the EOCS bit is cleared to 0
                                       @ – At the end of each regular channel conversion if the EOCS bit is set to 1
                                 @ Note: A JEOC interrupt is generated only on the end of conversion of the last channel if the
                                       @ JEOCIE bit is set.
.EQU  ADC_CR1_AWDSGL     , 1<<9        @ Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
                                       @ This bit is set and cleared by software to enable/disable the analog watchdog on the channel
                                       @ identified by the AWDCH[4:0] bits.
                                       @ 0: Analog watchdog enabled on all channels
                                       @ 1: Analog watchdog enabled on a single channel
.EQU  ADC_CR1_JAUTO      , 1<<10       @ Bit 10 JAUTO: Automatic injected group conversion
                                       @ This bit is set and cleared by software to enable/disable automatic injected group conversion
                                       @ after regular group conversion.
                                       @ 0: Automatic injected group conversion disabled
                                       @ 1: Automatic injected group conversion enabled
.EQU  ADC_CR1_DISCEN     , 1<<11       @ Bit 11 DISCEN: Discontinuous mode on regular channels
                                       @ This bit is set and cleared by software to enable/disable Discontinuous mode on regular
                                       @ channels.
                                       @ 0: Discontinuous mode on regular channels disabled
                                       @ 1: Discontinuous mode on regular channels enabled
.EQU  ADC_CR1_JDISCEN    , 1<<12       @ Bit 12 JDISCEN: Discontinuous mode on injected channels
                                       @ This bit is set and cleared by software to enable/disable discontinuous mode on the injected
                                       @ channels of a group.
                                       @ 0: Discontinuous mode on injected channels disabled
                                       @ 1: Discontinuous mode on injected channels enabled
.EQU  ADC_CR1_DISCNUM_N  , 13          @ 15:13  DISCNUM[2:0]: Discontinuous mode channel count
                                       @ These bits are written by software to define the number of regular channels to be converted
                                       @ in discontinuous mode, after receiving an external trigger.
.EQU  ADC_CR1_DISCNUM_1  , 0           @ 000: 1 channel
.EQU  ADC_CR1_DISCNUM_2  , 1<<13       @ 001: 2 channels
.EQU  ADC_CR1_DISCNUM_3  , 2<<13       @ 002: 3 channels
.EQU  ADC_CR1_DISCNUM_4  , 3<<13       @ 003: 4 channels
.EQU  ADC_CR1_DISCNUM_5  , 4<<13       @ 004: 5 channels
.EQU  ADC_CR1_DISCNUM_6  , 5<<13       @ 005: 6 channels
.EQU  ADC_CR1_DISCNUM_7  , 6<<13       @ 006: 7 channels
.EQU  ADC_CR1_DISCNUM_8  , 7<<13       @ 007: 8 channels
.EQU  ADC_CR1_JAWDEN     , 1<<22       @ Bit 22 JAWDEN: Analog watchdog enable on injected channels
                                       @ This bit is set and cleared by software.
                                       @ 0: Analog watchdog disabled on injected channels
                                       @ 1: Analog watchdog enabled on injected channels
.EQU  ADC_CR1_AWDEN      , 1<<23       @ Bit 23 AWDEN: Analog watchdog enable on regular channels
                                       @ This bit is set and cleared by software.
                                       @ 0: Analog watchdog disabled on regular channels
                                       @ 1: Analog watchdog enabled on regular channels
.EQU  ADC_CR1_RES_N      , 24          @ Bits 25:24 RES[1:0]: Resolution
                                       @ These bits are written by software to select the resolution of the conversion.
.EQU  ADC_CR1_RES_12BIT  , 0           @ 00: 12-bit (15 ADCCLK cycles)
.EQU  ADC_CR1_RES_10BIT  , 1<<24       @ 01: 10-bit (13 ADCCLK cycles)
.EQU  ADC_CR1_RES_8BIT   , 2<<24       @ 10: 8-bit (11 ADCCLK cycles)
.EQU  ADC_CR1_RES_6BIT   , 3<<24       @ 11: 6-bit (9 ADCCLK cycles)
.EQU  ADC_CR1_OVRIE_N    , 26          @ Bit 26 OVRIE: Overrun interrupt enable
                                       @ This bit is set and cleared by software to enable/disable the Overrun interrupt.
.EQU  ADC_CR1_OVRIE_DISABLE, 0         @ 0: Overrun interrupt disabled
.EQU  ADC_CR1_OVRIE_ENABLED, 1<<26     @ 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
@.end

@****************** Bit definition for ADC_CR2 register *******************
@.ITEM     ADC_CR2
.EQU  ADC_CR2_ADON       , 1           @ Bit 0 ADON: A/D Converter ON / OFF
.EQU  ADC_CR2_ADON_N     , 0           @ This bit is set and cleared by software.
                                       @ Note: 0: Disable ADC conversion and go to power down mode
                                       @ 1: Enable ADC
.EQU  ADC_CR2_CONT       , 1<<1        @ Bit 1 CONT: Continuous conversion
                                       @ This bit is set and cleared by software. If it is set, conversion takes place continuously until it
                                       @ is cleared.
                                       @ 0: Single conversion mode
                                       @ 1: Continuous conversion mode
.EQU  ADC_CR2_DMA        , 1<<8        @ Bit 8  DMA: Direct memory access mode (for single ADC mode)
                                       @ This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
                                       @ 0: DMA mode disabled
                                       @ 1: DMA mode enabled
.EQU  ADC_CR2_DDS        , 1<<9        @ Bit 9  DDS: DMA disable selection (for single ADC mode)
                                       @ This bit is set and cleared by software.
                                       @ 0: No new DMA request is issued after the last transfer (as configured in the DMA controller)
                                       @ 1: DMA requests are issued as long as data are converted and DMA=1
.EQU  ADC_CR2_EOCS       , 1<<10       @ Bit 10  EOCS: End of conversion selection
                                       @ This bit is set and cleared by software.
                                       @ 0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
                                       @ is enabled only if DMA=1.
                                       @ 1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
.EQU  ADC_CR2_ALIGN      , 1<<11       @ Bit 11 ALIGN: Data alignment
                                       @ This bit is set and cleared by software. Refer to Figure 35 and Figure 36.
                                       @ 0: Right alignment
                                       @ 1: Left alignment
.EQU  ADC_CR2_JEXTSEL_N  , 16          @ Bits 19:16 JEXTSEL[3:0]: External event select for injected group
                                       @ These bits select the external event used to trigger the start of conversion of an injected
                                       @ group.
.EQU  ADC_CR2_JEXTSEL_T1CC4, 0         @ 0000: Timer 1 CC4 event
.EQU  ADC_CR2_JEXTSEL_T1TRGO, 1<<16    @ 0001: Timer 1 TRGO event
.EQU  ADC_CR2_JEXTSEL_T2CC1 , 2<<16    @ 0010: Timer 2 CC1 event
.EQU  ADC_CR2_JEXTSEL_T2TRGO, 3<<16    @ 0011: Timer 2 TRGO event
.EQU  ADC_CR2_JEXTSEL_T3CC2 , 4<<16    @ 0100: Timer 3 CC2 event
.EQU  ADC_CR2_JEXTSEL_T3CC4 , 5<<16    @ 0101: Timer 3 CC4 event
.EQU  ADC_CR2_JEXTSEL_T4CC1 , 6<<16    @ 0110: Timer 4 CC1 event
.EQU  ADC_CR2_JEXTSEL_T4CC2 , 7<<16    @ 0111: Timer 4 CC2 event
.EQU  ADC_CR2_JEXTSEL_T4CC3 , 8<<16    @ 1000: Timer 4 CC3 event
.EQU  ADC_CR2_JEXTSEL_T4TRGO, 9<<16    @ 1001: Timer 4 TRGO event
.EQU  ADC_CR2_JEXTSEL_T5CC4 , 10<<16   @ 1010: Timer 5 CC4 event
.EQU  ADC_CR2_JEXTSEL_T5TRGO, 11<<16   @ 1011: Timer 5 TRGO event
.EQU  ADC_CR2_JEXTSEL_RES_12, 12<<16   @ 1100: Reserved
.EQU  ADC_CR2_JEXTSEL_RES_13, 13<<16   @ 1101: Reserved
.EQU  ADC_CR2_JEXTSEL_RES_14, 14<<16   @ 1110: Reserved
.EQU  ADC_CR2_JEXTSEL_EXTI15, 15<<16   @ 1111: EXTI line15
.EQU  ADC_CR2_JEXTEN_20  , 20          @ Bits 21:20 JEXTEN: External trigger enable for injected channels
                                       @ These bits are set and cleared by software to select the external trigger polarity and enable
                                       @ the trigger of an injected group.
.EQU  ADC_CR2_JEXTEN_DIS   ,  0        @ 00: Trigger detection disabled
.EQU  ADC_CR2_JEXTEN_RISING,  1<<20    @ 01: Trigger detection on the rising edge
.EQU  ADC_CR2_JEXTEN_FALLING, 2<<20    @ 10: Trigger detection on the falling edge
.EQU  ADC_CR2_JEXTEN_BOTH  ,  3<<20    @ 11: Trigger detection on both the rising and falling edges
.EQU  ADC_CR2_JSWSTART   , 1<<22       @ Bit 22 JSWSTART: Start conversion of injected channels
                                       @ This bit is set by software and cleared by hardware as soon as the conversion starts.
                                       @ 0: Reset state
                                       @ 1: Starts conversion of injected channels
                                 @ Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
.EQU  ADC_CR2_EXTSEL_N   , 24          @ Bits 27:24 EXTSEL[3:0]: External event select for regular group
                                       @ These bits select the external event used to trigger the start of conversion of a regular group:
.EQU  ADC_CR2_EXTSEL_T1CC1 , 0         @ 0000: Timer 1 CC1 event
.EQU  ADC_CR2_EXTSEL_T1CC2 , 1<<24     @ 0001: Timer 1 CC2 event
.EQU  ADC_CR2_EXTSEL_T1CC3 , 2<<24     @ 0010: Timer 1 CC3 event
.EQU  ADC_CR2_EXTSEL_T2CC2 , 3<<24     @ 0011: Timer 2 CC2 event
.EQU  ADC_CR2_EXTSEL_T2CC3 , 4<<24     @ 0100: Timer 2 CC3 event
.EQU  ADC_CR2_EXTSEL_T2CC4 , 5<<24     @ 0101: Timer 2 CC4 event
.EQU  ADC_CR2_EXTSEL_T2TRGO, 6<<24     @ 0110: Timer 2 TRGO event
.EQU  ADC_CR2_EXTSEL_T3CC1 , 7<<24     @ 0111: Timer 3 CC1 event
.EQU  ADC_CR2_EXTSEL_T3TRGO, 8<<24     @ 1000: Timer 3 TRGO event
.EQU  ADC_CR2_EXTSEL_T4CC4 , 9<<24     @ 1001: Timer 4 CC4 event
.EQU  ADC_CR2_EXTSEL_T5CC1 , 10<<24    @ 1010: Timer 5 CC1 event
.EQU  ADC_CR2_EXTSEL_T5CC2 , 11<<24    @ 1011: Timer 5 CC2 event
.EQU  ADC_CR2_EXTSEL_T5CC3 , 12<<24    @ 1100: Timer 5 CC3 event
.EQU  ADC_CR2_EXTSEL_RES13 , 13<<24    @ 1101: Reserved
.EQU  ADC_CR2_EXTSEL_RES14 , 14<<24    @ 1110: Reserved
.EQU  ADC_CR2_EXTSEL_EXTI11, 15<<24    @ 1111: EXTI line 11
.EQU  ADC_CR2_EXTEN_N    , 28          @ Bits 29:28 EXTEN: External trigger enable for regular channels
                                       @ These bits are set and cleared by software to select the external trigger polarity and enable
                                       @ the trigger of a regular group.
.EQU  ADC_CR2_EXTEN_DIS  , 0           @ 00: Trigger detection disabled
.EQU  ADC_CR2_EXTEN_RISING , 1<<28     @ 01: Trigger detection on the rising edge
.EQU  ADC_CR2_EXTEN_FALLING, 2<<28     @ 10: Trigger detection on the falling edge
.EQU  ADC_CR2_EXTEN_BOTH   , 3<<28     @ 11: Trigger detection on both the rising and falling edges
.EQU  ADC_CR2_SWSTART      , 1<<30     @ Bit 30 SWSTART: Start conversion of regular channels
.EQU  ADC_CR2_SWSTART_N    , 30        @ This bit is set by software to start conversion and cleared by hardware as soon as the
                                       @ conversion starts.
                                       @ 0: Reset state
                                       @ 1: Starts conversion of regular channels
                                 @ Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
@.end

@***************** Bit definition for ADC_SMPR1 register ******************
@.ITEM     ADC_SMPR1
.EQU  ADC_SMPR1_SMP10_N    , 0         @ Bits 2:0   SMP10[2:0]: Channel 10 sampling time selection
                                       @ These bits are written by software to select the sampling time individually for each channel.
                                       @ During sampling cycles, the channel selection bits must remain unchanged.
.EQU  ADC_SMPR1_SMP11_N    , 3         @ Bits 5:3   SMP11[2:0] bits (Channel 11 Sample time selection)
.EQU  ADC_SMPR1_SMP12_N    , 6         @ Bits 8:6   SMP12[2:0] bits (Channel 12 Sample time selection)
.EQU  ADC_SMPR1_SMP13_N    , 9         @ Bits 11:9  SMP13[2:0] bits (Channel 13 Sample time selection)
.EQU  ADC_SMPR1_SMP14_N    , 12        @ Bits 14:12 SMP14[2:0] bits (Channel 14 Sample time selection)
.EQU  ADC_SMPR1_SMP15_N    , 15        @ Bits 17:15 SMP15[2:0] bits (Channel 15 Sample time selection)
.EQU  ADC_SMPR1_SMP16_N    , 18        @ Bits 20:18 SMP16[2:0] bits (Channel 16 Sample time selection)
.EQU  ADC_SMPR1_SMP17_N    , 21        @ Bits 23:21 SMP17[2:0] bits (Channel 17 Sample time selection)
.EQU  ADC_SMPR1_SMP18_N    , 24        @ Bits 26:24 SMP18[2:0] bits (Channel 18 Sample time selection)
                                     @
                                     @ значение времени преобразования без сдвига !!!
                                     @ применение в виде:  ADC_SMPR1_SMPx_15C<<ADC_SMPR1_SMP14_N
                                     @ для 14го преобразования 15 циклов преобразования
.EQU  ADC_SMPR1_SMPx_3C  , 0         @ 000: 3 cycles
.EQU  ADC_SMPR1_SMPx_15C , 1         @ 001: 15 cycles
.EQU  ADC_SMPR1_SMPx_28C , 2         @ 010: 28 cycles
.EQU  ADC_SMPR1_SMPx_56C , 3         @ 011: 56 cycles
.EQU  ADC_SMPR1_SMPx_84C , 4         @ 100: 84 cycles
.EQU  ADC_SMPR1_SMPx_112C, 5         @ 101: 112 cycles
.EQU  ADC_SMPR1_SMPx_144C, 6         @ 110: 144 cycles
.EQU  ADC_SMPR1_SMPx_480C, 7         @ 111: 480 cycles
@.end

@***************** Bit definition for ADC_SMPR2 register ******************
@.ITEM     ADC_SMPR2
.EQU  ADC_SMPR2_SMP0_N     , 0       @ Bits 2:0   SMP0[2:0]: Channel 0 sampling time selection
                                     @ These bits are written by software to select the sampling time individually for each channel.
                                     @ During sample cycles, the channel selection bits must remain unchanged.
.EQU  ADC_SMPR2_SMP1_N     , 3       @ Bits 5:3   SMP1[2:0] bits (Channel 1 Sample time selection)
.EQU  ADC_SMPR2_SMP2_N     , 6       @ Bits 8:6   SMP2[2:0] bits (Channel 2 Sample time selection)
.EQU  ADC_SMPR2_SMP3_N     , 9       @ Bits 11:9  SMP3[2:0] bits (Channel 3 Sample time selection)
.EQU  ADC_SMPR2_SMP4_N     , 12      @ Bits 14:12 SMP4[2:0] bits (Channel 4 Sample time selection)
.EQU  ADC_SMPR2_SMP5_N     , 15      @ Bits 17:15 SMP5[2:0] bits (Channel 5 Sample time selection)
.EQU  ADC_SMPR2_SMP6_N     , 18      @ Bits 20:18 SMP6[2:0] bits (Channel 6 Sample time selection)
.EQU  ADC_SMPR2_SMP7_N     , 21      @ Bits 23:21 SMP7[2:0] bits (Channel 7 Sample time selection)
.EQU  ADC_SMPR2_SMP8_N     , 24      @ Bits 26:24 SMP8[2:0] bits (Channel 8 Sample time selection)
.EQU  ADC_SMPR2_SMP9_N     , 27      @ Bits 29:27 SMP9[2:0] bits (Channel 9 Sample time selection)
                                     @
                                     @ значение времени преобразования без сдвига !!!
                                     @ применение в виде:  ADC_SMPR2_SMPx_3C<<ADC_SMPR1_SMP1_N
                                     @ для 1-го преобразования 3 цикла преобразования
.EQU  ADC_SMPR2_SMPx_3C  , 0         @ 000: 3 cycles
.EQU  ADC_SMPR2_SMPx_15C , 1         @ 001: 15 cycles
.EQU  ADC_SMPR2_SMPx_28C , 2         @ 010: 28 cycles
.EQU  ADC_SMPR2_SMPx_56C , 3         @ 011: 56 cycles
.EQU  ADC_SMPR2_SMPx_84C , 4         @ 100: 84 cycles
.EQU  ADC_SMPR2_SMPx_112C, 5         @ 101: 112 cycles
.EQU  ADC_SMPR2_SMPx_144C, 6         @ 110: 144 cycles
.EQU  ADC_SMPR2_SMPx_480C, 7         @ 111: 480 cycles
@.end

@***************** Bit definition for ADC_JOFR1 register ******************
@.ITEM     ADC_JOFR1
.EQU  ADC_JOFR1_JOFFSET1 , 0x0FFF        @Data offset for injected channel 1
@.end

@***************** Bit definition for ADC_JOFR2 register ******************
@.ITEM     ADC_JOFR2
.EQU  ADC_JOFR2_JOFFSET2 , 0x0FFF        @Data offset for injected channel 2
@.end

@***************** Bit definition for ADC_JOFR3 register ******************
@.ITEM     ADC_JOFR3
.EQU  ADC_JOFR3_JOFFSET3 , 0x0FFF        @Data offset for injected channel 3
@.end

@***************** Bit definition for ADC_JOFR4 register ******************
@.ITEM     ADC_JOFR4
.EQU  ADC_JOFR4_JOFFSET4 , 0x0FFF        @Data offset for injected channel 4
@.end

@****************** Bit definition for ADC_HTR register *******************
@.ITEM     ADC_HTR
.EQU  ADC_HTR_HT         , 0x0FFF        @Analog watchdog high threshold
@.end

@****************** Bit definition for ADC_LTR register *******************
@.ITEM     ADC_LTR
.EQU  ADC_LTR_LT         , 0x0FFF        @Analog watchdog low threshold
@.end

@****************** Bit definition for ADC_SQR1 register ******************
@.ITEM     ADC_SQR1
.EQU  ADC_SQR1_SQ13_N    , 0             @ Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
.EQU  ADC_SQR1_SQ14_N    , 5             @ Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
.EQU  ADC_SQR1_SQ15_N    , 10            @ Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
.EQU  ADC_SQR1_SQ16_N    , 15            @ Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 16th in
                                         @ the conversion sequence.
.EQU  ADC_SQR1_L         , 20            @ Bits 23:20 L[3:0]: Regular channel sequence length
                                         @ These bits are written by software to define the total number of conversions in the regular
                                         @ channel conversion sequence.
                                         @ 0000: 1 conversion
                                         @ 0001: 2 conversions
                                         @ ...
                                         @ 1111: 16 conversions
@.end

@****************** Bit definition for ADC_SQR2 register ******************
@.ITEM     ADC_SQR2
.EQU  ADC_SQR2_SQ7_N     , 0             @ Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
.EQU  ADC_SQR2_SQ8_N     , 5             @ Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
.EQU  ADC_SQR2_SQ9_N     , 10            @ Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
.EQU  ADC_SQR2_SQ10_N    , 15            @ Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
.EQU  ADC_SQR2_SQ11_N    , 20            @ Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
.EQU  ADC_SQR2_SQ12_N    , 25            @ Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 12th in
                                         @ the sequence to be converted.
@.end

@****************** Bit definition for ADC_SQR3 register ******************
@.ITEM     ADC_SQR3
.EQU  ADC_SQR3_SQ1_N     , 0             @ Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
.EQU  ADC_SQR3_SQ2_N     , 5             @ Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
.EQU  ADC_SQR3_SQ3_N     , 10            @ Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
.EQU  ADC_SQR3_SQ4_N     , 15            @ Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
.EQU  ADC_SQR3_SQ5_N     , 20            @ Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
.EQU  ADC_SQR3_SQ6_N     , 25            @ Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
                                         @ These bits are written by software with the channel number (0..18) assigned as the 6th in the
                                         @ sequence to be converted.
@.end

@****************** Bit definition for ADC_JSQR register ******************
@.ITEM     ADC_JSQR
.EQU  ADC_JSQR_JSQ1      , 0x0000001F    @JSQ1[4:0] bits (1st conversion in injected sequence)
.EQU  ADC_JSQR_JSQ1_0    , 0x00000001    @Bit 0
.EQU  ADC_JSQR_JSQ1_1    , 0x00000002    @Bit 1
.EQU  ADC_JSQR_JSQ1_2    , 0x00000004    @Bit 2
.EQU  ADC_JSQR_JSQ1_3    , 0x00000008    @Bit 3
.EQU  ADC_JSQR_JSQ1_4    , 0x00000010    @Bit 4
.EQU  ADC_JSQR_JSQ2      , 0x000003E0    @JSQ2[4:0] bits (2nd conversion in injected sequence)
.EQU  ADC_JSQR_JSQ2_0    , 0x00000020    @Bit 0
.EQU  ADC_JSQR_JSQ2_1    , 0x00000040    @Bit 1
.EQU  ADC_JSQR_JSQ2_2    , 0x00000080    @Bit 2
.EQU  ADC_JSQR_JSQ2_3    , 0x00000100    @Bit 3
.EQU  ADC_JSQR_JSQ2_4    , 0x00000200    @Bit 4
.EQU  ADC_JSQR_JSQ3      , 0x00007C00    @JSQ3[4:0] bits (3rd conversion in injected sequence)
.EQU  ADC_JSQR_JSQ3_0    , 0x00000400    @Bit 0
.EQU  ADC_JSQR_JSQ3_1    , 0x00000800    @Bit 1
.EQU  ADC_JSQR_JSQ3_2    , 0x00001000    @Bit 2
.EQU  ADC_JSQR_JSQ3_3    , 0x00002000    @Bit 3
.EQU  ADC_JSQR_JSQ3_4    , 0x00004000    @Bit 4
.EQU  ADC_JSQR_JSQ4      , 0x000F8000    @JSQ4[4:0] bits (4th conversion in injected sequence)
.EQU  ADC_JSQR_JSQ4_0    , 0x00008000    @Bit 0
.EQU  ADC_JSQR_JSQ4_1    , 0x00010000    @Bit 1
.EQU  ADC_JSQR_JSQ4_2    , 0x00020000    @Bit 2
.EQU  ADC_JSQR_JSQ4_3    , 0x00040000    @Bit 3
.EQU  ADC_JSQR_JSQ4_4    , 0x00080000    @Bit 4
.EQU  ADC_JSQR_JL        , 0x00300000    @JL[1:0] bits (Injected Sequence length)
.EQU  ADC_JSQR_JL_0      , 0x00100000    @Bit 0
.EQU  ADC_JSQR_JL_1      , 0x00200000    @Bit 1
@.end

@****************** Bit definition for ADC_JDR1 register ******************
@.ITEM     ADC_JDR1
.EQU  ADC_JDR1_JDATA     , 0xFFFF        @Injected data
@.end

@****************** Bit definition for ADC_JDR2 register ******************
@.ITEM     ADC_JDR2
.EQU  ADC_JDR2_JDATA     , 0xFFFF        @Injected data
@.end

@****************** Bit definition for ADC_JDR3 register ******************
@.ITEM     ADC_JDR3
.EQU  ADC_JDR3_JDATA     , 0xFFFF        @Injected data
@.end

@****************** Bit definition for ADC_JDR4 register ******************
@.ITEM     ADC_JDR4
.EQU  ADC_JDR4_JDATA     , 0xFFFF        @Injected data
@.end

@******************* Bit definition for ADC_DR register *******************
@.ITEM     ADC_DR
.EQU  ADC_DR_DATA        , 0x0000FFFF    @Regular data
.EQU  ADC_DR_ADC2DATA    , 0xFFFF0000    @ADC2 data
@.end

@****************** Bit definition for ADC_CSR register *******************
@.ITEM     ADC_CSR
.EQU  ADC_CSR_AWD1       , 0x00000001    @ADC1 Analog watchdog flag
.EQU  ADC_CSR_EOC1       , 0x00000002    @ADC1 End of conversion
.EQU  ADC_CSR_JEOC1      , 0x00000004    @ADC1 Injected channel end of conversion
.EQU  ADC_CSR_JSTRT1     , 0x00000008    @ADC1 Injected channel Start flag
.EQU  ADC_CSR_STRT1      , 0x00000010    @ADC1 Regular channel Start flag
.EQU  ADC_CSR_DOVR1      , 0x00000020    @ADC1 DMA overrun flag
.EQU  ADC_CSR_AWD2       , 0x00000100    @ADC2 Analog watchdog flag
.EQU  ADC_CSR_EOC2       , 0x00000200    @ADC2 End of conversion
.EQU  ADC_CSR_JEOC2      , 0x00000400    @ADC2 Injected channel end of conversion
.EQU  ADC_CSR_JSTRT2     , 0x00000800    @ADC2 Injected channel Start flag
.EQU  ADC_CSR_STRT2      , 0x00001000    @ADC2 Regular channel Start flag
.EQU  ADC_CSR_DOVR2      , 0x00002000    @ADC2 DMA overrun flag
.EQU  ADC_CSR_AWD3       , 0x00010000    @ADC3 Analog watchdog flag
.EQU  ADC_CSR_EOC3       , 0x00020000    @ADC3 End of conversion
.EQU  ADC_CSR_JEOC3      , 0x00040000    @ADC3 Injected channel end of conversion
.EQU  ADC_CSR_JSTRT3     , 0x00080000    @ADC3 Injected channel Start flag
.EQU  ADC_CSR_STRT3      , 0x00100000    @ADC3 Regular channel Start flag
.EQU  ADC_CSR_DOVR3      , 0x00200000    @ADC3 DMA overrun flag
@.end

@****************** Bit definition for ADC_CCR register *******************
@.ITEM     ADC_CCR
.EQU  ADC_CCR_MULTI      , 0x0000001F    @MULTI[4:0] bits (Multi-ADC mode selection)
.EQU  ADC_CCR_MULTI_0    , 0x00000001    @Bit 0
.EQU  ADC_CCR_MULTI_1    , 0x00000002    @Bit 1
.EQU  ADC_CCR_MULTI_2    , 0x00000004    @Bit 2
.EQU  ADC_CCR_MULTI_3    , 0x00000008    @Bit 3
.EQU  ADC_CCR_MULTI_4    , 0x00000010    @Bit 4
.EQU  ADC_CCR_DELAY      , 0x00000F00    @DELAY[3:0] bits (Delay between 2 sampling phases)
.EQU  ADC_CCR_DELAY_0    , 0x00000100    @Bit 0
.EQU  ADC_CCR_DELAY_1    , 0x00000200    @Bit 1
.EQU  ADC_CCR_DELAY_2    , 0x00000400    @Bit 2
.EQU  ADC_CCR_DELAY_3    , 0x00000800    @Bit 3
.EQU  ADC_CCR_DDS        , 0x00002000    @DMA disable selection (Multi-ADC mode)
.EQU  ADC_CCR_DMA        , 0x0000C000    @DMA[1:0] bits (Direct Memory Access mode for multimode)
.EQU  ADC_CCR_DMA_0      , 0x00004000    @Bit 0
.EQU  ADC_CCR_DMA_1      , 0x00008000    @Bit 1
.EQU  ADC_CCR_ADCPRE     , 0x00030000    @ADCPRE[1:0] bits (ADC prescaler)
.EQU  ADC_CCR_ADCPRE_N   , 16            @ Bits 17:16  ADCPRE: ADC prescaler
                                         @ Set and cleared by software to select the frequency of the clock to the ADC. .
.EQU  ADC_CCR_ADCPRE_DIV2, 0             @  00: PCLK2 divided by 2
.EQU  ADC_CCR_ADCPRE_DIV4, 1<<16         @  01: PCLK2 divided by 4
.EQU  ADC_CCR_ADCPRE_DIV6, 2<<16         @  10: PCLK2 divided by 6
.EQU  ADC_CCR_ADCPRE_DIV8, 3<<16         @  11: PCLK2 divided by 8
.EQU  ADC_CCR_ADCPRE_0   , 0x00010000    @Bit 0
.EQU  ADC_CCR_ADCPRE_1   , 0x00020000    @Bit 1
.EQU  ADC_CCR_VBATE      , 0x00400000    @VBAT Enable
.EQU  ADC_CCR_TSVREFE    , 0x00800000    @Temperature Sensor and VREFINT Enable
@.end

@****************** Bit definition for ADC_CDR register *******************
@.ITEM     ADC_CDR
.EQU  ADC_CDR_DATA1      , 0x0000FFFF    @1st data of a pair of regular conversions
.EQU  ADC_CDR_DATA2      , 0xFFFF0000    @2nd data of a pair of regular conversions
@.end

