@.CHARSET CP1251

@.ITEM     SPI1  SPI2   SPI1_BASE   SPI2_BASE
.EQU  SPI_CR1      ,  0x00   @ SPI control register 1 (SPIx_CR1)
.EQU  SPI_CR2      ,  0x04   @ SPI control register 2 (SPIx_CR2)
.EQU  SPI_SR       ,  0x08   @ SPI status register (SPIx_SR)
.EQU  SPI_DR       ,  0x0C   @ SPI data register (SPIx_DR)
.EQU  SPI_CRCPR    ,  0x10   @ SPI CRC polynomial register (SPIx_CRCPR)
.EQU  SPI_RXCRCR   ,  0x14   @ SPI Rx CRC register (SPIx_RXCRCR)
.EQU  SPI_TXCRCR   ,  0x18   @ SPI Tx CRC register (SPIx_TXCRCR)
@.END

@ Описание битов настройки  SPI control register 1 (SPIx_CR1)
@.ITEM SPI_CR1
.EQU  SPI_CR1_RST_VAL, 0x0000    @ Reset value: 0x0000
.EQU  SPI_CR1_CPHA , 1           @ Bit 0 CPHA: Clock phase
                              @ 0: The first clock transition is the first data capture edge
                              @ 1: The second clock transition is the first data capture edge
                              @ Note: This bit should not be changed when communication is ongoing.
                              @ This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
.EQU  SPI_CR1_CPOL , 1 << 1   @ Bit1 CPOL: Clock polarity
                              @ 0: CK to 0 when idle
                              @ 1: CK to 1 when idle
                              @ Note: This bit should not be changed when communication is ongoing.
                              @ This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
.EQU  SPI_CR1_MSTR , 1 << 2    @ Bit 2 MSTR: Master selection
                               @ 0: Slave configuration
                               @ 1: Master configuration
                               @ Note: This bit should not be changed when communication is ongoing.
.EQU  SPI_CR1_BR_N , 3       @ Bits 5:3 BR[2:0]: Baud rate control
.EQU  SPI_CR1_BR_fPCLK_2, 0 << 3    @ 000: fPCLK/2
.EQU  SPI_CR1_BR_fPCLK_4, 1 << 3    @ 001: fPCLK/4
.EQU  SPI_CR1_BR_fPCLK_8, 2 << 3    @ 010: fPCLK/8
.EQU  SPI_CR1_BR_fPCLK_16, 3 << 3    @ 011: fPCLK/16
.EQU  SPI_CR1_BR_fPCLK_32, 4 << 3    @ 100: fPCLK/32
.EQU  SPI_CR1_BR_fPCLK_64, 5 << 3    @ 101: fPCLK/64
.EQU  SPI_CR1_BR_fPCLK_128, 6 << 3    @ 110: fPCLK/128
.EQU  SPI_CR1_BR_fPCLK_256, 7 << 3    @ 111: fPCLK/256
@ Note: These bits should not be changed when communication is ongoing.
.EQU  SPI_CR1_SPE  , 1 << 6    @ Bit 6 SPE: SPI enable
                               @ 0: Peripheral disabled
                               @ 1: Peripheral enabled
                               @ Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 653.
.EQU  SPI_CR1_LSBFIRST, 1 << 7    @ Bit 7 LSBFIRST: Frame format
                                  @ 0: data is transmitted / received with the MSB first
                                  @ 1: data is transmitted / received with the LSB first
                                  @ Note: 1. This bit should not be changed when communication is ongoing.
                                  @ 2. This bit is not used in SPI TI mode.
.EQU  SPI_CR1_SSI  , 1 << 8    @ Bit 8 SSI: Internal slave select
                               @ This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS
                               @ pin and the I/O value of the NSS pin is ignored.
                               @ Note: This bit is not used in SPI TI mode.
.EQU  SPI_CR1_SSM  , 1 << 9    @ Bit 9 SSM: Software slave management
                               @ When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
                               @ 0: Software slave management disabled
                               @ 1: Software slave management enabled
                               @ Note: This bit is not used in SPI TI mode.
.EQU  SPI_CR1_RXONLY  , 1 << 10    @ Bit 10 RXONLY: Receive only mode enabled.
                               @ This bit enables simplex communication using a single unidirectional line to receive data
                               @ exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful
                               @ in a multislave system in which this particular slave is not accessed, the output from the
                               @ accessed slave is not corrupted.
                               @ 0: Full-duplex (Transmit and receive)
                               @ 1: Output disabled (Receive-only mode)
.EQU  SPI_CR1_CRCL  , 1 << 11    @ Bit 11 CRCL: CRC length
                               @ This bit is set and cleared by software to select the CRC length.
                               @ 0: 8-bit CRC length
                               @ 1: 16-bit CRC length
                               @ Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
.EQU  SPI_CR1_CRCNEXT  , 1 << 12    @ Bit 12 CRCNEXT: Transmit CRC next
                               @ 0: Next transmit value is from Tx buffer
                               @ 1: Next transmit value is from Tx CRC register
                               @ Note: This bit has to be written as soon as the last data is written in the SPIx_DR register.
.EQU  SPI_CR1_CRCEN  , 1 << 13    @ Bit 13 CRCEN: Hardware CRC calculation enable
                               @ 0: CRC calculation disabled
                               @ 1: CRC calculation Enabled
                               @ Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
.EQU  SPI_CR1_BIDIOE  , 1 << 14    @ Bit 14 BIDIOE: Output enable in bidirectional mode
                               @ This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode
                               @ 0: Output disabled (receive-only mode)
                               @ 1: Output enabled (transmit-only mode)
                               @ Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.
.EQU  SPI_CR1_BIDIMODE , 1 << 15    @ Bit 15 BIDIMODE: Bidirectional data mode enable. This bit enables half-duplex communication using
                               @ common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active.
                               @ 0: 2-line unidirectional data mode selected
                               @ 1: 1-line bidirectional data mode selected
@.END

@ Описание битов настройки  SPI control register 2 (SPIx_CR2)
@.ITEM SPI_CR2
.EQU  SPI_CR2_RST_VAL, 0x0700    @ Reset value: 0x0700
.EQU  SPI_CR2_RXDMAEN, 1     @ Bit 0 RXDMAEN: Rx buffer DMA enable
                             @ When this bit is set, a DMA request is generated whenever the RXNE flag is set.
                             @ 0: Rx buffer DMA disabled
                             @ 1: Rx buffer DMA enabled
.EQU  SPI_CR2_XDMAEN, 1 << 1    @ Bit 1 TXDMAEN: Tx buffer DMA enable
                             @ When this bit is set, a DMA request is generated whenever the TXE flag is set.
                             @ 0: Tx buffer DMA disabled
                             @ 1: Tx buffer DMA enabled
.EQU  SPI_CR2_SSOE, 1 << 2    @ Bit 2 SSOE: SS output enable
                             @ 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration
                             @ 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI
                             @ interface cannot work in a multimaster environment.
                             @ Note: This bit is not used in SPI TI mode.
.EQU  SPI_CR2_NSSP, 1 << 3    @ Bit 3 NSSP: NSS pulse management
                             @ This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two
                             @ consecutive data when doing continuous transfers. In the case of a single data transfer, it
                             @ forces the NSS pin high level after the transfer.
                             @ It has no meaning if CPHA = 1, or FRF = 1.
                             @ 0: No NSS pulse
                             @ 1: NSS pulse generated
                             @ Note: 1. This bit must be written only when the SPI is disabled (SPE=0).
                             @ 2. This bit is not used in SPI TI mode.
.EQU  SPI_CR2_FRF, 1 << 4    @  Bit 4 FRF: Frame format
                             @ 0: SPI Motorola mode
                             @ 1 SPI TI mode
                             @ Note: This bit must be written only when the SPI is disabled (SPE=0).
.EQU  SPI_CR2_ERRIE, 1 << 5    @ Bit 5 ERRIE: Error interrupt enable
                             @ This bit controls the generation of an interrupt when an error condition occurs (CRCERR,
                             @ OVR, MODF in SPI mode, FRE at TI mode).
                             @ 0: Error interrupt is masked
                             @ 1: Error interrupt is enabled
.EQU  SPI_CR2_RXNEIE, 1 << 6    @ Bit 6 RXNEIE: RX buffer not empty interrupt enable
                             @ 0: RXNE interrupt masked
                             @ 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.
.EQU  SPI_CR2_TXEIE, 1 << 7    @  Bit 7 TXEIE: Tx buffer empty interrupt enable
                             @ 0: TXE interrupt masked
                             @ 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
.EQU  SPI_CR2_DS_N , 8       @ Bits 11:8 DS [3:0]: Data size
                             @ These bits configure the data length for SPI transfers:
.EQU  SPI_CR2_DS_4 , 3 << 8     @ 0011: 4-bit
.EQU  SPI_CR2_DS_5 , 4 << 8     @ 0100: 5-bit
.EQU  SPI_CR2_DS_6 , 5 << 8     @ 0101: 6-bit
.EQU  SPI_CR2_DS_7 , 6 << 8     @ 0110: 7-bit
.EQU  SPI_CR2_DS_8 , 7 << 8     @ 0111: 8-bit
.EQU  SPI_CR2_DS_9 , 8 << 8     @ 1000: 9-bit
.EQU  SPI_CR2_DS_10, 9 << 8     @ 1001: 10-bit
.EQU  SPI_CR2_DS_11, 10 << 8    @ 1010: 11-bit
.EQU  SPI_CR2_DS_12, 11 << 8    @ 1011: 12-bit
.EQU  SPI_CR2_DS_13, 12 << 8    @ 1100: 13-bit
.EQU  SPI_CR2_DS_14, 13 << 8    @ 1101: 14-bit
.EQU  SPI_CR2_DS_15, 14 << 8    @ 1110: 15-bit
.EQU  SPI_CR2_DS_16, 15 << 8    @ 1111: 16-bit
                                 @ 0000: Not used
                                 @ 0001: Not used
                                 @ 0010: Not used
.EQU  SPI_CR2_FRXTH, 1 << 12    @ Bit 12 FRXTH: FIFO reception threshold
                                @ This bit is used to set the threshold of the RXFIFO that triggers an RXNE event
                                @ 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
                                @ 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
.EQU  SPI_CR2_LDMA_RX, 1 << 13    @ Bit 13 LDMA_RX: Last DMA transfer for reception
                                @ This bit is used in data packing mode, to define if the total number of data to receive by DMA is
                                @ odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if
                                @ packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It has
                                @ to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
                                @ 0: Number of data to transfer is even
                                @ 1: Number of data to transfer is odd
                                @ Note: Refer to Procedure for disabling the SPI on page 653 if the CRCEN bit is set.
.EQU  SPI_CR2_LDMA_TX, 1 << 14    @  Bit 14 LDMA_TX: Last DMA transfer for transmission
                                @ This bit is used in data packing mode, to define if the total number of data to transmit by DMA
                                @ is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and
                                @ if packing mode is used (data length =< 8-bit and write access to SPIx_DR is 16-bit wide). It
                                @ has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register).
                                @ 0: Number of data to transfer is even
                                @ 1: Number of data to transfer is odd
                                @ Note: Refer to Procedure for disabling the SPI on page 653 if the CRCEN bit is set.
                                @ Bit 15 Reserved, must be kept at reset value.
@.END

@ Описание битов настройки  SPI status register (SPIx_SR)
@.ITEM  SPI_SR
.EQU  SPI_SR_RST_VAL, 0x0002    @ Reset value: 0x0002
.EQU  SPI_SR_RXNE  , 1          @ Bit 0 RXNE: Receive buffer not empty
                                @ 0: Rx buffer empty
                                @ 1: Rx buffer not empty
.EQU  SPI_SR_TXE   , 1 << 1     @ Bit 1 TXE: Transmit buffer empty
                                @ 0: Tx buffer not empty
                                @ 1: Tx buffer empty
                                @ Bits 3:2 Reserved, must be kept at reset value.
.EQU  SPI_SR_CRCERR   , 1 << 4    @ Bit 4 CRCERR: CRC error flag
                                @ 0: CRC value received matches the SPIx_RXCRCR value
                                @ 1: CRC value received does not match the SPIx_RXCRCR value
                                @ This flag is set by hardware and cleared by software writing 0.
.EQU  SPI_SR_MODF   , 1 << 5    @ Bit 5 MODF: Mode fault
                                @ 0: No mode fault occurred
                                @ 1: Mode fault occurred
                                @ This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault
                                @ (MODF) on page 663 for the software sequence.
.EQU  SPI_SR_OVR   , 1 << 6     @ Bit 6 OVR: Overrun flag
                                @ 0: No overrun occurred
                                @ 1: Overrun occurred
                                @ This flag is set by hardware and reset by a software sequence.
.EQU  SPI_SR_BSY   , 1 << 7     @ Bit 7 BSY: Busy flag
                                @ 0: SPI not busy
                                @ 1: SPI is busy in communication or Tx buffer is not empty
                                @ This flag is set and cleared by hardware.
                                @ Note: The BSY flag must be used with caution: refer to Section 24.4.10: SPI status flags and
                                @ Procedure for disabling the SPI on page 653.
.EQU  SPI_SR_FRE   , 1 << 8     @  Bit 8 FRE: Frame format error
                                @ This flag is used for SPI in TI slave mode. Refer to Section 24.4.11: SPI error flags.
                                @ This flag is set by hardware and reset when SPIx_SR is read by software.
                                @ 0: No frame format error
                                @ 1: A frame format error occurred
.EQU  SPI_SR_FRLVL_N, 9         @  Bits 10:9 FRLVL[1:0]: FIFO reception level
                                @ These bits are set and cleared by hardware.
.EQU  SPI_SR_FRLVL_FIFO_EMPTY, 0 << 9    @ 00: FIFO empty
.EQU  SPI_SR_FRLVL_FIFO_1_4,   1 << 9    @ 01: 1/4 FIFO
.EQU  SPI_SR_FRLVL_FIFO_1_2,   2 << 9    @ 10: 1/2 FIFO
.EQU  SPI_SR_FRLVL_FIFO_FULL,  3 << 9    @ 11: FIFO full
                                @ Note: These bits are not used in SPI receive-only mode while CRC calculation is enabled.
.EQU  SPI_SR_FTLVL_N, 11        @ Bits 12:11 FTLVL[1:0]: FIFO Transmission Level
                                @ These bits are set and cleared by hardware.
.EQU  SPI_SR_FTLVL_FIFO_EMPTY, 0 << 11   @ 00: FIFO empty
.EQU  SPI_SR_FTLVL_FIFO_1_4,   1 << 11   @ 01: 1/4 FIFO
.EQU  SPI_SR_FTLVL_FIFO_1_2,   2 << 11   @ 10: 1/2 FIFO
.EQU  SPI_SR_FTLVL_FIFO_EMPTY, 3 << 11   @ 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2)
                                @ Bits 15:13 Reserved, must be kept at reset value.
@.END

@ Описание битов настройки   SPI data register (SPIx_DR)
@.ITEM  SPI_DR
.EQU  SPI_DR_RST_VAL, 0x0000    @ Reset value: 0x0000
                                @ Bits 15:0 DR[15:0]: Data register
                                @ Data received or to be transmitted
                                @ The data register serves as an interface between the Rx and Tx FIFOs. When the data
                                @ register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
                                @ Section 24.4.9: Data transmission and reception procedures).
                                @ Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
                                @ read as zero when the register is read. The Rx threshold setting must always
                                @ correspond with the read access currently used.
@.END

@ Описание битов настройки SPI CRC polynomial register (SPIx_CRCPR)
@.ITEM  SPI_CRCPR
.EQU  SPI_CRCPR_RST_VAL, 0x0007    @ Reset value: 0x0007
                                @ Bits 15:0 CRCPOLY[15:0]: CRC polynomial register
                                @ This register contains the polynomial for the CRC calculation.
                                @ The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be
                                @ configured as required.
                                @ Note: The polynomial value should be odd only. No even value is supported.
@.END

@ Описание битов настройки SPI Rx CRC register (SPIx_RXCRCR)
@.ITEM  SPI_RXCRCR
.EQU  SPI_RXCRCR_RST_VAL, 0x0000    @ Reset value: 0x0000
                                 @ Bits 15:0 RXCRC[15:0]: Rx CRC register
                                 @ When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of
                                 @ the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1
                                 @ register is written to 1. The CRC is calculated serially using the polynomial programmed in the
                                 @ SPIx_CRCPR register.
                                 @ Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL
                                 @ bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
                                 @ The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
                                 @ (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard.
                                 @ A read to this register when the BSY Flag is set could return an incorrect value.
@.END

@ Описание битов настройки SPI Tx CRC register (SPIx_TXCRCR)
@.ITEM  SPI_TXCRCR
.EQU  SPI_TXCRCR_RST_VAL, 0x0000    @ Reset value: 0x0000
                                  @ Bits 15:0 TxCRC[15:0]: Tx CRC register
                                  @ When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of
                                  @ the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is
                                  @ written to 1. The CRC is calculated serially using the polynomial programmed in the
                                  @ SPIx_CRCPR register.
                                  @ Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length
                                  @ (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
                                  @ The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected
                                  @ (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard.
                                  @ A read to this register when the BSY flag is set could return an incorrect value.
@.END




