@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                       Константы DMA                              |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     AHB1PERIPH_BASE
.EQU  DMA1_BASE     , ( AHB1PERIPH_BASE + 0x00000000 )
.EQU  DMA2_BASE     , ( AHB1PERIPH_BASE + 0x00000400 )
.EQU  DMA1          , PERIPH_BASE + DMA1_BASE
.EQU  DMA2          , PERIPH_BASE + DMA2_BASE
@.END

@.ITEM     DMA1_BASE DMA2_BASE DMA1 DMA2
.EQU  DMA_ISR   , 0x00     @ DMA interrupt status register
.EQU  DMA_IFCR      , 0x04     @ DMA interrupt flag clear regis
.EQU  DMA_CCR1      , 0x08     @ DMA channel 1 configuration register
.EQU  DMA_CNDTR1    , 0x0C     @ DMA channel 1 number of data register
.EQU  DMA_CPAR1     , 0x10     @ DMA channel 1 peripheral address register
.EQU  DMA_CMAR1     , 0x14     @ DMA channel 1 memory address register
.EQU  DMA_CCR2      , 0x1C     @ DMA channel 2 configuration register
.EQU  DMA_CNDTR2    , 0x20     @ DMA channel 2 number of data register
.EQU  DMA_CPAR2     , 0x24     @ DMA channel 2 peripheral address register
.EQU  DMA_CMAR2     , 0x28     @ DMA channel 2 memory address register
.EQU  DMA_CCR3      , 0x30     @ DMA channel 3 configuration register
.EQU  DMA_CNDTR3    , 0x34     @ DMA channel 3 number of data register
.EQU  DMA_CPAR3     , 0x38     @ DMA channel 3 peripheral address register
.EQU  DMA_CMAR3     , 0x3C     @ DMA channel 3 memory address register
.EQU  DMA_CCR4      , 0x44     @ DMA channel 4 configuration register
.EQU  DMA_CNDTR4    , 0x48     @ DMA channel 4 number of data register
.EQU  DMA_CPAR4     , 0x4C     @ DMA channel 4 peripheral address register
.EQU  DMA_CMAR4     , 0x50     @ DMA channel 4 memory address register
.EQU  DMA_CCR5      , 0x58     @ DMA channel 5 configuration register
.EQU  DMA_CNDTR5    , 0x5C     @ DMA channel 5 number of data register
.EQU  DMA_CPAR5     , 0x60     @ DMA channel 5 peripheral address register
.EQU  DMA_CMAR5     , 0x64     @ DMA channel 5 memory address register
.EQU  DMA_CCR6      , 0x6C     @ DMA channel 6 configuration register
.EQU  DMA_CNDTR6    , 0x70     @ DMA channel 6 number of data register
.EQU  DMA_CPAR6     , 0x74     @ DMA channel 6 peripheral address register
.EQU  DMA_CMAR6     , 0x78     @ DMA channel 6 memory address register
.EQU  DMA_CCR7      , 0x80     @ DMA channel 7 configuration register
.EQU  DMA_CNDTR7    , 0x84     @ DMA channel 7 number of data register
.EQU  DMA_CPAR7     , 0x88     @ DMA channel 7 peripheral address register
.EQU  DMA_CMAR7     , 0x8C     @ DMA channel 7 memory address register
@.END

@.ITEM     DMA_ISR
.EQU  DMA_ISR_GIF1_N, 0
.EQU  DMA_ISR_GIF1  , 1 << 0
.EQU  DMA_ISR_TCIF1_N, 1
.EQU  DMA_ISR_TCIF1 , 1 << 1    @Channel 1 Transfer Complete flag
.EQU  DMA_ISR_HTIF1_N, 2
.EQU  DMA_ISR_HTIF1 , 1 << 2    @Channel 1 Half Transfer flag
.EQU  DMA_ISR_TEIF1_N, 3
.EQU  DMA_ISR_TEIF1 , 1 << 3    @ Channel 1 Transfer Error flag
.EQU  DMA_ISR_GIF2_N, 4
.EQU  DMA_ISR_GIF2  , 1 << 4    @ Channel 2 Global interrupt flag
.EQU  DMA_ISR_TCIF2_N, 5
.EQU  DMA_ISR_TCIF2 , 1 << 5    @ Channel 2 Transfer Complete flag
.EQU  DMA_ISR_HTIF2_N, 6
.EQU  DMA_ISR_HTIF2 , 1 << 6    @ Channel 2 Half Transfer flag
.EQU  DMA_ISR_TEIF2_N, 7
.EQU  DMA_ISR_TEIF2 , 1 << 7    @  Channel 2 Transfer Error flag
.EQU  DMA_ISR_GIF3_N, 8
.EQU  DMA_ISR_GIF3  , 1 << 8    @
.EQU  DMA_ISR_TCIF3_N, 9
.EQU  DMA_ISR_TCIF3 , 1 << 9    @ Channel 3 Transfer Complete flag
.EQU  DMA_ISR_HTIF3_N, 10
.EQU  DMA_ISR_HTIF3 , 1 << 10    @ Channel 3 Half Transfer flag
.EQU  DMA_ISR_TEIF3_N, 11
.EQU  DMA_ISR_TEIF3 , 1 << 11    @ Channel 3 Transfer Error flag
.EQU  DMA_ISR_GIF4_N, 12
.EQU  DMA_ISR_GIF4  , 1 << 12    @ Channel 4 Global interrupt flag
.EQU  DMA_ISR_TCIF4_N, 13
.EQU  DMA_ISR_TCIF4 , 1 << 13    @  Channel 4 Transfer Complete flag
.EQU  DMA_ISR_HTIF4_N, 14
.EQU  DMA_ISR_HTIF4 , 1 << 14    @ Channel 4 Half Transfer flag
.EQU  DMA_ISR_TEIF4_N, 15
.EQU  DMA_ISR_TEIF4 , 1 << 15    @ Channel 4 Transfer Error flag
.EQU  DMA_ISR_GIF5_N, 16
.EQU  DMA_ISR_GIF5  , 1 << 16    @ Channel 5 Global interrupt flag
.EQU  DMA_ISR_TCIF5_N, 17
.EQU  DMA_ISR_TCIF5 , 1 << 17    @ Channel 5 Transfer Complete flag
.EQU  DMA_ISR_HTIF5_N, 18
.EQU  DMA_ISR_HTIF5 , 1 << 18    @ Channel 5 Half Transfer flag
.EQU  DMA_ISR_TEIF5_N, 19
.EQU  DMA_ISR_TEIF5 , 1 << 19    @ Channel 5 Transfer Error flag
.EQU  DMA_ISR_GIF6_N, 20
.EQU  DMA_ISR_GIF6  , 1 << 20    @ Channel 6 Global interrupt flag
.EQU  DMA_ISR_TCIF6_N, 21
.EQU  DMA_ISR_TCIF6 , 1 << 21    @ Channel 6 Transfer Complete flag
.EQU  DMA_ISR_HTIF6_N, 22
.EQU  DMA_ISR_HTIF6 , 1 << 22    @ Channel 6 Half Transfer flag
.EQU  DMA_ISR_TEIF6_N, 23
.EQU  DMA_ISR_TEIF6 , 1 << 23    @ Channel 6 Transfer Error flag
.EQU  DMA_ISR_GIF7_N, 24
.EQU  DMA_ISR_GIF7  , 1 << 24    @ Channel 7 Global interrupt flag
.EQU  DMA_ISR_TCIF7_N, 25
.EQU  DMA_ISR_TCIF7 , 1 << 25    @ Channel 7 Transfer Complete flag
.EQU  DMA_ISR_HTIF7_N, 26
.EQU  DMA_ISR_HTIF7 , 1 << 26    @ Channel 7 Half Transfer flag
.EQU  DMA_ISR_TEIF7_N, 27
.EQU  DMA_ISR_TEIF7 , 1 << 27    @ Channel 7 Transfer Error flag
@.END

@.ITEM     DMA_IFCR
.EQU  DMA_IFCR_CGIF1_N    , 0
.EQU  DMA_IFCR_CGIF1      , 1 << 0    @  Channel 1 Global interrupt clear
.EQU  DMA_IFCR_CTCIF1_N   , 1
.EQU  DMA_IFCR_CTCIF1     , 1 << 1    @  Channel 1 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF1_N   , 2
.EQU  DMA_IFCR_CHTIF1     , 1 << 2    @ Channel 1 Half Transfer clear
.EQU  DMA_IFCR_CTEIF1_N   , 3
.EQU  DMA_IFCR_CTEIF1     , 1 << 3    @ Channel 1 Transfer Error clear
.EQU  DMA_IFCR_CGIF2_N    , 4
.EQU  DMA_IFCR_CGIF2      , 1 << 4    @ Channel 2 Global interrupt clear
.EQU  DMA_IFCR_CTCIF2_N   , 5
.EQU  DMA_IFCR_CTCIF2     , 1 << 5    @ Channel 2 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF2_N   , 6
.EQU  DMA_IFCR_CHTIF2     , 1 << 6    @ Channel 2 Half Transfer clear
.EQU  DMA_IFCR_CTEIF2_N   , 7
.EQU  DMA_IFCR_CTEIF2     , 1 << 7    @ Channel 2 Transfer Error clear
.EQU  DMA_IFCR_CGIF3_N    , 8
.EQU  DMA_IFCR_CGIF3      , 1 << 8    @ Channel 3 Global interrupt clear
.EQU  DMA_IFCR_CTCIF3_N   , 9
.EQU  DMA_IFCR_CTCIF3     , 1 << 9    @ Channel 3 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF3_N   , 10
.EQU  DMA_IFCR_CHTIF3     , 1 << 10    @ Channel 3 Half Transfer clear
.EQU  DMA_IFCR_CTEIF3_N   , 11
.EQU  DMA_IFCR_CTEIF3     , 1 << 11    @ Channel 3 Transfer Error clear
.EQU  DMA_IFCR_CGIF4_N    , 12
.EQU  DMA_IFCR_CGIF4      , 1 << 12    @ Channel 4 Global interrupt clear
.EQU  DMA_IFCR_CTCIF4_N   , 13
.EQU  DMA_IFCR_CTCIF4     , 1 << 13    @ Channel 4 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF4_N   , 14
.EQU  DMA_IFCR_CHTIF4     , 1 << 14    @ Channel 4 Half Transfer clear
.EQU  DMA_IFCR_CTEIF4_N   , 15
.EQU  DMA_IFCR_CTEIF4     , 1 << 15    @ Channel 4 Transfer Error clear
.EQU  DMA_IFCR_CGIF5_N    , 16
.EQU  DMA_IFCR_CGIF5      , 1 << 16    @ Channel 5 Global interrupt clear
.EQU  DMA_IFCR_CTCIF5_N   , 17
.EQU  DMA_IFCR_CTCIF5     , 1 << 17    @ Channel 5 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF5_N   , 18
.EQU  DMA_IFCR_CHTIF5     , 1 << 18    @  Channel 5 Half Transfer clear
.EQU  DMA_IFCR_CTEIF5_N   , 19
.EQU  DMA_IFCR_CTEIF5     , 1 << 19    @ Channel 5 Transfer Error clear
.EQU  DMA_IFCR_CGIF6_N    , 20
.EQU  DMA_IFCR_CGIF6      , 1 << 20    @ Channel 6 Global interrupt clear
.EQU  DMA_IFCR_CTCIF6_N   , 21
.EQU  DMA_IFCR_CTCIF6     , 1 << 21    @ Channel 6 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF6_N   , 22
.EQU  DMA_IFCR_CHTIF6     , 1 << 22    @  Channel 6 Half Transfer clear
.EQU  DMA_IFCR_CTEIF6_N   , 23
.EQU  DMA_IFCR_CTEIF6     , 1 << 23    @ Channel 6 Transfer Error clear
.EQU  DMA_IFCR_CGIF7_N    , 24
.EQU  DMA_IFCR_CGIF7      , 1 << 24    @ Channel 7 Global interrupt clear
.EQU  DMA_IFCR_CTCIF7_N   , 25
.EQU  DMA_IFCR_CTCIF7     , 1 << 25    @ Channel 7 Transfer Complete clear
.EQU  DMA_IFCR_CHTIF7_N   , 26
.EQU  DMA_IFCR_CHTIF7     , 1 << 26    @ Channel 7 Half Transfer clear
.EQU  DMA_IFCR_CTEIF7_N   , 27
.EQU  DMA_IFCR_CTEIF7     , 1 << 27    @  hannel 7 Transfer Error clear
@.END

@.ITEM   DMA_CCR1 DMA_CCR2 DMA_CCR3 DMA_CCR4  DMA_CCR5 DMA_CCR6 DMA_CCR7
.EQU  DMA_CCR_EN_N        , 0
.EQU  DMA_CCR_EN          , 1 << 0    @ Channel enable
.EQU  DMA_CCR_TCIE_N      , 1
.EQU  DMA_CCR_TCIE        , 1 << 1    @ Transfer complete interrupt enable
.EQU  DMA_CCR_HTIE_N      , 2
.EQU  DMA_CCR_HTIE        , 1 << 2    @ Half Transfer interrupt enable
.EQU  DMA_CCR_TEIE_N      , 3
.EQU  DMA_CCR_TEIE        , 1 << 3    @ Transfer error interrupt enable
.EQU  DMA_CCR_DIR_N       , 4
.EQU  DMA_CCR_DIR         , 1 << 4    @ Data transfer direction
.EQU  DMA_CCR_CIRC_N      , 5
.EQU  DMA_CCR_CIRC        , 1 << 5    @ Circular mode
.EQU  DMA_CCR_PINC_N      , 6
.EQU  DMA_CCR_PINC        , 1 << 6    @ Peripheral increment mode
.EQU  DMA_CCR_MINC_N      , 7
.EQU  DMA_CCR_MINC        , 1 << 7    @ Bit 7 MINC: Memory increment mode
.EQU  DMA_CCR_PSIZE_N     , 8    @ Bits 9:8 PSIZE[1:0]: Peripheral size
.EQU  DMA_CCR_PSIZE       , 0x00 << 8    @  00: 8-bits
.EQU  DMA_CCR_PSIZE_0     , 0x01 << 8    @  01: 16-bits
.EQU  DMA_CCR_PSIZE_1     , 0x10 << 8    @  10: 32-bits
.EQU  DMA_CCR_MSIZE_N     , 10    @ Bits 11:10 MSIZE[1:0]: Memory size
.EQU  DMA_CCR_MSIZE       , 0x00 << 10    @  00: 8-bits
.EQU  DMA_CCR_MSIZE_0     , 0x01 << 10    @  01: 16-bits
.EQU  DMA_CCR_MSIZE_1     , 0x10 << 10    @  10: 32-bits
.EQU  DMA_CCR_PL_N        , 12    @ Bits 13:12 PL[1:0]: Channel priority level
.EQU  DMA_CCR_PL_L        , 0x00 << 10    @  00: Low
.EQU  DMA_CCR_PL_M        , 0x01 << 10    @  01: Medium
.EQU  DMA_CCR_PL_H        , 0x10 << 10    @  10: High
.EQU  DMA_CCR_PL_VH       , 0x11 << 10    @  11: Very high
.EQU  DMA_CCR_MEM2MEM_N   , 14    @ Bit 14 MEM2MEM: Memory to memory mode
.EQU  DMA_CCR_MEM2MEM     , 1 << 14    @  1: Memory to memory mode enabled
@.END

@.ITEM  DMA_CNDTR1 DMA_CNDTR2  DMA_CNDTR3  DMA_CNDTR4  DMA_CNDTR5   DMA_CNDTR6  DMA_CNDTR7
.EQU DMA_CNDTR_NDT_N  , 0  @ Bits 15:0 NDT[15:0]: Number of data to transfer
.EQU DMA_CNDTR_NDT_M  ,   0xFFFF << 0
@.END

@.ITEM  DMA_CPAR1 DMA_CPAR2  DMA_CPAR3 DMA_CPAR4  DMA_CPAR5 DMA_CPAR6  DMA_CPAR7
.EQU DMA_CPAR_PA_N    ,  0   @ Bits 31:0 PA[31:0]: Peripheral address
.EQU DMA_CPAR_PA_M    ,   0xFFFFFFFF << 0
@.END

@.ITEM  DMA_CMAR1 DMA_CMAR2  DMA_CMAR3 DMA_CMAR4 DMA_CMAR5  DMA_CMAR6 DMA_CMAR7
.EQU DMA_CMAR_MA_N    ,  0  @ Bits 31:0 MA[31:0]: Memory addres
.EQU DMA_CMAR_MA_M   ,    (0xFFFFFFFF << 0)
@.END

