@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                         константы DAC                            |
@ |                            STM32L1xx                             |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@ константы DAC
@.item     APB1PERIPH_BASE
.equ  DAC_BASE           , APB1PERIPH_BASE + 0x7400
.equ  DAC                , PERIPH_BASE + DAC_BASE
@.END

@.item    DAC_BASE  DAC
.equ  DAC_CR             , 0x00    @ DAC control register
.equ  DAC_SWTRIGR        , 0x04    @ DAC software trigger register
.equ  DAC_DHR12R1        , 0x08    @ DAC channel1 12-bit right-aligned data holding register
.equ  DAC_DHR12L1        , 0x0C    @ DAC channel1 12-bit left aligned data holding register
.equ  DAC_DHR8R1         , 0x10    @ DAC channel1 8-bit right aligned data holding register
.equ  DAC_DHR12R2        , 0x14    @ DAC channel2 12-bit right aligned data holding register
.equ  DAC_DHR12L2        , 0x18    @ DAC channel2 12-bit left aligned data holding register
.equ  DAC_DHR8R2         , 0x1C    @ DAC channel2 8-bit right-aligned data holding register
.equ  DAC_DHR12RD        , 0x20    @ Dual DAC 12-bit right-aligned data holding register
.equ  DAC_DHR12LD        , 0x24    @ DUAL DAC 12-bit left aligned data holding register
.equ  DAC_DHR8RD         , 0x28    @ DUAL DAC 8-bit right aligned data holding register
.equ  DAC_DOR1           , 0x2C    @ DAC channel1 data output register
.equ  DAC_DOR2           , 0x30    @ DAC channel2 data output register
.equ  DAC_SR             , 0x34    @ DAC status register
@.END

@ Описание битов настройки регистра  DAC_CR
@.item     DAC_CR
.equ  DAC_CR_EN1_N       , 0             @ Bit 0 EN1: DAC channel1 enable
                                         @ This bit is set and cleared by software to enable/disable DAC channel1.
                                         @ 0: DAC channel1 disabled
.equ  DAC_CR_EN1         , 1             @ 1: DAC channel1 enabled
.equ  DAC_CR_BOFF1_N     , 1             @ Bit 1 BOFF1: DAC channel1 output buffer disable
                                         @ This bit is set and cleared by software to enable/disable DAC channel1 output buffer.
                                         @ 0: DAC channel1 output buffer enabled
.equ  DAC_CR_BOFF1       , 1<<1          @ 1: DAC channel1 output buffer disabled
.equ  DAC_CR_TEN1_N      , 2             @ Bit 2 TEN1: DAC channel1 trigger enable
                                         @ This bit is set and cleared by software to enable/disable DAC channel1 trigger.
                                         @ 0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are
                                         @ transferred one APB1 clock cycle later to the DAC_DOR1 register
.equ  DAC_CR_TEN1        , 1<<2          @ 1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred
                                         @ three APB1 clock cycles later to the DAC_DOR1 register
                                   @ Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
                                         @ DAC_DOR1 register takes only one APB1 clock cycle.
.equ  DAC_CR_TSEL1_N     , 3             @ Bits 5:3 TSEL1[2:0]: DAC channel 1 trigger selection
                                         @ These bits select the external event used to trigger DAC channel2
.equ  DAC_CR_TSEL1_T6TRGO, 0             @ 000: Timer 6 TRGO event
                                         @ 001: Reserved
.equ  DAC_CR_TSEL1_T7TRGO, 2<<3          @ 010: Timer 7 TRGO event
.equ  DAC_CR_TSEL1_T9TRGO, 3<<3          @ 011: Timer 9 TRGO event
.equ  DAC_CR_TSEL1_T2TRGO, 4<<3          @ 100: Timer 2 TRGO event
.equ  DAC_CR_TSEL1_T4TRGO, 5<<3          @ 101: Timer 4 TRGO event
.equ  DAC_CR_TSEL1_EXT9  , 6<<3          @ 110: External line9
.equ  DAC_CR_TSEL1_SOFT  , 7<<3          @ 111: Software trigger
                                   @ Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
.equ  DAC_CR_WAVE1_N     , 6             @ Bits 7:6 WAVE1[1:0]: DAC channel 1 noise/triangle wave generation enable
                                         @ These bits are set/reset by software.
.equ  DAC_CR_WAVE1_DISABLE, 0            @ 00: wave generation disabled
.equ  DAC_CR_WAVE1_NOISEWAVE, 1<<6       @ 01: Noise wave generation enabled
.equ  DAC_CR_WAVE1_TRIANGLE, 1<<6        @ 1x: Triangle wave generation enabled
                                         @ Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
.equ  DAC_CR_MAMP1_N     , 8             @ Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
                                         @ These bits are written by software to select mask in wave generation mode or amplitude in
                                         @ triangle generation mode.
.equ  DAC_CR_MAMP1_A1    , 0             @ 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
.equ  DAC_CR_MAMP1_A3    , 1<<8          @ 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
.equ  DAC_CR_MAMP1_A7    , 2<<8          @ 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
.equ  DAC_CR_MAMP1_A15   , 3<<8          @ 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
.equ  DAC_CR_MAMP1_A31   , 4<<8          @ 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
.equ  DAC_CR_MAMP1_A63   , 5<<8          @ 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
.equ  DAC_CR_MAMP1_A127  , 6<<8          @ 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
.equ  DAC_CR_MAMP1_A255  , 7<<8          @ 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
.equ  DAC_CR_MAMP1_A511  , 8<<8          @ 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
.equ  DAC_CR_MAMP1_A1023 , 9<<8          @ 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
.equ  DAC_CR_MAMP1_A2047 , 10<<8         @ 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
.equ  DAC_CR_MAMP1_A4095 , 11<<8         @  1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
.equ  DAC_CR_DMAEN1_N    , 12            @ Bit 12 DMAEN1: DAC channel1 DMA enable
                                         @ This bit is set and cleared by software.
                                         @ 0: DAC channel1 DMA mode disabled
.equ  DAC_CR_DMAEN1      , 1<<12         @ 1: DAC channel1 DMA mode enabled
.equ  DAC_CR_DMAUDRIE_N  , 13            @ Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
                                         @ This bit is set and cleared by software.
                                         @ 0: DAC channel1 DMA Underrun Interrupt disabled
.equ  DAC_CR_DMAUDRIE    , 1<<13         @ 1: DAC channel1 DMA Underrun Interrupt enabled
.equ  DAC_CR_EN2_N       , 16            @ Bit 16 EN2: DAC channel2 enable
                                         @ This bit is set and cleared by software to enable/disable DAC channel2.
                                         @ 0: DAC channel2 disabled
.equ  DAC_CR_EN2         , 1<<16         @ 1: DAC channel2 enabled
.equ  DAC_CR_BOFF2_N     , 17            @ Bit 17 BOFF2: DAC channel2 output buffer disable
                                         @ This bit is set and cleared by software to enable/disable DAC channel2 output buffer.
                                         @ 0: DAC channel2 output buffer enabled
.equ  DAC_CR_BOFF2       , 1<<17         @ 1: DAC channel2 output buffer disabled
.equ  DAC_CR_TEN2_N      , 18            @ Bit 18 TEN2: DAC channel2 trigger enable
                                         @ This bit is set and cleared by software to enable/disable DAC channel2 trigger
                                         @ 0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are
                                         @ transferred one APB1 clock cycle later to the DAC_DOR2 register
.equ  DAC_CR_TEN2        , 1<<18         @ 1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred
                                         @ three APB1 clock cycles later to the DAC_DOR2 register
                                   @ Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
                                         @ DAC_DOR2 register takes only one APB1 clock cycle.
.equ  DAC_CR_TSEL2_N     , 19            @ Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection
                                         @ These bits select the external event used to trigger DAC channel2
.equ  DAC_CR_TSEL2_T6TRGO, 0             @ 000: Timer 6 TRGO event
                                         @ 001: Reserved
.equ  DAC_CR_TSEL2_T7TRGO, 2<<19         @ 010: Timer 7 TRGO event
.equ  DAC_CR_TSEL2_T9TRGO, 3<<19         @ 011: Timer 9 TRGO event
.equ  DAC_CR_TSEL2_T2TRGO, 4<<19         @ 100: Timer 2 TRGO event
.equ  DAC_CR_TSEL2_T4TRGO, 5<<19         @ 101: Timer 4 TRGO event
.equ  DAC_CR_TSEL2_EXT9  , 6<<19         @ 110: External line9
.equ  DAC_CR_TSEL2_SOFT  , 7<<19         @ 111: Software trigger
                                   @ Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
.equ  DAC_CR_WAVE2_N     , 22            @ Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
                                         @ These bits are set/reset by software.
.equ  DAC_CR_WAVE2_DISABLE, 0            @ 00: wave generation disabled
.equ  DAC_CR_WAVE2_NOISEWAVE, 1<<22      @ 01: Noise wave generation enabled
.equ  DAC_CR_WAVE2_TRIANGLE, 1<<22       @ 1x: Triangle wave generation enabled
                                         @ Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
.equ  DAC_CR_MAMP2_N     , 24            @ Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector
                                         @ These bits are written by software to select mask in wave generation mode or amplitude in
                                         @ triangle generation mode.
.equ  DAC_CR_MAMP2_A1    , 0             @ 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
.equ  DAC_CR_MAMP2_A3    , 1<<24         @ 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
.equ  DAC_CR_MAMP2_A7    , 2<<24         @ 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
.equ  DAC_CR_MAMP2_A15   , 3<<24         @ 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
.equ  DAC_CR_MAMP2_A31   , 4<<24         @ 0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
.equ  DAC_CR_MAMP2_A63   , 5<<24         @ 0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
.equ  DAC_CR_MAMP2_A127  , 6<<24         @ 0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
.equ  DAC_CR_MAMP2_A255  , 7<<24         @ 0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
.equ  DAC_CR_MAMP2_A511  , 8<<24         @ 1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
.equ  DAC_CR_MAMP2_A1023 , 9<<24         @ 1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
.equ  DAC_CR_MAMP2_A2047 , 10<<24        @ 1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
.equ  DAC_CR_MAMP2_A4095 , 11<<24        @  1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
.equ  DAC_CR_DMAEN2_N    , 28            @ Bit 28 DMAEN2: DAC channel2 DMA enable
                                         @ This bit is set and cleared by software.
                                         @ 0: DAC channel2 DMA mode disabled
.equ  DAC_CR_DMAEN2      , 1<<28         @ 1: DAC channel2 DMA mode enabled
.EQU  DAC_CR_DMAUDRIE_N, 29              @ Bits 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
                                         @ This bit is set and cleared by software.
                                         @ 0: DAC channel2 DMA underrun interrupt disabled
.EQU  DAC_CR_DMAUDRIE, 1<<29             @ 1: DAC channel2 DMA underrun interrupt enabled
@.END

@.ITEM     DAC_SWTRIGR
.equ  DAC_SWTRIGR_SWTRIG2_N, 1     @ Bit 1 SWTRIG2: DAC channel2 software trigger
                                   @ This bit is set and cleared by software to enable/disable the software trigger.
                                   @ 0: Software trigger disabled
.equ  DAC_SWTRIGR_SWTRIG2, 1<<1    @ 1: Software trigger enabled
                             @ Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
                                   @ register value has been loaded into the DAC_DOR2 register.
.equ  DAC_SWTRIGR_SWTRIG1_N, 0     @ Bit 0 SWTRIG1: DAC channel1 software trigger
                                   @ This bit is set and cleared by software to enable/disable the software trigger.
                                   @ 0: Software trigger disabled
.equ  DAC_SWTRIGR_SWTRIG1  , 1     @ 1: Software trigger enabled
                             @ Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
                                   @ register value has been loaded into the DAC_DOR1 register.
@.END

@.item     DAC_DHR12R1
.equ DAC_DHR12R1_DACC1DHR_M, 0x0FFF  @ Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
                                   @ These bits are written by software which specifies 12-bit data for DAC channel1
@.END

@.item     DAC_DHR12L1
.equ DAC_DHR12L1_DACC1DHR_M, 0xFFF0  @ Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
                                   @ These bits are written by software which specifies 12-bit data for DAC channel1.
@.END

@.ITEM     DAC_DHR8R1
.EQU  DAC_DHR8R1_DACC1DHR_M, 0xFF    @ Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
                                   @ These bits are written by software which specifies 8-bit data for DAC channel1.
@.END

@.ITEM     DAC_DHR12R2
.EQU  DAC_DHR12R2_DACC2DHR_M, 0x0FFF   @ Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
                                     @ These bits are written by software which specifies 12-bit data for DAC channel2.
@.END

@.ITEM     DAC_DHR12L2
.equ DAC_DHR12L2_DACC2DHR_M, 0xFFF0    @ Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
                                     @ These bits are written by software which specify 12-bit data for DAC channel2.
@.END

@.item     DAC_DHR8R2
.equ DAC_DHR8R2_DACC2DHR_M, 0xFF       @ Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
                                     @ These bits are written by software which specifies 8-bit data for DAC channel2.
@.END

@.item     DAC_DHR12RD
.equ DAC_DHR12RD_DACC1DHR_M, 0x00000FFF @ Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
.equ DAC_DHR12RD_DACC1DHR_N, 0          @ These bits are written by software which specifies 12-bit data for DAC channel1
.equ DAC_DHR12RD_DACC2DHR_M, 0x0FFF0000 @Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
.equ DAC_DHR12RD_DACC2DHR_N, 16         @ These bits are written by software which specifies 12-bit data for DAC channel2.
@.END

@.item     DAC_DHR12LD
.equ DAC_DHR12LD_DACC1DHR_M, 0x0000FFF0 @ Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
.equ DAC_DHR12LD_DACC1DHR_N, 4          @ These bits are written by software which specifies 12-bit data for DAC channel1.
.equ DAC_DHR12LD_DACC2DHR_M, 0xFFF00000 @ Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
.equ DAC_DHR12LD_DACC2DHR_N, 20         @ These bits are written by software which specifies 12-bit data for DAC channel2.
@.END

@.item     DAC_DHR8RD
.equ DAC_DHR8RD_DACC1DHR_M, 0x00FF      @ Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
.equ DAC_DHR8RD_DACC1DHR_N, 0           @ These bits are written by software which specifies 8-bit data for DAC channel1.
.equ DAC_DHR8RD_DACC2DHR_M, 0xFF00      @ Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
.equ DAC_DHR8RD_DACC2DHR_N, 8           @ These bits are written by software which specifies 8-bit data for DAC channel2
@.END

@.item     DAC_DOR1
.equ DAC_DOR1_DACC1DOR_M, 0x0FFF        @ Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
                                        @ These bits are read-only, they contain data output for DAC channel1.
@.END

@.item     DAC_DOR2
.equ DAC_DOR2_DACC2DOR_M, 0x0FFF        @ Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
                                        @ These bits are read-only, they contain data output for DAC channel2.
@.END

@.item     DAC_SR
.equ DAC_SR_DMAUDR1_N, 13                @ Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
                                         @ This bit is set by hardware and cleared by software (by writing it to 1).
                                         @ 0: No DMA underrun error condition occurred for DAC channel1
.equ DAC_SR_DMAUDR1   , 1<<13            @ 1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
                                         @ driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
.equ DAC_SR_DMAUDR2_N, 29                @ Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
                                         @ This bit is set by hardware and cleared by software (by writing it to 1).
                                         @ 0: No DMA underrun error condition occurred for DAC channel2
.equ DAC_SR_DMAUDR2, 1<<29               @ 1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
                                         @ driving DAC channel2 conversion at a frequency higher than the DMA service capability rate)
@.END

