@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Áàçîâûå êîíñòàíòû RCC                        |
@ |                           STM32F303                              |
@ +------------------------------------------------------------------+
@.enddesc


.include "/src/inc/base.inc"

@.item AHB1PERIPH_BASE
.equ     RCC_BASE     , (AHB1PERIPH_BASE + 0x1000) @ Áàçîâûé àäðåñ RCC
@.end

@.item RCC_BASE
.equ RCC_CR       , 0x00 @ RCC clock control register
.equ RCC_CFGR     , 0x04 @ Clock configuration register
.equ RCC_CIR      , 0x08 @ Clock interrupt register
.equ RCC_APB2RSTR , 0x0C @ RCC APB2 peripheral reset register
.equ RCC_APB1RSTR , 0x10 @ RCC APB1 peripheral reset register
.equ RCC_AHBENR   , 0x14 @ RCC AHB peripheral clock register
.equ RCC_APB2ENR  , 0x18 @ RCC APB2 peripheral clock enable register
.equ RCC_APB1ENR  , 0x1C @ RCC APB1 peripheral clock enable register
.equ RCC_BDCR     , 0x20 @ RCC Backup domain control register
.equ RCC_CSR      , 0x24 @ RCC clock control & status register
.equ RCC_AHBRSTR  , 0x28 @ RCC AHB peripheral reset register
.equ RCC_CFGR2    , 0x2C @
.equ RCC_CFGR3    , 0x30 @
@.end

@.item RCC_CR
.equ RCC_CR_HSION              , 0x00000001 @ Bit 0 HSION: Internal high-speed clock enable
.equ RCC_CR_HSION_N            , 0
.equ RCC_CR_HSIRDY             , 0x00000002 @ Bit 1 HSIRDY: Internal high-speed clock ready flag
.equ RCC_CR_HSIRDY_N           , 1
.equ RCC_CR_HSITRIM_N          , 3 @ Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
.equ RCC_CR_HSICAL_N           , 8 @ Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
.equ RCC_CR_HSEON              , 0x00010000 @ Bit 16 HSEON: HSE clock enable
.equ RCC_CR_HSEON_N            , 16
.equ RCC_CR_HSERDY             , 0x00020000 @ Bit 17 HSERDY: HSE clock ready flag
.equ RCC_CR_HSERDY_N           , 17
.equ RCC_CR_HSEBYP             , 0x00040000 @ Bit 18 HSEBYP: HSE clock bypass
.equ RCC_CR_HSEBYP_N           , 18
.equ RCC_CR_CSSON              , 0x00080000 @ Bit 19 CSSON: Clock security system enable
.equ RCC_CR_CSSON_N            , 19
.equ RCC_CR_PLLON              , 0x01000000 @ Bit 24 PLLON: Main PLL (PLL) enable
.equ RCC_CR_PLLON_N            , 24
.equ RCC_CR_PLLRDY             , 0x02000000 @ Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
.equ RCC_CR_PLLRDY_N           , 25
@.end

@.item RCC_CFGR
.equ  RCC_CFGR_SW_HSI          , 0x00000000 @ Bits 1:0 SW: System clock switch
.equ  RCC_CFGR_SW_HSE          , 0x00000001
.equ  RCC_CFGR_SW_PLL          , 0x00000002
.equ  RCC_CFGR_SWS_N           , 2 @ Bits 3:2 SWS: System clock switch status
.equ  RCC_CFGR_SWS_HSI         , 0x00
.equ  RCC_CFGR_SWS_HSE         , 0x04
.equ  RCC_CFGR_SWS_PLL         , 0x08
.equ  RCC_CFGR_HPRE_N          , 4
.equ  RCC_CFGR_HPRE_DIV1       , 0x00000000 @ Bits 7:4 HPRE: AHB prescaler
.equ  RCC_CFGR_HPRE_DIV2       , 0x00000080
.equ  RCC_CFGR_HPRE_DIV4       , 0x00000090
.equ  RCC_CFGR_HPRE_DIV8       , 0x000000A0
.equ  RCC_CFGR_HPRE_DIV16      , 0x000000B0
.equ  RCC_CFGR_HPRE_DIV64      , 0x000000C0
.equ  RCC_CFGR_HPRE_DIV128     , 0x000000D0
.equ  RCC_CFGR_HPRE_DIV256     , 0x000000E0
.equ  RCC_CFGR_HPRE_DIV512     , 0x000000F0
.equ  RCC_CFGR_PPRE1_N         , 8          @ Bits 10:8 PPRE1: APB Low speed prescaler (APB1)
.equ  RCC_CFGR_PPRE1_DIV1      , 0          @ HCLK not divided
.equ  RCC_CFGR_PPRE1_DIV2      , 0b100<<8   @ HCLK divided by 2
.equ  RCC_CFGR_PPRE1_DIV4      , 0b101<<8   @ HCLK divided by 4
.equ  RCC_CFGR_PPRE1_DIV8      , 0b110<<8   @ HCLK divided by 8
.equ  RCC_CFGR_PPRE1_DIV16     , 0b111<<8   @ HCLK divided by 16
.equ  RCC_CFGR_PPRE2_N         , 11         @ Bits 15:13 PPRE2: APB high-speed prescaler (APB2)
.equ  RCC_CFGR_PPRE2_DIV1      , 0          @ HCLK not divided
.equ  RCC_CFGR_PPRE2_DIV2      , 0b100<<11  @ HCLK divided by 2
.equ  RCC_CFGR_PPRE2_DIV4      , 0b101<<11  @ HCLK divided by 4
.equ  RCC_CFGR_PPRE2_DIV8      , 0b110<<11  @ HCLK divided by 8
.equ  RCC_CFGR_PPRE2_DIV16     , 0b111<<11  @ HCLK divided by 16
.equ  RCC_CFGR_PLLSRC_N        , 16         @ Bit 16 PLLSRC: PLL entry clock source
.equ  RCC_CFGR_PLLXTPRE_N      , 17         @ Bit 17 PLLXTPRE: HSE divider for PLL input clock
.equ  RCC_CFGR_PLLMUL_N        , 18         @ Bits 21:18 PLLMUL: PLL multiplication factor
.equ  RCC_CFGR_PLLMUL_x2       , 0          @ PLL input clock x 2
.equ  RCC_CFGR_PLLMUL_x3       , 1<<18      @ PLL input clock x 3
.equ  RCC_CFGR_PLLMUL_x4       , 2<<18      @ PLL input clock x 4
.equ  RCC_CFGR_PLLMUL_x5       , 3<<18      @ PLL input clock x 5
.equ  RCC_CFGR_PLLMUL_x6       , 4<<18      @ PLL input clock x 6
.equ  RCC_CFGR_PLLMUL_x7       , 5<<18      @ PLL input clock x 7
.equ  RCC_CFGR_PLLMUL_x8       , 6<<18      @ PLL input clock x 8
.equ  RCC_CFGR_PLLMUL_x9       , 7<<18      @ PLL input clock x 9
.equ  RCC_CFGR_PLLMUL_x10      , 8<<18      @ PLL input clock x 10
.equ  RCC_CFGR_PLLMUL_x11      , 9<<18      @ PLL input clock x 11
.equ  RCC_CFGR_PLLMUL_x12      , 10<<18     @ PLL input clock x 12
.equ  RCC_CFGR_PLLMUL_x13      , 11<<18     @ PLL input clock x 13
.equ  RCC_CFGR_PLLMUL_x14      , 12<<18     @ PLL input clock x 14
.equ  RCC_CFGR_PLLMUL_x15      , 13<<18     @ PLL input clock x 15
.equ  RCC_CFGR_PLLMUL_x16      , 14<<18     @ PLL input clock x 16
.equ  RCC_CFGR_PLLMUL_x16      , 15<<18     @ PLL input clock x 16
.equ  RCC_CFGR_USBPRE_N        , 22         @ Bit 22 USBPRE: USB prescaler
.equ  RCC_CFGR_USBPRE          , 1<<22      @ PLL clock is not divided
.equ  RCC_CFGR_I2SSRC_N        , 23
.equ  RCC_CFGR_I2SSRC          , 0x00800000 @ Bit 23 I2SSRC: I2S clock selection
.equ  RCC_CFGR_MCO_N           , 24         @ Bits 26:24 MCO: Microcontroller clock output
.equ  RCC_CFGR_MCO_0           , 0x00       @ MCO output disabled, no clock on MCO
.equ  RCC_CFGR_MCO_1           , 1<<24      @ Reserved
.equ  RCC_CFGR_MCO_2           , 2<<24      @ LSI clock selected.
.equ  RCC_CFGR_MCO_3           , 3<<24      @ LSE clock selected.
.equ  RCC_CFGR_MCO_4           , 4<<24      @ System clock (SYSCLK) selected
.equ  RCC_CFGR_MCO_5           , 5<<24      @ HSI clock selected
.equ  RCC_CFGR_MCO_6           , 6<<24      @ HSE clock selected
.equ  RCC_CFGR_MCO_7           , 7<<24      @ PLL clock selected (divided by 1 or 2 depending on PLLNODIV bit).
.equ  RCC_CFGR_MCOPRE_N        , 28
.equ  RCC_CFGR_MCOPRE_1        , 0<<28      @ MCO is divided by 1
.equ  RCC_CFGR_MCOPRE_2        , 1<<28      @ MCO is divided by 2
.equ  RCC_CFGR_MCOPRE_4        , 2<<28      @ MCO is divided by 4
.equ  RCC_CFGR_MCOPRE_8        , 3<<28      @ MCO is divided by 8
.equ  RCC_CFGR_MCOPRE_16       , 4<<28      @ MCO is divided by 16
.equ  RCC_CFGR_MCOPRE_32       , 5<<28      @ MCO is divided by 32
.equ  RCC_CFGR_MCOPRE_64       , 6<<28      @ MCO is divided by 64
.equ  RCC_CFGR_MCOPRE_128      , 7<<28      @ MCO is divided by 128
.equ  RCC_CFGR_PLLNODIV_N      , 31         @ Bit 31 PLLNODIV: Do not divide PLL to MCO (in STM32F303x6/8 and STM32F328x8 , STM32F303xDxE and STM32F398xE only)
.equ  RCC_CFGR_PLLNODIV        , 1<<31
@.end

@.item RCC_CIR
.equ  RCC_CIR_LSIRDYF_N           , 0 @ Bit 0 LSIRDYF: LSI ready interrupt flag
.equ  RCC_CIR_LSIRDYF            , 0x00000001
.equ  RCC_CIR_LSERDYF_N          , 1 @ Bit 1 LSERDYF: LSE ready interrupt flag
.equ  RCC_CIR_LSERDYF            , 0x00000002
.equ  RCC_CIR_HSIRDYF_N          , 2 @ Bit 2 HSIRDYF: HSI ready interrupt flag
.equ  RCC_CIR_HSIRDYF            , 0x00000004
.equ  RCC_CIR_HSERDYF_N          , 3 @ Bit 3 HSERDYF: HSE ready interrupt flag
.equ  RCC_CIR_HSERDYF            , 0x00000008
.equ  RCC_CIR_PLLRDYF_N          , 4 @ Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
.equ  RCC_CIR_PLLRDYF            , 0x00000010
.equ  RCC_CIR_CSSF_N             , 7 @ Bit 7 CSSF: Clock security system interrupt flag
.equ  RCC_CIR_CSSF               , 0x00000080
.equ  RCC_CIR_LSIRDYIE_N         , 8 @ Bit 8 LSIRDYIE: LSI ready interrupt enable
.equ  RCC_CIR_LSIRDYIE           , 0x00000100
.equ  RCC_CIR_LSERDYIE_N         , 9 @ Bit 9 LSERDYIE: LSE ready interrupt enable
.equ  RCC_CIR_LSERDYIE           , 0x00000200
.equ  RCC_CIR_HSIRDYIE_N         , 10 @ Bit 10 HSIRDYIE: HSI ready interrupt enable
.equ  RCC_CIR_HSIRDYIE           , 0x00000400
.equ  RCC_CIR_HSERDYIE_N         , 11 @ Bit 11 HSERDYIE: HSE ready interrupt enable
.equ  RCC_CIR_HSERDYIE           , 0x00000800
.equ  RCC_CIR_PLLRDYIE_N         , 12 @ Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
.equ  RCC_CIR_PLLRDYIE           , 0x00001000
.equ  RCC_CIR_LSIRDYC_N          , 16 @ Bit 16 LSIRDYC: LSI ready interrupt clear
.equ  RCC_CIR_LSIRDYC            , 0x00010000
.equ  RCC_CIR_LSERDYC_N          , 17 @ Bit 17 LSERDYC: LSE ready interrupt clear
.equ  RCC_CIR_LSERDYC            , 0x00020000
.equ  RCC_CIR_HSIRDYC_N          , 18 @ Bit 18 HSIRDYC: HSI ready interrupt clear
.equ  RCC_CIR_HSIRDYC            , 0x00040000
.equ  RCC_CIR_HSERDYC_N          , 19 @ Bit 19 HSERDYC: HSE ready interrupt clear
.equ  RCC_CIR_HSERDYC            , 0x00080000
.equ  RCC_CIR_PLLRDYC_N          , 20 @ Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
.equ  RCC_CIR_PLLRDYC            , 0x00100000
.equ  RCC_CIR_CSSC_N             , 23 @ Bit 23 CSSC: Clock security system interrupt clear
.equ  RCC_CIR_CSSC               , 0x00800000
@.end

@.item RCC_APB2RSTR
.equ  RCC_APB2RSTR_SYSCFGRST_N   , 0
.equ  RCC_APB2RSTR_TIM1RST_N     , 11
.equ  RCC_APB2RSTR_SPI1RST_N     , 12
.equ  RCC_APB2RSTR_TIM8RST_N     , 13
.equ  RCC_APB2RSTR_USART1RST_N   , 14
.equ  RCC_APB2RSTR_SPI4RST_N     , 15
.equ  RCC_APB2RSTR_TIM15RST_N    , 16
.equ  RCC_APB2RSTR_TIM16RST_N    , 17
.equ  RCC_APB2RSTR_TIM17RST_N    , 18
.equ  RCC_APB2RSTR_TIM20RST_N    , 20
@.end

@.item RCC_APB1RSTR
.equ  RCC_APB1RSTR_TIM2RST_N     , 0
.equ  RCC_APB1RSTR_TIM3RST_N     , 1
.equ  RCC_APB1RSTR_TIM4RST_N     , 2
.equ  RCC_APB1RSTR_TIM6RST_N     , 4
.equ  RCC_APB1RSTR_TIM7RST_N     , 5
.equ  RCC_APB1RSTR_WWDGRST_N     , 11
.equ  RCC_APB1RSTR_SPI2RST_N     , 14
.equ  RCC_APB1RSTR_SPI3RST_N     , 15
.equ  RCC_APB1RSTR_USART2RST_N   , 17
.equ  RCC_APB1RSTR_USART3RST_N   , 18
.equ  RCC_APB1RSTR_UART4RST_N    , 19
.equ  RCC_APB1RSTR_UART5RST_N    , 20
.equ  RCC_APB1RSTR_I2C1RST_N     , 21
.equ  RCC_APB1RSTR_I2C2RST_N     , 22
.equ  RCC_APB1RSTR_USBRST_N      , 23
.equ  RCC_APB1RSTR_CANRST_N      , 25
.equ  RCC_APB1RSTR_DAC2RST_N     , 26
.equ  RCC_APB1RSTR_PWRRST_N      , 28
.equ  RCC_APB1RSTR_DAC1RST_N     , 29
.equ  RCC_APB1RSTR_I2C3RST_N     , 30
@.end

@.item RCC_AHBENR
.equ  RCC_AHBENR_DMA1EN_N       , 0  @ Bit 0 DMA1EN: DMA1 clock enable
.equ  RCC_AHBENR_DMA1EN         , 1
.equ  RCC_AHBENR_DMA2EN_N       , 1  @ Bit 1 DMA2EN: DMA2 clock enable
.equ  RCC_AHBENR_DMA2EN         , 1<<1
.equ  RCC_AHBENR_SRAMEN_N       , 2  @ Bit 2 SRAMEN: SRAM interface clock enable
.equ  RCC_AHBENR_SRAMEN         , 1<<2
.equ  RCC_AHBENR_FLITFEN_N      , 4  @ Bit 4 FLITFEN: FLITF clock enable
.equ  RCC_AHBENR_FLITFEN        , 1<<4
.equ  RCC_AHBENR_FMCEN_N        , 5  @ Bit 5 FMCEN: FMC clock enable. (Only on STM32F303xDxE)
.equ  RCC_AHBENR_FMCEN          , 1<<5
.equ  RCC_AHBENR_CRCEN_N        , 6  @ Bit 6 CRCEN: CRC clock enable
.equ  RCC_AHBENR_CRCEN          , 1<<6
.equ  RCC_AHBENR_GPIOHEN_N      , 16 @ Bit 16 GPIOHEN: IO port H clock enable
.equ  RCC_AHBENR_GPIOHEN        , 1<<16
.equ  RCC_AHBENR_GPIOAEN        , 1<<17 @ Bit 17 GPIOAEN: IO port A clock enable
.equ  RCC_AHBENR_GPIOAEN_N      , 17
.equ  RCC_AHBENR_GPIOBEN        , 1<<18 @ Bit 18 GPIOBEN: IO port B clock enable
.equ  RCC_AHBENR_GPIOBEN_N      , 18
.equ  RCC_AHBENR_GPIOCEN        , 1<<19 @ Bit 19 GPIOCEN: IO port C clock enable
.equ  RCC_AHBENR_GPIOCEN_N      , 19
.equ  RCC_AHBENR_GPIODEN        , 1<<20 @ Bit 20 GPIODEN: IO port D clock enable
.equ  RCC_AHBENR_GPIODEN_N      , 20
.equ  RCC_AHBENR_GPIOEEN        , 1<<21 @ Bit 21 GPIOEEN: IO port E clock enable
.equ  RCC_AHBENR_GPIOEEN_N      , 21
.equ  RCC_AHBENR_GPIOFEN_N      , 1<<22 @ Bit 22 GPIOFEN: IO port F clock enable
.equ  RCC_AHBENR_GPIOFEN        , 22
.equ  RCC_AHBENR_GPIOGEN_N      , 1<<23 @ Bit 23 GPIOGEN: IO port G clock enable
.equ  RCC_AHBENR_GPIOGEN        , 23
.equ  RCC_AHBENR_TSCEN_N        , 24   @ Bit 24 TSCEN: Touch sensing controller clock enable
.equ  RCC_AHBENR_TSCEN          , 1<<24
.equ  RCC_AHBENR_ADC12EN_N      , 28   @ Bit 28 ADC12EN: ADC1 and ADC2 enable
.equ  RCC_AHBENR_ADC12EN        , 1<<28
.equ  RCC_AHBENR_ADC34EN_N      , 29   @ Bit 29 ADC34EN: ADC3 and ADC4 enable (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.equ  RCC_AHBENR_ADC34EN        , 1<<29
@.end

@.item RCC_APB2ENR
.equ  RCC_APB2ENR_SYSCFGEN_N   , 0    @ Bit 0 SYSCFGEN: SYSCFG clock enable
.equ  RCC_APB2ENR_TIM1EN_N     , 11   @ Bit 11 TIM1EN: TIM1 timer clock enable
.equ  RCC_APB2ENR_SPI1EN_N     , 12   @ Bit 12 SPI1EN: SPI1 clock enable
.equ  RCC_APB2ENR_TIM8EN_N     , 13   @ Bit 13 TIM8EN: TIM8 timer clock enable (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.equ  RCC_APB2ENR_USART1EN_N   , 14   @ Bit 14 USART1EN: USART1 clock enable
.equ  RCC_APB2ENR_SPI4EN_N     , 15   @ Bit 15 SPI4EN: SPI4 clock enable (STM32F303xD/E and STM32F398xE only)
.equ  RCC_APB2ENR_TIM15EN_N    , 16   @ Bit 16 TIM15EN: TIM15 timer clock enable
.equ  RCC_APB2ENR_TIM16EN_N    , 17   @ Bit 17 TIM16EN: TIM16 timer clock enable
.equ  RCC_APB2ENR_TIM17EN_N    , 18   @ Bit 18 TIM17EN: TIM17 timer clock enable
.equ  RCC_APB2ENR_TIM20EN_N    , 20   @ Bit 20 TIM20EN: TIM20 timer clock enable (STM32F303xD/E and STM32F398xE only)
@.end

@.item RCC_APB1ENR
.equ  RCC_APB1ENR_TIM2EN_N       , 0 @ Bit 0 TIM2EN: TIM2 clock enable
.equ  RCC_APB1ENR_TIM2EN         ,0x00000001
.equ  RCC_APB1ENR_TIM3EN_N       , 1 @ Bit 1 TIM3EN: TIM3 clock enable
.equ  RCC_APB1ENR_TIM3EN         ,0x00000002
.equ  RCC_APB1ENR_TIM4EN_N       , 2 @ Bit 2 TIM4EN: TIM4 clock enable
.equ  RCC_APB1ENR_TIM4EN         ,0x00000004
.equ  RCC_APB1ENR_TIM6EN_N       , 4 @ Bit 4 TIM6EN: TIM6 clock enable
.equ  RCC_APB1ENR_TIM6EN         ,0x00000010
.equ  RCC_APB1ENR_TIM7EN_N       , 5 @ Bit 5 TIM7EN: TIM7 clock enable
.equ  RCC_APB1ENR_TIM7EN         ,0x00000020
.equ  RCC_APB1ENR_WWDGEN_N       , 11 @ Bit 11 WWDGEN: Window watchdog clock enable
.equ  RCC_APB1ENR_WWDGEN         ,0x00000800
.equ  RCC_APB1ENR_SPI2EN_N       , 14 @ Bit 14 SPI2EN: SPI2 clock enable
.equ  RCC_APB1ENR_SPI2EN         ,0x00004000
.equ  RCC_APB1ENR_SPI3EN_N       , 15 @ Bit 15 SPI3EN: SPI3 clock enable
.equ  RCC_APB1ENR_SPI3EN         ,0x00008000
.equ  RCC_APB1ENR_USART2EN_N     , 17 @ Bit 17 USART2EN: USART2 clock enable
.equ  RCC_APB1ENR_USART2EN       ,0x00020000
.equ  RCC_APB1ENR_USART3EN_N     , 18 @ Bit 18 USART3EN: USART3 clock enable
.equ  RCC_APB1ENR_USART3EN       ,0x00040000
.equ  RCC_APB1ENR_UART4EN_N      , 19 @ Bit 19 UART4EN: UART4 clock enable       
.equ  RCC_APB1ENR_UART4EN        ,0x00080000
.equ  RCC_APB1ENR_UART5EN_N      , 20 @ Bit 20 UART5EN: UART5 clock enable
.equ  RCC_APB1ENR_UART5EN        ,0x00100000
.equ  RCC_APB1ENR_I2C1EN_N       , 21 @ Bit 21 I2C1EN: I2C1 clock enable
.equ  RCC_APB1ENR_I2C1EN         ,0x00200000
.equ  RCC_APB1ENR_I2C2EN_N       , 22 @ Bit 22 I2C2EN: I2C2 clock enable
.equ  RCC_APB1ENR_I2C2EN         ,0x00400000
.equ  RCC_APB1ENR_USBEN_N        , 23 @ Bit 23 USBEN: USB clock enable
.equ  RCC_APB1ENR_USBEN          ,0x00800000
.equ  RCC_APB1ENR_CANEN_N        , 25 @ Bit 25 CANEN: CAN 1 clock enable
.equ  RCC_APB1ENR_CANEN          ,0x02000000
.equ  RCC_APB1ENR_DAC2EN_N       , 26 @ Bit 26 DAC2EN: DAC 2 clock enable
.equ  RCC_APB1ENR_DAC2EN         ,0x04000000
.equ  RCC_APB1ENR_PWREN_N        , 28 @ Bit 28 PWREN: PWR clock enable
.equ  RCC_APB1ENR_PWREN          ,0x10000000
.equ  RCC_APB1ENR_DAC1EN_N        , 29 @ Bit 29 DAC1EN: DAC1 interface clock enable
.equ  RCC_APB1ENR_DAC1EN          ,0x20000000
.equ  RCC_APB1ENR_I2C3EN_N       , 30 @ Bit 30 I2C3EN: I2C3 clock enable
.equ  RCC_APB1ENR_I2C3EN         , 1<<30
@.end

@.item RCC_BDCR
.equ  RCC_BDCR_LSEON_N           , 0 @ Bit 0 LSEON: External low-speed oscillator enable
.equ  RCC_BDCR_LSEON             ,0x00000001
.equ  RCC_BDCR_LSERDY_N          , 1 @ Bit 1 LSERDY: External low-speed oscillator ready
.equ  RCC_BDCR_LSERDY            ,0x00000002
.equ  RCC_BDCR_LSEBYP_N          , 2 @ Bit 2 LSEBYP: External low-speed oscillator bypass
.equ  RCC_BDCR_LSEBYP            , 1<<2
.equ  RCC_BDCR_LSEDRV_N          , 3     @ Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
.equ  RCC_BDCR_LSEDRV_0          , 0<<3  @ ‘Xtal mode’ lower driving capability
.equ  RCC_BDCR_LSEDRV_1          , 1<<3  @ ‘Xtal mode’ medium high driving capability
.equ  RCC_BDCR_LSEDRV_2          , 2<<3  @ ‘Xtal mode’ medium low driving capability
.equ  RCC_BDCR_LSEDRV_3          , 3<<3  @ ‘Xtal mode’ higher driving capability (reset value)
.equ  RCC_BDCR_RTCSEL_N          , 8     @ Bits 9:8 RTCSEL[1:0]: RTC clock source selection
.equ  RCC_BDCR_RTCSEL_NO_CLOCK   , 0x00<<8 @ Bits 9:8 RTCSEL[1:0]: RTC clock source selection
.equ  RCC_BDCR_RTCSEL_LSE        , 0x01<<8
.equ  RCC_BDCR_RTCSEL_LSI        , 0x02<<8
.equ  RCC_BDCR_RTCSEL_HSE        , 0x03<<8
.equ  RCC_BDCR_RTCEN_N           , 15 @ Bit 15 RTCEN: RTC clock enable
.equ  RCC_BDCR_RTCEN             ,0x00008000
.equ  RCC_BDCR_BDRST_N           ,16 @ Bit 16 BDRST: Backup domain software reset
.equ  RCC_BDCR_BDRST             ,0x00010000
@.end

@.item RCC_CSR
.equ  RCC_CSR_LSION_N            , 0 @ Bit 0 LSION: Internal low-speed oscillator enable
.equ  RCC_CSR_LSION              ,0x00000001
.equ  RCC_CSR_LSIRDY_N           , 1 @ Bit 1 LSIRDY: Internal low-speed oscillator ready
.equ  RCC_CSR_LSIRDY             ,0x00000002
.equ  RCC_CSR_V18PWRRSTF_N       , 23 @ Bit 23 V18PWRRSTF: Reset flag of the 1.8 V domain.
.equ  RCC_CSR_V18PWRRSTF         , 1<<23
.equ  RCC_CSR_RMVF_N             , 24 @ Bit 24 RMVF: Remove reset flag
.equ  RCC_CSR_RMVF               ,0x01000000
.equ  RCC_CSR_OBLRSTF_N          , 25 @ Bit 25 OBLRSTF: Option byte loader reset flag
.equ  RCC_CSR_OBLRSTF            ,0x02000000
.equ  RCC_CSR_PINRSTF_N          , 26 @ Bit 26 PINRSTF: PIN reset flag
.equ  RCC_CSR_PINRSTF            ,0x04000000
.equ  RCC_CSR_PORRSTF_N          , 27 @ Bit 27 PORRSTF: POR/PDR reset flag
.equ  RCC_CSR_PORRSTF            ,0x08000000
.equ  RCC_CSR_SFTRSTF_N          , 28 @ Bit 28 SFTRSTF: Software reset flag
.equ  RCC_CSR_SFTRSTF            ,0x10000000
.equ  RCC_CSR_IWDGRSTF_N         , 29 @ Bit 29 IWDGRSTF: Independent watchdog reset flag
.equ  RCC_CSR_IWDGRSTF           ,0x20000000
.equ  RCC_CSR_WWDGRSTF_N         , 30 @ Bit 30 WWDGRSTF: Window watchdog reset flag
.equ  RCC_CSR_WWDGRSTF           ,0x40000000
.equ  RCC_CSR_LPWRRSTF_N         , 31 @Bit 31 LPWRRSTF: Low-power reset flag
.equ  RCC_CSR_LPWRRSTF           ,0x80000000
@.end

@.item RCC_AHBRSTR
.equ  RCC_AHBRSTR_FMCRST_N        , 5  @ Bit 5 FMCRST: FMC reset (Only on STM32F303xDxE).
.equ  RCC_AHBRSTR_FMCRST          , 1<<5
.equ  RCC_AHBRSTR_GPIOHRST_N      , 16 @ Bit 16 IOPHRST: I/O port H reset (Only on STM32F303xDxE).
.equ  RCC_AHBRSTR_GPIOHRST        , 1<<16
.equ  RCC_AHBRSTR_GPIOARST        , 1<<17 @ Bit 17 IOPARST: I/O port A reset
.equ  RCC_AHBRSTR_GPIOARST_N      , 17
.equ  RCC_AHBRSTR_GPIOBRST        , 1<<18 @ Bit 18 IOPBRST: I/O port B reset
.equ  RCC_AHBRSTR_GPIOBRST_N      , 18
.equ  RCC_AHBRSTR_GPIOCRST        , 1<<19 @ Bit 19 IOPCRST: I/O port C reset
.equ  RCC_AHBRSTR_GPIOCRST_N      , 19
.equ  RCC_AHBRSTR_GPIODRST        , 1<<20 @ Bit 20 IOPDRST: I/O port D reset
.equ  RCC_AHBRSTR_GPIODRST_N      , 20
.equ  RCC_AHBRSTR_GPIOERST        , 1<<21 @ Bit 21 OPERST: I/O port E reset
.equ  RCC_AHBRSTR_GPIOERST_N      , 21
.equ  RCC_AHBRSTR_GPIOFRST_N      , 1<<22 @ Bit 22 IOPFRST: I/O port F reset
.equ  RCC_AHBRSTR_GPIOFRST        , 22
.equ  RCC_AHBRSTR_GPIOGRST_N      , 1<<23 @ Bit 23 IOPGRST: I/O port G reset. (Only on STM32F303xDxE)
.equ  RCC_AHBRSTR_GPIOGRST        , 23
.equ  RCC_AHBRSTR_TSCRST_N        , 24   @ Bit 24 TSCRST: Touch sensing controller reset
.equ  RCC_AHBRSTR_TSCRST          , 1<<24
.equ  RCC_AHBRSTR_ADC12RST_N      , 28   @ Bit 28 ADC12RST: ADC1 and ADC2 reset
.equ  RCC_AHBRSTR_ADC12RST        , 1<<28
.equ  RCC_AHBRSTR_ADC34RST_N      , 29   @ Bit 29 ADC34RST: ADC3 and ADC4 reset (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.equ  RCC_AHBRSTR_ADC34RST        , 1<<29
@.end

@.item RCC_CFGR2
.EQU RCC_CFGR2_PREDIV_N           , 0         @ Bits 3:0 PREDIV: PREDIV division factor
.EQU RCC_CFGR2_PREDIV_1           , 0         @ HSE input to PLL not divided
.EQU RCC_CFGR2_PREDIV_2           , 1         @ HSE input to PLL divided by 2
.EQU RCC_CFGR2_PREDIV_3           , 2         @ HSE input to PLL divided by 3
.EQU RCC_CFGR2_PREDIV_4           , 3         @ HSE input to PLL divided by 4
.EQU RCC_CFGR2_PREDIV_5           , 4         @ HSE input to PLL divided by 5
.EQU RCC_CFGR2_PREDIV_6           , 5         @ HSE input to PLL divided by 6
.EQU RCC_CFGR2_PREDIV_7           , 6         @ HSE input to PLL divided by 7
.EQU RCC_CFGR2_PREDIV_8           , 7         @ HSE input to PLL divided by 8
.EQU RCC_CFGR2_PREDIV_9           , 8         @ HSE input to PLL divided by 9
.EQU RCC_CFGR2_PREDIV_10          , 9         @ HSE input to PLL divided by 10
.EQU RCC_CFGR2_PREDIV_11          , 10        @ HSE input to PLL divided by 11
.EQU RCC_CFGR2_PREDIV_12          , 11        @ HSE input to PLL divided by 12
.EQU RCC_CFGR2_PREDIV_13          , 12        @ HSE input to PLL divided by 13
.EQU RCC_CFGR2_PREDIV_14          , 13        @ HSE input to PLL divided by 14
.EQU RCC_CFGR2_PREDIV_15          , 14        @ HSE input to PLL divided by 15
.EQU RCC_CFGR2_PREDIV_16          , 15        @ HSE input to PLL divided by 16
.EQU RCC_CFGR2_ADC12PRES_N        , 4         @ Bits 8:4 ADC12PRES: ADC12 prescaler
.EQU RCC_CFGR2_ADC34PRES_N        , 9         @ Bits 13:9 ADC34PRES: ADC34 prescaler (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE only)
.EQU RCC_CFGR2_ADCxxPRES_1        , 0B10000   @ PLL clock divided by 1
.EQU RCC_CFGR2_ADCxxPRES_2        , 0B10001   @ PLL clock divided by 2
.EQU RCC_CFGR2_ADCxxPRES_4        , 0B10010   @ PLL clock divided by 4
.EQU RCC_CFGR2_ADCxxPRES_6        , 0B10011   @ PLL clock divided by 6
.EQU RCC_CFGR2_ADCxxPRES_8        , 0B10100   @ PLL clock divided by 8
.EQU RCC_CFGR2_ADCxxPRES_10       , 0B10101   @ PLL clock divided by 10
.EQU RCC_CFGR2_ADCxxPRES_12       , 0B10110   @ PLL clock divided by 12
.EQU RCC_CFGR2_ADCxxPRES_16       , 0B10111   @ PLL clock divided by 16
.EQU RCC_CFGR2_ADCxxPRES_32       , 0B11000   @ PLL clock divided by 32
.EQU RCC_CFGR2_ADCxxPRES_64       , 0B11001   @ PLL clock divided by 64
.EQU RCC_CFGR2_ADCxxPRES_128      , 0B11010   @ PLL clock divided by 128
.EQU RCC_CFGR2_ADCxxPRES_256      , 0B11011   @ PLL clock divided by 256
@.END

@.item RCC_CFGR3
.EQU RCC_CFGR3_USART1SW_N           , 0         @ Bits 3:0 PREDIV: PREDIV division factor
.EQU RCC_CFGR3_I2C1SW_N             , 4         @ Bit 4 I2C1SW: I2C1 clock source selection
.EQU RCC_CFGR3_I2C2SW_N             , 5         @ Bit 5 I2C2SW: I2C2 clock source selection (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.EQU RCC_CFGR3_I2C3SW_N             , 6         @ Bit 6 I2C3SW: I2C3 clock source selection (STM32F303xD/E devices only)
.EQU RCC_CFGR3_TIM1SW_N             , 8         @ Bit 8 TIM1SW: Timer1 clock source selection
.EQU RCC_CFGR3_TIM8SW_N             , 9         @ Bit 9 TIM8SW: Timer8 clock source selection (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE devices only)
.EQU RCC_CFGR3_TIM15SW_N            , 10        @ Bit 10 TIM15SW: Timer15 clock source selection
.EQU RCC_CFGR3_TIM16SW_N            , 11        @ Bit 11 TIM16SW: Timer16 clock source selection
.EQU RCC_CFGR3_TIM17SW_N            , 13        @ Bit 13 TIM17SW: Timer17 clock source selection
.EQU RCC_CFGR3_TIM20SW_N            , 15        @ Bit 15 TIM20SW: Timer20 clock source selection
.EQU RCC_CFGR3_USART2SW_N           , 16        @ Bits 17:16 USART2SW[1:0]: USART2 clock source selection
.EQU RCC_CFGR3_USART2SW_0           , 0<<16     @ PCLK selected as USART2 clock source (default)
.EQU RCC_CFGR3_USART2SW_1           , 1<<16     @ System clock (SYSCLK) selected as USART2 clock
.EQU RCC_CFGR3_USART2SW_2           , 2<<16     @ LSE clock selected as USART2 clock
.EQU RCC_CFGR3_USART2SW_3           , 3<<16     @ HSI clock selected as USART2 clock
.EQU RCC_CFGR3_USART3SW_N           , 18        @ Bits 19:18 USART3SW[1:0]: USART3 clock source selection
.EQU RCC_CFGR3_USART3SW_0           , 0<<18     @ PCLK selected as USART3 clock source (default)
.EQU RCC_CFGR3_USART3SW_1           , 1<<18     @ System clock (SYSCLK) selected as USART3 clock
.EQU RCC_CFGR3_USART3SW_2           , 2<<18     @ LSE clock selected as USART3 clock
.EQU RCC_CFGR3_USART3SW_3           , 3<<18     @ HSI clock selected as USART3 clock
.EQU RCC_CFGR3_USART4SW_N           , 20        @ Bits 21:20 USART4SW[1:0]: USART4 clock source selection
.EQU RCC_CFGR3_USART4SW_0           , 0<<18     @ PCLK selected as USART4 clock source (default)
.EQU RCC_CFGR3_USART4SW_1           , 1<<18     @ System clock (SYSCLK) selected as USART4 clock
.EQU RCC_CFGR3_USART4SW_2           , 2<<18     @ LSE clock selected as USART4 clock
.EQU RCC_CFGR3_USART4SW_3           , 3<<18     @ HSI clock selected as USART4 clock
.EQU RCC_CFGR3_USART5SW_N           , 22        @ Bits 23:22 USART5SW[1:0]: USART5 clock source selection
.EQU RCC_CFGR3_USART5SW_0           , 0<<18     @ PCLK selected as USART5 clock source (default)
.EQU RCC_CFGR3_USART5SW_1           , 1<<18     @ System clock (SYSCLK) selected as USART5 clock
.EQU RCC_CFGR3_USART5SW_2           , 2<<18     @ LSE clock selected as USART5 clock
.EQU RCC_CFGR3_USART5SW_3           , 3<<18     @ HSI clock selected as USART5 clock
.EQU RCC_CFGR3_TIM2SW_N             , 24        @ Bit 24 TIM2SW: Timer2 clock source selection
.EQU RCC_CFGR3_TIM34SW_N            , 25        @ Bit 25 TIM34SW: Timer34 clock source selection
@.END


