@GNU AS
@.CHARSET =CP1251 ( Cyrillic )
@.DESC     type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы RCC                        |
@ |               для STM32F401xB/C и STM32F401xD/E                  |
@ +------------------------------------------------------------------+
@.ENDDESC


.INCLUDE       "/src/inc/base.inc"

@.ITEM     AHB1PERIPH_BASE
.EQU  RCC_BASE      , AHB1PERIPH_BASE + 0x3800    @ Базовый адрес RCC
@.END

@.ITEM     RCC_BASE
.EQU  RCC_CR        , 0x00       @ RCC clock control register
.EQU  RCC_PLLCFGR   , 0x04       @ RCC PLL configuration register
.EQU  RCC_CFGR      , 0x08       @ RCC clock configuration register
.EQU  RCC_CIR       , 0x0C       @ RCC clock interrupt register
.EQU  RCC_AHB1RSTR  , 0x10       @ RCC AHB1 peripheral reset register
.EQU  RCC_AHB2RSTR  , 0x14       @ RCC AHB2 peripheral reset register
.EQU  RCC_APB1RSTR  , 0x20       @ RCC APB1 peripheral reset register
.EQU  RCC_APB2RSTR  , 0x24       @ RCC APB2 peripheral reset register
.EQU  RCC_AHB1ENR   , 0x30       @ RCC AHB1 peripheral clock register
.EQU  RCC_AHB2ENR   , 0x34       @ RCC AHB2 peripheral clock enable register
.EQU  RCC_APB1ENR   , 0x40       @ RCC APB1 peripheral clock enable register
.EQU  RCC_APB2ENR   , 0x44       @ RCC APB1 peripheral clock enable register
.EQU  RCC_AHB1LPENR , 0x50       @ RCC AHB1 peripheral clock enable in low power mode register
.EQU  RCC_AHB2LPENR , 0x54       @ RCC AHB2 peripheral clock enable in low power mode register
.EQU  RCC_APB1LPENR , 0x60       @ RCC APB1 peripheral clock enable in low power mode register
.EQU  RCC_APB2LPENR , 0x64       @ RCC APB2 peripheral clock enabled in low power mode register
.EQU  RCC_BDCR      , 0x70       @ RCC Backup domain control register
.EQU  RCC_CSR       , 0x74       @ RCC clock control & status register
.EQU  RCC_SSCGR     , 0x80       @ RCC spread spectrum clock generation register
.EQU  RCC_PLLI2SCFGR, 0x84       @ RCC PLLI2S configuration register
.EQU  RCC_DCKCFGR   , 0x8C       @ RCC Dedicated Clock Configuration Register
@.END

@.ITEM     RCC_CR
.EQU  RCC_CR_HSION_N, 0          @ Bit 0 HSION: Internal high-speed clock enable
                                 @ Set and cleared by software.
                                 @ Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in
                                 @ case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit
                                 @ cannot be cleared if the HSI is used directly or indirectly as the system clock.
                                 @ 0: HSI oscillator OFF
.EQU  RCC_CR_HSION  , 1          @ 1: HSI oscillator ON
.EQU  RCC_CR_HSIRDY_N, 1         @ Bit 1 HSIRDY: Internal high-speed clock ready flag
                                 @ Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,
                                 @ HSIRDY goes low after 6 HSI clock cycles.
                                 @ 0: HSI oscillator not ready
.EQU  RCC_CR_HSIRDY , 1<<1       @ 1: HSI oscillator ready
.EQU  RCC_CR_HSITRIM_N, 3        @ Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
                                 @ These bits provide an additional user-programmable trimming value that is added to the
                                 @ HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
                                 @ that influence the frequency of the internal HSI RC.
.EQU  RCC_CR_HSICAL_N, 8         @ Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
                                 @ These bits are initialized automatically at startup.
.EQU  RCC_CR_HSEON_N, 16         @ Bit 16 HSEON: HSE clock enable
                                 @ Set and cleared by software.
                                 @ Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
                                 @ bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
                                 @ 0: HSE oscillator OFF
.EQU  RCC_CR_HSEON  , 1<<16      @ 1: HSE oscillator ON
.EQU  RCC_CR_HSERDY_N, 17        @ Bit 17 HSERDY: HSE clock ready flag
                                 @ Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,
                                 @ HSERDY goes low after 6 HSE oscillator clock cycles.
                                 @ 0: HSE oscillator not ready
.EQU  RCC_CR_HSERDY , 1<<17      @ 1: HSE oscillator ready
.EQU  RCC_CR_HSEBYP_N, 18        @ Bit 18 HSEBYP: HSE clock bypass
                                 @ Set and cleared by software to bypass the oscillator with an external clock. The external
                                 @ clock must be enabled with the HSEON bit, to be used by the device.
                                 @ The HSEBYP bit can be written only if the HSE oscillator is disabled.
                                 @ 0: HSE oscillator not bypassed
.EQU  RCC_CR_HSEBYP , 1 << 18    @ 1: HSE oscillator bypassed with an external clock
.EQU  RCC_CR_CSSON_N, 19         @ Bit 19 CSSON: Clock security system enable
                                 @ Set and cleared by software to enable the clock security system. When CSSON is set, the
                                 @ clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
                                 @ hardware if an oscillator failure is detected.
                                 @ 0: Clock security system OFF (Clock detector OFF)
.EQU  RCC_CR_CSSON  , 1 << 19    @ 1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)
.EQU  RCC_CR_PLLON_N, 24         @ Bit 24 PLLON: Main PLL (PLL) enable
                                 @ Set and cleared by software to enable PLL.
                                 @ Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL
                                 @ clock is used as the system clock.
                                 @ 0: PLL OFF
.EQU  RCC_CR_PLLON  , 1<<24      @ 1: PLL ON
.EQU  RCC_CR_PLLRDY_N, 25        @ Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
                                 @ Set by hardware to indicate that PLL is locked.
                                 @ 0: PLL unlocked
.EQU  RCC_CR_PLLRDY , 1<<25      @ 1: PLL locked
.EQU  RCC_CR_PLLI2SON_N, 26      @ Bit 26 PLLI2SON: PLLI2S enable
                                 @ Set and cleared by software to enable PLLI2S.
                                 @ Cleared by hardware when entering Stop or Standby mode.
                                 @ 0: PLLI2S OFF
.EQU  RCC_CR_PLLI2SON, 1 << 26   @ 1: PLLI2S ON
.EQU  RCC_CR_PLLI2SRDY_N, 27     @ Bit 27 PLLI2SRDY: PLLI2S clock ready flag
                                 @ Set by hardware to indicate that the PLLI2S is locked.
                                 @ 0: PLLI2S unlocked
.EQU  RCC_CR_PLLI2SRDY, 1<<27    @ 1: PLLI2S locked
@.END

@.ITEM     RCC_PLLCFGR
@ Access: no wait state, word, half-word and byte access.
@ This register is used to configure the PLL clock outputs according to the formulas:
@ • f(VCO clock) = f(PLL clock input) Ч (PLLN / PLLM)
@ • f(PLL general clock output) = f(VCO clock) / PLLP
@ • f(USB OTG FS, SDIO, RNG clock output) = f(VCO clock) / PLLQ
.EQU  RCC_PLLCFGR_RSTVAL, 0x24003010    @ Reset value: 0x2400 3010
.EQU  RCC_PLLCFGR_PLLM_N, 0      @ Bits 5:0 PLLM: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
                                 @ Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
                                 @ These bits can be written only when the PLL and PLLI2S are disabled.
                        @ Caution: The software has to set these bits correctly to ensure that the VCO input frequency
                                 @ ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit
                                 @ PLL jitter.
                                 @ VCO input frequency = PLL input clock frequency / PLLM with 2  PLLM  63
                                 @ 000000: PLLM = 0, wrong configuration
                                 @ 000001: PLLM = 1, wrong configuration
                                 @ 000010: PLLM = 2
                                 @ 000011: PLLM = 3
                                 @ 000100: PLLM = 4
                                 @ ...
                                 @ 111110: PLLM = 62
                                 @ 111111: PLLM = 63
.EQU  RCC_PLLCFGR_PLLN_N, 6      @ Bits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO
                                 @ Set and cleared by software to control the multiplication factor of the VCO. These bits can
                                 @ be written only when PLL is disabled. Only half-word and word accesses are allowed to
                                 @ write these bits.
                        @ Caution: The software has to set these bits correctly to ensure that the VCO output
                                 @ frequency is between 192 and 432 MHz. (check also Section 6.3.20: RCC PLLI2S
                                 @ configuration register (RCC_PLLI2SCFGR))
                                 @ VCO output frequency = VCO input frequency Ч PLLN with 192  PLLN  432
                                 @ 000000000: PLLN = 0, wrong configuration
                                 @ 000000001: PLLN = 1, wrong configuration
                                 @ ...
                                 @ ...
                                 @ 110110000: PLLN = 432
                                 @ 110110001: PLLN = 433, wrong configuration
                                 @ ...
                                 @ 111111111: PLLN = 511, wrong configuration
.EQU  RCC_PLLCFGR_PLLP_N, 16     @ Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock
                                 @ Set and cleared by software to control the frequency of the general PLL output clock. These
                                 @ bits can be written only if PLL is disabled.
                        @ Caution: The software has to set these bits correctly not to exceed 84 MHz on this domain.
                                 @ PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
.EQU  RCC_PLLCFGR_PLLP_2, 0      @ 00: PLLP = 2
.EQU  RCC_PLLCFGR_PLLP_4, 1 << 16    @ 01: PLLP = 4
.EQU  RCC_PLLCFGR_PLLP_6, 2 << 16    @ 10: PLLP = 6
.EQU  RCC_PLLCFGR_PLLP_8, 3 << 16    @ 11: PLLP = 8
.EQU  RCC_PLLCFGR_PLLSRC_N, 22   @ Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
                                 @ Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written
                                 @ only when PLL and PLLI2S are disabled.
.EQU  RCC_PLLCFGR_PLLSRC_HSI, 0     @ 0: HSI clock selected as PLL and PLLI2S clock entry
.EQU  RCC_PLLCFGR_PLLSRC_HSE, 1<<22 @ 1: HSE oscillator clock selected as PLL and PLLI2S clock entry
.EQU  RCC_PLLCFGR_PLLQ_N, 24     @ Bits 27:24 PLLQ: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator
                                 @ clocks
                                 @ Set and cleared by software to control the frequency of USB OTG FS clock, the random
                                 @ number generator clock and the SDIO clock. These bits should be written only if PLL is
                                 @ disabled.
                        @ Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIO and the
                                 @ random number generator need a frequency lower than or equal to 48 MHz to work
                                 @ correctly.
                                 @ USB OTG FS clock frequency = VCO frequency / PLLQ with 2  PLLQ  15
                                 @ 0000: PLLQ = 0, wrong configuration
                                 @ 0001: PLLQ = 1, wrong configuration
.EQU  RCC_PLLCFGR_PLLQ_2, 2 << 24    @ 0010: PLLQ = 2
.EQU  RCC_PLLCFGR_PLLQ_3, 3 << 24    @ 0011: PLLQ = 3
.EQU  RCC_PLLCFGR_PLLQ_4, 4 << 24    @ 0100: PLLQ = 4
.EQU  RCC_PLLCFGR_PLLQ_5, 5 << 24    @ ...
.EQU  RCC_PLLCFGR_PLLQ_6, 6 << 24    @ ...
.EQU  RCC_PLLCFGR_PLLQ_7, 7 << 24    @ ...
.EQU  RCC_PLLCFGR_PLLQ_8, 8 << 24    @ ...
.EQU  RCC_PLLCFGR_PLLQ_9, 9 << 24    @ ...
.EQU  RCC_PLLCFGR_PLLQ_10, 10 << 24  @ ...
.EQU  RCC_PLLCFGR_PLLQ_11, 11 << 24  @ ...
.EQU  RCC_PLLCFGR_PLLQ_12, 12 << 24  @ ...
.EQU  RCC_PLLCFGR_PLLQ_13, 13 << 24  @ ...
.EQU  RCC_PLLCFGR_PLLQ_14, 14 << 24  @ ...
.EQU  RCC_PLLCFGR_PLLQ_15, 15 << 24  @ 1111: PLLQ = 15
@.END

@.ITEM     RCC_CFGR
@ Access: 0  wait state   2, word, half-word and byte access
@ 1 or 2 wait states inserted only if the access occurs during a clock source switch.
.EQU  RCC_CFGR_SWS_N, 2          @ Bits 1:0 SW: System clock switch
                                 @ Set and cleared by software to select the system clock source.
                                 @ Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in
                                 @ case of failure of the HSE oscillator used directly or indirectly as the system clock.
.EQU  RCC_CFGR_SW_HSI, 0         @ 00: HSI oscillator selected as system clock
.EQU  RCC_CFGR_SW_HSE, 1         @ 01: HSE oscillator selected as system clock
.EQU  RCC_CFGR_SW_PLL, 2         @ 10: PLL selected as system clock
                                 @ 11: not allowed
.EQU  RCC_CFGR_SWS_N, 2          @ Bits 3:2 SWS: System clock switch status
                                 @ Set and cleared by hardware to indicate which clock source is used as the system clock.
.EQU  RCC_CFGR_SWS_HSI, 0        @ 00: HSI oscillator used as the system clock
.EQU  RCC_CFGR_SWS_HSE, 1 << 2   @ 01: HSE oscillator used as the system clock
.EQU  RCC_CFGR_SWS_PLL, 2 << 2   @ 10: PLL used as the system clock
                                 @ 11: not applicable
.EQU  RCC_CFGR_HPRE_N, 4         @ Bits 7:4 HPRE: AHB prescaler
                                 @ Set and cleared by software to control AHB clock division factor.
                        @ Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
                                 @ HPRE write.
.EQU  RCC_CFGR_HPRE_DIV1, 0            @ 0xxx: system clock not divided
.EQU  RCC_CFGR_HPRE_DIV2, 8 << 4       @ 1000: system clock divided by 2
.EQU  RCC_CFGR_HPRE_DIV4, 9 << 4       @ 1001: system clock divided by 4
.EQU  RCC_CFGR_HPRE_DIV8, 10 << 4      @ 1010: system clock divided by 8
.EQU  RCC_CFGR_HPRE_DIV16, 11 << 4     @ 1011: system clock divided by 16
.EQU  RCC_CFGR_HPRE_DIV64, 12 << 4     @ 1100: system clock divided by 64
.EQU  RCC_CFGR_HPRE_DIV128, 13 << 4    @ 1101: system clock divided by 128
.EQU  RCC_CFGR_HPRE_DIV256, 14 << 4    @ 1110: system clock divided by 256
.EQU  RCC_CFGR_HPRE_DIV512, 15 << 4    @ 1111: system clock divided by 512
.EQU  RCC_CFGR_PPRE1_N, 10       @ Bits 12:10 PPRE1: APB Low speed prescaler (APB1)
                                 @ Set and cleared by software to control APB low-speed clock division factor.
                                 @ Caution: The software has to set these bits correctly not to exceed 42 MHz on this domain.
                                 @ The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
                                 @ PPRE1 write.
.EQU  RCC_CFGR_PPRE1_DIV1, 0           @ 0xx: AHB clock not divided
.EQU  RCC_CFGR_PPRE1_DIV2, 4 << 10     @ 100: AHB clock divided by 2
.EQU  RCC_CFGR_PPRE1_DIV4, 5 << 10     @ 101: AHB clock divided by 4
.EQU  RCC_CFGR_PPRE1_DIV8, 6 << 10     @ 110: AHB clock divided by 8
.EQU  RCC_CFGR_PPRE1_DIV16, 7 << 10    @ 111: AHB clock divided by 16
.EQU  RCC_CFGR_PPRE2_N, 13       @ Bits 15:13 PPRE2: APB high-speed prescaler (APB2)
                                 @ Set and cleared by software to control APB high-speed clock division factor.
                                 @ Caution: The software has to set these bits correctly not to exceed 84 MHz on this domain.
                                 @ The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
                                 @ PPRE2 write.
.EQU  RCC_CFGR_PPRE2_DIV1, 0           @ 0xx: AHB clock not divided
.EQU  RCC_CFGR_PPRE2_DIV2, 4 << 13     @ 100: AHB clock divided by 2
.EQU  RCC_CFGR_PPRE2_DIV4, 5 << 13     @ 101: AHB clock divided by 4
.EQU  RCC_CFGR_PPRE2_DIV8, 6 << 13     @ 110: AHB clock divided by 8
.EQU  RCC_CFGR_PPRE2_DIV16, 7 << 13    @ 111: AHB clock divided by 16
.EQU  RCC_CFGR_RTCPRE_N, 16      @ Bits 20:16 RTCPRE: HSE division factor for RTC clock
                                 @ Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock
                                 @ for RTC.
                        @ Caution: The software has to set these bits correctly to ensure that the clock supplied to the
                                 @ RTC is 1 MHz. These bits must be configured if needed before selecting the RTC
                                 @ clock source.
                                 @ 00000: no clock
                                 @ 00001: no clock
                                 @ 00010: HSE/2
                                 @ 00011: HSE/3
                                 @ 00100: HSE/4
                                 @ ...
                                 @ 11110: HSE/30
                                 @ 11111: HSE/31
.EQU  RCC_CFGR_MCO1_N, 21        @ Bits 22:21 MCO1: Microcontroller clock output 1
                                 @ Set and cleared by software. Clock source selection may generate glitches on MCO1. It is
                                 @ highly recommended to configure these bits only after reset before enabling the external
                                 @ oscillators and PLL.
.EQU  RCC_CFGR_MCO1_HSI, 0       @ 00: HSI clock selected
.EQU  RCC_CFGR_MCO1_LSE, 1 << 21    @ 01: LSE oscillator selected
.EQU  RCC_CFGR_MCO1_HSE, 2 << 21    @ 10: HSE oscillator clock selected
.EQU  RCC_CFGR_MCO1_PLL, 3 << 21    @ 11: PLL clock selected
.EQU  RCC_CFGR_I2SSRC_N, 23      @ Bit 23 I2SSRC: I2S clock selection
                                 @ Set and cleared by software. This bit allows to select the I2S clock source between the
                                 @ PLLI2S clock and the external clock. It is highly recommended to change this bit only after
                                 @ reset and before enabling the I2S module.
                                 @ 0: PLLI2S clock used as I2S clock source
.EQU  RCC_CFGR_I2SSRC, 1 << 23   @ 1: External clock mapped on the I2S_CKIN pin used as I2S clock source
.EQU  RCC_CFGR_MCO1PRE_N, 24     @ Bits 26:24 MCO1PRE: MCO1 prescaler
                                 @ Set and cleared by software to configure the prescaler of the MCO1. Modification of this
                                 @ prescaler may generate glitches on MCO1. It is highly recommended to change this
                                 @ prescaler only after reset before enabling the external oscillators and the PLL.
.EQU  RCC_CFGR_MCO1PRE_DIV1, 0        @ 0xx: no division
.EQU  RCC_CFGR_MCO1PRE_DIV2, 4 << 24  @ 100: division by 2
.EQU  RCC_CFGR_MCO1PRE_DIV3, 5 << 24  @ 101: division by 3
.EQU  RCC_CFGR_MCO1PRE_DIV4, 6 << 24  @ 110: division by 4
.EQU  RCC_CFGR_MCO1PRE_DIV5, 7 << 24  @ 111: division by 5
.EQU  RCC_CFGR_MCO2PRE_N, 27     @ Bits 29:27 MCO2PRE: MCO2 prescaler
                                 @ Set and cleared by software to configure the prescaler of the MCO2. Modification of this
                                 @ prescaler may generate glitches on MCO2. It is highly recommended to change this
                                 @ prescaler only after reset before enabling the external oscillators and the PLLs.
.EQU  RCC_CFGR_MCO2PRE_DIV1, 0        @ 0xx: no division
.EQU  RCC_CFGR_MCO2PRE_DIV2, 4 << 27  @ 100: division by 2
.EQU  RCC_CFGR_MCO2PRE_DIV3, 5 << 27  @ 101: division by 3
.EQU  RCC_CFGR_MCO2PRE_DIV4, 6 << 27  @ 110: division by 4
.EQU  RCC_CFGR_MCO2PRE_DIV5, 7 << 27  @ 111: division by 5
.EQU  RCC_CFGR_MCO2_N, 30        @ Bits 31:30 MCO2[1:0]: Microcontroller clock output 2
                                 @ Set and cleared by software. Clock source selection may generate glitches on MCO2. It is
                                 @ highly recommended to configure these bits only after reset before enabling the external
                                 @ oscillators and the PLLs.
.EQU  RCC_CFGR_MCO2_SYSCLK, 0        @ 00: System clock (SYSCLK) selected
.EQU  RCC_CFGR_MCO2_PLLI2S, 1 << 30  @ 01: PLLI2S clock selected
.EQU  RCC_CFGR_MCO2_HSE, 2 << 30     @ 10: HSE oscillator clock selected
.EQU  RCC_CFGR_MCO2_PLL, 3 << 30     @ 11: PLL clock selected
@.END

@.ITEM     RCC_CIR
@ Access: no wait state, word, half-word and byte access
.EQU  RCC_CIR_LSIRDYF_N, 0       @ Bit 0 LSIRDYF: LSI ready interrupt flag
                                 @ Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
                                 @ Cleared by software setting the LSIRDYC bit.
                                 @ 0: No clock ready interrupt caused by the LSI oscillator
.EQU  RCC_CIR_LSIRDYF, 1         @ 1: Clock ready interrupt caused by the LSI oscillator
.EQU  RCC_CIR_LSERDYF_N, 1       @ Bit 1 LSERDYF: LSE ready interrupt flag
                                 @ Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
                                 @ set.
                                 @ Cleared by software setting the LSERDYC bit.
                                 @ 0: No clock ready interrupt caused by the LSE oscillator
.EQU  RCC_CIR_LSERDYF, 1 << 1    @ 1: Clock ready interrupt caused by the LSE oscillator
.EQU  RCC_CIR_HSIRDYF_N, 2       @ Bit 2 HSIRDYF: HSI ready interrupt flag
                                 @ Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
                                 @ set.
                                 @ Cleared by software setting the HSIRDYC bit.
                                 @ 0: No clock ready interrupt caused by the HSI oscillator
.EQU  RCC_CIR_HSIRDYF, 1 << 2    @ 1: Clock ready interrupt caused by the HSI oscillator
.EQU  RCC_CIR_HSERDYF_N, 3       @ Bit 3 HSERDYF: HSE ready interrupt flag
                                 @ Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.
                                 @ Cleared by software setting the HSERDYC bit.
                                 @ 0: No clock ready interrupt caused by the HSE oscillator
.EQU  RCC_CIR_HSERDYF, 1 << 3    @ 1: Clock ready interrupt caused by the HSE oscillator
.EQU  RCC_CIR_PLLRDYF_N, 4       @ Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
                                 @ Set by hardware when PLL locks and PLLRDYDIE is set.
                                 @ Cleared by software setting the PLLRDYC bit.
                                 @ 0: No clock ready interrupt caused by PLL lock
.EQU  RCC_CIR_PLLRDYF, 1 << 4    @ 1: Clock ready interrupt caused by PLL lock
.EQU  RCC_CIR_PLLI2SRDYF_N, 5    @ Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag
                                 @ Set by hardware when the PLLI2S locks and PLLI2SRDYDIE is set.
                                 @ Cleared by software setting the PLLRI2SDYC bit.
                                    @ 0: No clock ready interrupt caused by PLLI2S lock
.EQU  RCC_CIR_PLLI2SRDYF, 1 << 5    @ 1: Clock ready interrupt caused by PLLI2S lock
.EQU  RCC_CIR_CSSF_N, 7          @ Bit 7 CSSF: Clock security system interrupt flag
                                 @ Set by hardware when a failure is detected in the HSE oscillator.
                                 @ Cleared by software setting the CSSC bit.
                                 @ 0: No clock security interrupt caused by HSE clock failure
.EQU  RCC_CIR_CSSF  , 1 << 7     @ 1: Clock security interrupt caused by HSE clock failure
.EQU  RCC_CIR_LSIRDYIE_N, 8      @ Bit 8 LSIRDYIE: LSI ready interrupt enable
                                 @ Set and cleared by software to enable/disable interrupt caused by LSI oscillator
                                 @ stabilization.
                                  @ 0: LSI ready interrupt disabled
.EQU  RCC_CIR_LSIRDYIE, 1 << 8    @ 1: LSI ready interrupt enabled
.EQU  RCC_CIR_LSERDYIE_N, 9      @ Bit 9 LSERDYIE: LSE ready interrupt enable
                                 @ Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
                                 @ stabilization.
                                  @ 0: LSE ready interrupt disabled
.EQU  RCC_CIR_LSERDYIE, 1 << 9    @ 1: LSE ready interrupt enabled
.EQU  RCC_CIR_HSIRDYIE_N, 10     @ Bit 10 HSIRDYIE: HSI ready interrupt enable
                                 @ Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
                                 @ stabilization.
                                   @ 0: HSI ready interrupt disabled
.EQU  RCC_CIR_HSIRDYIE, 1 << 10    @ 1: HSI ready interrupt enabled
.EQU  RCC_CIR_HSERDYIE_N, 11     @ Bit 11 HSERDYIE: HSE ready interrupt enable
                                 @ Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
                                 @ stabilization.
                                   @ 0: HSE ready interrupt disabled
.EQU  RCC_CIR_HSERDYIE, 1 << 11    @ 1: HSE ready interrupt enabled
.EQU  RCC_CIR_PLLRDYIE_N, 12     @ Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
                                 @ Set and cleared by software to enable/disable interrupt caused by PLL lock.
                                   @ 0: PLL lock interrupt disabled
.EQU  RCC_CIR_PLLRDYIE, 1 << 12    @ 1: PLL lock interrupt enabled
.EQU  RCC_CIR_PLLI2SRDYIE_N, 13    @ Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable
                                   @ Set and cleared by software to enable/disable interrupt caused by PLLI2S lock.
                                      @ 0: PLLI2S lock interrupt disabled
.EQU  RCC_CIR_PLLI2SRDYIE, 1 << 13    @ 1: PLLI2S lock interrupt enabled
.EQU  RCC_CIR_LSIRDYC_N, 16      @ Bit 16 LSIRDYC: LSI ready interrupt clear
                                 @ This bit is set by software to clear the LSIRDYF flag.
                                  @ 0: No effect
.EQU  RCC_CIR_LSIRDYC, 1 << 16    @ 1: LSIRDYF cleared
.EQU  RCC_CIR_LSERDYC_N, 17      @ Bit 17 LSERDYC: LSE ready interrupt clear
                                 @ This bit is set by software to clear the LSERDYF flag.
                                  @ 0: No effect
.EQU  RCC_CIR_LSERDYC, 1 << 17    @ 1: LSERDYF cleared
.EQU  RCC_CIR_HSIRDYC_N, 18      @ Bit 18 HSIRDYC: HSI ready interrupt clear
                                 @ This bit is set software to clear the HSIRDYF flag.
                                  @ 0: No effect
.EQU  RCC_CIR_HSIRDYC, 1 << 18    @ 1: HSIRDYF cleared
.EQU  RCC_CIR_HSERDYC_N, 19      @ Bit 19 HSERDYC: HSE ready interrupt clear
                                 @ This bit is set by software to clear the HSERDYF flag.
                                  @ 0: No effect
.EQU  RCC_CIR_HSERDYC, 1 << 19    @ 1: HSERDYF cleared
.EQU  RCC_CIR_PLLRDYC_N, 20      @ Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
                                 @ This bit is set by software to clear the PLLRDYF flag.
                                  @ 0: No effect
.EQU  RCC_CIR_PLLRDYC, 1 << 20    @ 1: PLLRDYF cleared
.EQU  RCC_CIR_PLLI2SRDYC_N, 21    @ Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
                                  @ This bit is set by software to clear the PLLI2SRDYF flag.
                                     @ 0: No effect
.EQU  RCC_CIR_PLLI2SRDYC, 1 << 21    @ 1: PLLI2SRDYF cleared
.EQU  RCC_CIR_CSSC_N, 23         @ Bit 23 CSSC: Clock security system interrupt clear
                                 @ This bit is set by software to clear the CSSF flag.
                                 @ 0: No effect
.EQU  RCC_CIR_CSSC  , 1<<23      @ 1: Clear CSSF flag
@.END

@.ITEM     RCC_AHB1RSTR
.EQU  RCC_AHB1RSTR_GPIOARST_N, 0       @ Bit 0 GPIOARST: IO port A reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset IO port A
.EQU  RCC_AHB1RSTR_GPIOARST, 1         @ 1: resets IO port A
.EQU  RCC_AHB1RSTR_GPIOBRST_N, 1       @ Bit 1 GPIOBRST: IO port B reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset IO port B
.EQU  RCC_AHB1RSTR_GPIOBRST, 1 << 1    @ 1:resets IO port B
.EQU  RCC_AHB1RSTR_GPIOCRST_N, 2       @ Bit 2 GPIOCRST: IO port C reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset IO port C
.EQU  RCC_AHB1RSTR_GPIOCRST, 1 << 2    @ 1: resets IO port C
.EQU  RCC_AHB1RSTR_GPIODRST_N, 3       @ Bit 3 GPIODRST: IO port D reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset IO port D
.EQU  RCC_AHB1RSTR_GPIODRST, 1 << 3    @ 1: resets IO port D
.EQU  RCC_AHB1RSTR_GPIOERST_N, 4       @ Bit 4 GPIOERST: IO port E reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset IO port E
.EQU  RCC_AHB1RSTR_GPIOERST, 1 << 4    @ 1: resets IO port E
.EQU  RCC_AHB1RSTR_GPIOHRST_N, 7       @ Bit 7 GPIOHRST: IO port H reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset IO port H
.EQU  RCC_AHB1RSTR_GPIOHRST, 1 << 7    @ 1: resets IO port H
.EQU  RCC_AHB1RSTR_CRCRST_N, 12       @ Bit 12 CRCRST: CRC reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset CRC
.EQU  RCC_AHB1RSTR_CRCRST, 1 << 12    @ 1: resets CRC
.EQU  RCC_AHB1RSTR_DMA1RST_N, 21       @ Bit 21 DMA1RST: DMA1 reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset DMA1
.EQU  RCC_AHB1RSTR_DMA1RST, 1<<21      @ 1: resets DMA1
.EQU  RCC_AHB1RSTR_DMA2RST_N, 22       @ Bit 22 DMA2RST: DMA2 reset
                                       @ Set and cleared by software.
                                       @ 0: does not reset DMA2
.EQU  RCC_AHB1RSTR_DMA2RST, 1 << 22    @ 1: resets DMA2
@.END

@.ITEM     RCC_AHB2RSTR
.EQU  RCC_AHB2RSTR_OTGFSRST_N, 7
.EQU  RCC_AHB2RSTR_OTGFSRST, 1<<7
@.END

@.ITEM     RCC_APB1RSTR
.EQU  RCC_APB1RSTR_TIM2RST_N, 0       @ Bit 0 TIM2RST: TIM2 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset TIM2
.EQU  RCC_APB1RSTR_TIM2RST, 1         @ 1: resets TIM2
.EQU  RCC_APB1RSTR_TIM3RST_N, 1       @ Bit 1 TIM3RST: TIM3 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset TIM3
.EQU  RCC_APB1RSTR_TIM3RST, 1 << 1    @ 1: resets TIM3
.EQU  RCC_APB1RSTR_TIM4RST_N, 2       @ Bit 2 TIM4RST: TIM4 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset TIM4
.EQU  RCC_APB1RSTR_TIM4RST, 1 << 2    @ 1: resets TIM4
.EQU  RCC_APB1RSTR_TIM5RST_N, 3       @ Bit 3 TIM5RST: TIM5 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset TIM5
.EQU  RCC_APB1RSTR_TIM5RST, 1 << 3    @ 1: resets TIM5
.EQU  RCC_APB1RSTR_WWDGEN_N, 11       @ Bit 11 WWDGRST: Window watchdog reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset the window watchdog
.EQU  RCC_APB1RSTR_WWDGEN, 1 << 11    @ 1: resets the window watchdog
.EQU  RCC_APB1RSTR_SPI2RST_N, 14      @ Bit 14 SPI2RST: SPI2 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset SPI2
.EQU  RCC_APB1RSTR_SPI2RST, 1 << 14   @ 1: resets SPI2
.EQU  RCC_APB1RSTR_SPI3RST_N, 15      @ Bit 15 SPI3RST: SPI3 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset SPI3
.EQU  RCC_APB1RSTR_SPI3RST, 1<<15     @ 1: resets SPI3
.EQU  RCC_APB1RSTR_USART2RST_N, 17    @ Bit 17 USART2RST: USART2 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset USART2
.EQU  RCC_APB1RSTR_USART2RST, 1<<17   @ 1: resets USART2
.EQU  RCC_APB1RSTR_I2C1RST_N, 21      @ Bit 21 I2C1RST: I2C1 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset I2C1
.EQU  RCC_APB1RSTR_I2C1RST, 1 << 21   @ 1: resets I2C1
.EQU  RCC_APB1RSTR_I2C2RST_N, 22      @ Bit 22  I2C2RST: I2C2 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset I2C2
.EQU  RCC_APB1RSTR_I2C2RST, 1<<22     @ 1: resets I2C2
.EQU  RCC_APB1RSTR_I2C3RST_N, 23      @ Bit 23  I2C3RST: I2C3 reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset I2C3
.EQU  RCC_APB1RSTR_I2C3RST, 1<<23     @ 1: resets I2C3
.EQU  RCC_APB1RSTR_PWRRST_N, 28       @ Bit 28 PWRRST: Power interface reset
                                      @ Set and cleared by software.
                                      @ 0: does not reset the power interface
.EQU  RCC_APB1RSTR_PWRRST, 1 << 28    @ 1: resets the power interface
@.END

@.ITEM     RCC_APB2RSTR
.EQU  RCC_APB2RSTR_TIM1RST_N, 0     @ Bit 0 TIM1RST: TIM1 reset
                                    @ Set and cleared by software.
                                        @ 0: does not reset TIM1
.EQU  RCC_APB2RSTR_TIM1RST, 1           @ 1: resets TIM1
.EQU  RCC_APB2RSTR_USART1RST_N, 4   @ Bit 4 USART1RST: USART1 reset
                                    @ Set and cleared by software.
                                        @ 0: does not reset USART1
.EQU  RCC_APB2RSTR_USART1RST, 1 << 4    @ 1: resets USART1
.EQU  RCC_APB2RSTR_USART6RST_N, 5   @ Bit 5 USART6RST: USART6 reset
                                    @ Set and cleared by software.
                                        @ 0: does not reset USART6
.EQU  RCC_APB2RSTR_USART6RST, 1 << 5    @ 1: resets USART6
.EQU  RCC_APB2RSTR_ADCRST_N, 8      @ Bit 8 ADC1RST: ADC interface reset
                                    @ Set and cleared by software.
                                     @ 0: does not reset the ADC interface
.EQU  RCC_APB2RSTR_ADCRST, 1 << 8    @ 1: resets the ADC interface
.EQU  RCC_APB2RSTR_SDIORST_N, 11    @ Bit 11 SDIORST: SDIO reset
                                    @ Set and cleared by software.
                                       @ 0: does not reset the SDIO module
.EQU  RCC_APB2RSTR_SDIORST, 1 << 11    @ 1: resets the SDIO module
.EQU  RCC_APB2RSTR_SPI1RST_N, 12    @ Bit 12 SPI1RST: SPI1 reset
                                    @ Set and cleared by software.
                                       @ 0: does not reset SPI1
.EQU  RCC_APB2RSTR_SPI1RST, 1 << 12    @ 1: resets SPI1
.EQU  RCC_APB2RSTR_SPI4RST_N, 13     @ Bit 13 SPI4RST: SPI4 reset
                                     @ Set and reset by software.
                                       @ 0: does not reset SPI4
.EQU  RCC_APB2RSTR_SPI4RST, 1 << 13    @ 1: resets SPI4
.EQU  RCC_APB2RSTR_SYSCFGRST_N, 14   @ Bit 14 SYSCFGRST: System configuration controller reset
                                     @ Set and cleared by software.
                                        @ 0: does not reset the System configuration controller
.EQU  RCC_APB2RSTR_SYSCFGRST, 1 << 14   @ 1: resets the System configuration controller
.EQU  RCC_APB2RSTR_TIM9RST_N, 16     @ Bit 16 TIM9RST: TIM9 reset
                                     @ Set and cleared by software.
                                        @ 0: does not reset TIM9
.EQU  RCC_APB2RSTR_TIM9RST, 1 << 16     @ 1: resets TIM9
.EQU  RCC_APB2RSTR_TIM10RST_N, 17    @ Bit 17 TIM10RST: TIM10 reset
                                     @ Set and cleared by software.
                                        @ 0: does not reset TIM10
.EQU  RCC_APB2RSTR_TIM10RST, 1 << 17    @ 1: resets TIM10
.EQU  RCC_APB2RSTR_TIM11RST_N, 18    @ Bit 18 TIM11RST: TIM11 reset
                                     @ Set and cleared by software.
                                        @ 0: does not reset TIM11
.EQU  RCC_APB2RSTR_TIM11RST, 1 << 18    @ 1: resets TIM11
@.END

@.ITEM     RCC_AHB1ENR
.EQU  RCC_AHB1ENR_GPIOAEN_N, 0    @ Bit 0 GPIOAEN: IO port A clock enable
                                  @ Set and cleared by software.
                                  @ 0: IO port A clock disabled
.EQU  RCC_AHB1ENR_GPIOAEN, 1      @ 1: IO port A clock enabled
.EQU  RCC_AHB1ENR_GPIOBEN_N, 1    @ Bit 1 GPIOBEN: IO port B clock enable
                                  @ Set and cleared by software.
                                  @ 0: IO port B clock disabled
.EQU  RCC_AHB1ENR_GPIOBEN, 1<<1   @ 1: IO port B clock enabled
.EQU  RCC_AHB1ENR_GPIOCEN_N, 2    @ Bit 2 GPIOCEN: IO port C clock enable
                                  @ Set and cleared by software.
                                  @ 0: IO port C clock disabled
.EQU  RCC_AHB1ENR_GPIOCEN, 1<<2   @ 1: IO port C clock enabled
.EQU  RCC_AHB1ENR_GPIODEN_N, 3    @ Bit 3 GPIODEN: IO port D clock enable
                                  @ Set and cleared by software.
                                  @ 0: IO port D clock disabled
.EQU  RCC_AHB1ENR_GPIODEN, 1<<3   @ 1: IO port D clock enabled
.EQU  RCC_AHB1ENR_GPIOEEN_N, 4    @ Bit 4 GPIOEEN: IO port E clock enable
                                  @ Set and cleared by software.
                                  @ 0: IO port E clock disabled
.EQU  RCC_AHB1ENR_GPIOEEN, 1<<4   @ 1: IO port E clock enabled
.EQU  RCC_AHB1ENR_GPIOHEN_N, 7    @ Bit 7 GPIOHEN: IO port H clock enable
                                  @ Set and reset by software.
                                  @ 0: IO port H clock disabled
.EQU  RCC_AHB1ENR_GPIOHEN, 1<<7   @ 1: IO port H clock enabled
.EQU  RCC_AHB1ENR_CRCEN_N, 12     @ Bit 12 CRCEN: CRC clock enable
                                  @ Set and cleared by software.
                                  @ 0: CRC clock disabled
.EQU  RCC_AHB1ENR_CRCEN, 1<<12    @ 1: CRC clock enabled
.EQU  RCC_AHB1ENR_DMA1EN_N, 21    @ Bit 21 DMA1EN: DMA1 clock enable
                                  @ Set and cleared by software.
                                  @ 0: DMA1 clock disabled
.EQU  RCC_AHB1ENR_DMA1EN, 1<<21   @ 1: DMA1 clock enabled
.EQU  RCC_AHB1ENR_DMA2EN_N, 22    @ Bit 22 DMA2EN: DMA2 clock enable
                                  @ Set and cleared by software.
                                  @ 0: DMA2 clock disabled
.EQU  RCC_AHB1ENR_DMA2EN, 1<<22   @ 1: DMA2 clock enabled
@.END

@.ITEM     RCC_AHB2ENR
.EQU  RCC_AHB2ENR_OTGFSEN_N, 7    @ Bit 7 OTGFSEN: USB OTG FS clock enable
                                  @ Set and cleared by software.
                                  @ 0: USB OTG FS clock disabled
.EQU  RCC_AHB2ENR_OTGFSEN, 1<<7   @ 1: USB OTG FS clock enabled
@.END

@.ITEM     RCC_APB1ENR
.EQU  RCC_APB1ENR_TIM2EN_N, 0    @ Bit 0 TIM2EN: TIM2 clock enable
                                 @ Set and cleared by software.
                                 @ 0: TIM2 clock disabled
.EQU  RCC_APB1ENR_TIM2EN, 1      @ 1: TIM2 clock enabled
.EQU  RCC_APB1ENR_TIM3EN_N, 1    @ Bit 1 TIM3EN: TIM3 clock enable
                                 @ Set and cleared by software.
                                 @ 0: TIM3 clock disabled
.EQU  RCC_APB1ENR_TIM3EN, 1<<1   @ 1: TIM3 clock enabled
.EQU  RCC_APB1ENR_TIM4EN_N, 2    @ Bit 2 TIM4EN: TIM4 clock enable
                                 @ Set and cleared by software.
                                 @ 0: TIM4 clock disabled
.EQU  RCC_APB1ENR_TIM4EN, 1<<2   @ 1: TIM4 clock enabled
.EQU  RCC_APB1ENR_TIM5EN_N, 3    @ Bit 3 TIM5EN: TIM5 clock enable
                                 @ Set and cleared by software.
                                 @ 0: TIM5 clock disabled
.EQU  RCC_APB1ENR_TIM5EN, 1<<3   @ 1: TIM5 clock enabled
.EQU  RCC_APB1ENR_WWDGEN_N, 11   @ Bit 11 WWDGEN: Window watchdog clock enable
                                 @ Set and cleared by software.
                                 @ 0: Window watchdog clock disabled
.EQU  RCC_APB1ENR_WWDGEN, 1<<11  @ 1: Window watchdog clock enabled
.EQU  RCC_APB1ENR_SPI2EN_N, 14   @ Bit 14 SPI2EN: SPI2 clock enable
                                 @ Set and cleared by software.
                                 @ 0: SPI2 clock disabled
.EQU  RCC_APB1ENR_SPI2EN, 1<<14  @ 1: SPI2 clock enabled
.EQU  RCC_APB1ENR_SPI3EN_N, 15   @ Bit 15 SPI3EN: SPI3 clock enable
                                 @ Set and cleared by software.
                                 @ 0: SPI3 clock disabled
.EQU  RCC_APB1ENR_SPI3EN, 1<<15  @ 1: SPI3 clock enabled
.EQU  RCC_APB1ENR_USART2EN_N, 17 @ Bit 17 USART2EN: USART2 clock enable
                                 @ Set and cleared by software.
                                 @ 0: USART2 clock disabled
.EQU  RCC_APB1ENR_USART2EN, 1<<17 @ 1: USART2 clock enabled
.EQU  RCC_APB1ENR_I2C1EN_N, 21   @ Bit 21 I2C1EN: I2C1 clock enable
                                 @ Set and cleared by software.
                                 @ 0: I2C1 clock disabled
.EQU  RCC_APB1ENR_I2C1EN, 1<<21  @ 1: I2C1 clock enabled
.EQU  RCC_APB1ENR_I2C2EN_N, 22   @ Bit 22 I2C2EN: I2C2 clock enable
                                 @ Set and cleared by software.
                                 @ 0: I2C2 clock disabled
.EQU  RCC_APB1ENR_I2C2EN, 1<<22  @ 1: I2C2 clock enabled
.EQU  RCC_APB1ENR_I2C3EN_N, 23   @ Bit 23 I2C3EN: I2C3 clock enable
                                 @ Set and cleared by software.
                                 @ 0: I2C3 clock disabled
.EQU  RCC_APB1ENR_I2C3EN, 1<<23  @ 1: I2C3 clock enabled
.EQU  RCC_APB1ENR_PWREN_N, 28    @ Bit 28 PWREN: Power interface clock enable
                                 @ Set and cleared by software.
                                 @ 0: Power interface clock disabled
.EQU  RCC_APB1ENR_PWREN, 1<<28   @ 1: Power interface clock enable
@.END

@.ITEM     RCC_APB2ENR
.EQU  RCC_APB2ENR_TIM1EN_N, 0    @ Bit 0 TIM1EN: TIM1 clock enable
                                 @ Set and cleared by software.
                                 @ 0: TIM1 clock disabled
.EQU  RCC_APB2ENR_TIM1EN, 1      @ 1: TIM1 clock enabled
.EQU  RCC_APB2ENR_USART1EN_N, 4  @ Bit 4 USART1EN: USART1 clock enable
                                 @ Set and cleared by software.
                                 @ 0: USART1 clock disabled
.EQU  RCC_APB2ENR_USART1EN, 1<<4 @ 1: USART1 clock enabled
.EQU  RCC_APB2ENR_USART6EN_N, 5  @ Bit 5 USART6EN: USART6 clock enable
                                 @ Set and cleared by software.
                                 @ 0: USART6 clock disabled
.EQU  RCC_APB2ENR_USART6EN, 1<<5 @ 1: USART6 clock enabled
.EQU  RCC_APB2ENR_ADC1EN_N, 8    @ Bit 8 ADC1EN: ADC1 clock enable
                                 @ Set and cleared by software.
                                 @ 0: ADC1 clock disabled
.EQU  RCC_APB2ENR_ADC1EN, 1<<8   @ 1: ADC1 clock disabled
.EQU  RCC_APB2ENR_SDIOEN_N, 11   @ Bit 11 SDIOEN: SDIO clock enable
                                 @ Set and cleared by software.
                                 @ 0: SDIO module clock disabled
.EQU  RCC_APB2ENR_SDIOEN, 1<<11  @ 1: SDIO module clock enabled
.EQU  RCC_APB2ENR_SPI1EN_N, 12   @ Bit 12 SPI1EN: SPI1 clock enable
                                 @ Set and cleared by software.
                                 @ 0: SPI1 clock disabled
.EQU  RCC_APB2ENR_SPI1EN, 1<<12  @ 1: SPI1 clock enabled
.EQU  RCC_APB2ENR_SPI4EN_N, 13   @ Bit 13 SPI4EN: SPI4 clock enable
                                 @ Set and reset by software.
                                 @ 0: SPI4 clock disabled
.EQU  RCC_APB2ENR_SPI4EN, 1<<13  @ 1: SPI4 clock enable
.EQU  RCC_APB2ENR_SYSCFGEN_N, 14 @ Bit 14 SYSCFGEN: System configuration controller clock enable
                                  @ Set and cleared by software.
                                  @ 0: System configuration controller clock disabled
.EQU  RCC_APB2ENR_SYSCFGEN, 1<<14 @ 1: System configuration controller clock enabled
.EQU  RCC_APB2ENR_TIM9EN_N, 16    @ Bit 16 TIM9EN: TIM9 clock enable
                                  @ Set and cleared by software.
                                  @ 0: TIM9 clock disabled
.EQU  RCC_APB2ENR_TIM9EN, 1<<16   @ 1: TIM9 clock enabled
.EQU  RCC_APB2ENR_TIM10EN_N, 17   @ Bit 17 TIM10EN: TIM10 clock enable
                                  @ Set and cleared by software.
                                  @ 0: TIM10 clock disabled
.EQU  RCC_APB2ENR_TIM10EN, 1<<17  @ 1: TIM10 clock enabled
.EQU  RCC_APB2ENR_TIM11EN_N, 18   @ Bit 18 TIM11EN: TIM11 clock enable
                                  @ Set and cleared by software.
                                  @ 0: TIM11 clock disabled
.EQU  RCC_APB2ENR_TIM11EN, 1<<18  @ 1: TIM11 clock enabled
@.END

@.ITEM     RCC_AHB1LPENR
.EQU  RCC_AHB1LPENR_GPIOALPEN_N, 0  @ Bit 0 GPIOALPEN: IO port A clock enable during sleep mode
                                    @ Set and cleared by software.
                                    @ 0: IO port A clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOALPEN, 1    @ 1: IO port A clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOBLPEN_N, 1  @ Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode
                                    @ Set and cleared by software.
                                    @ 0: IO port B clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOBLPEN, 1<<1 @ 1: IO port B clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOCLPEN_N, 2  @ Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode
                                    @ Set and cleared by software.
                                    @ 0: IO port C clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOCLPEN, 1<<2 @ 1: IO port C clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIODLPEN_N, 3  @ Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode
                                    @ Set and cleared by software.
                                    @ 0: IO port D clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIODLPEN, 1<<3 @ 1: IO port D clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOELPEN_N, 4  @ Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode
                                    @ Set and cleared by software.
                                    @ 0: IO port E clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOELPEN, 1<<4 @ 1: IO port E clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_GPIOHLPEN_N, 7  @ Bit 7 GPIOHLPEN: IO port H clock enable during sleep mode
                                    @ Set and reset by software.
                                    @ 0: IO port H clock disabled during sleep mode
.EQU  RCC_AHB1LPENR_GPIOHLPEN, 1<<7 @ 1: IO port H clock enabled during sleep mode
.EQU  RCC_AHB1LPENR_CRCLPEN_N, 12   @ Bit 12 CRCLPEN: CRC clock enable during Sleep mode
                                    @ Set and cleared by software.
                                    @ 0: CRC clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_CRCLPEN, 1<<12  @ 1: CRC clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_FLITFLPEN_N, 15 @ Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: Flash interface clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_FLITFLPEN, 1<<15 @ 1: Flash interface clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_SRAM1LPEN_N, 16  @ Bit 16 SRAM1LPEN: SRAM1interface clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: SRAM1 interface clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_SRAM1LPEN, 1<<16 @ 1: SRAM1 interface clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_DMA1LPEN_N, 21   @ Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: DMA1 clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_DMA1LPEN, 1<<21  @ 1: DMA1 clock enabled during Sleep mode
.EQU  RCC_AHB1LPENR_DMA2LPEN_N, 22   @ Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: DMA2 clock disabled during Sleep mode
.EQU  RCC_AHB1LPENR_DMA2LPEN, 1<<22  @ 1: DMA2 clock enabled during Sleep mode
@.END

@.ITEM     RCC_AHB2LPENR
.EQU  RCC_AHB2LPENR_OTGFSLPEN_N, 7   @ Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: USB OTG FS clock disabled during Sleep mode
.EQU  RCC_AHB2LPENR_OTGFSLPEN, 1<<7  @ 1: USB OTG FS clock enabled during Sleep mode
@.END

@.ITEM     RCC_APB1LPENR
.EQU  RCC_APB1LPENR_TIM2LPEN_N, 0    @ Bit 0 TIM2LPEN: TIM2 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: TIM2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM2LPEN, 1      @ 1: TIM2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM3LPEN_N, 1    @ Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: TIM3 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM3LPEN, 1<<1   @ 1: TIM3 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM4LPEN_N, 2    @ Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: TIM4 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM4LPEN, 1<<2   @ 1: TIM4 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM5LPEN_N, 3    @ Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: TIM5 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_TIM5LPEN, 1<<3   @ 1: TIM5 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_WWDGLPEN_N, 11   @ Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: Window watchdog clock disabled during sleep mode
.EQU  RCC_APB1LPENR_WWDGLPEN, 1<<11  @ 1: Window watchdog clock enabled during sleep mode
.EQU  RCC_APB1LPENR_SPI2LPEN_N, 14   @ Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: SPI2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI2LPEN, 1<<14  @ 1: SPI2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI3LPEN_N, 15   @ Bit 15 SPI3LPEN: SPI3 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: SPI3 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_SPI3LPEN, 1<<15  @ 1: SPI3 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_USART2LPEN_N, 17 @ Bit 17 USART2LPEN: USART2 clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: USART2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_USART2LPEN, 1<<17 @ 1: USART2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C1LPEN_N, 21    @ Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: I2C1 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C1LPEN, 1<<21   @ 1: I2C1 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C2LPEN_N, 22    @ Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: I2C2 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C2LPEN, 1<<22   @ 1: I2C2 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C3LPEN_N, 23    @ Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: I2C3 clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_I2C3LPEN, 1<<23   @ 1: I2C3 clock enabled during Sleep mode
.EQU  RCC_APB1LPENR_PWRLPEN_N, 28     @ Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: Power interface clock disabled during Sleep mode
.EQU  RCC_APB1LPENR_PWRLPEN, 1<<28    @ 1: Power interface clock enabled during Sleep mode
@.END

@.ITEM     RCC_APB2LPENR
.EQU  RCC_APB2LPENR_TIM1LPEN_N, 0    @ Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: TIM1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM1LPEN, 1      @ 1: TIM1 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_USART1LPEN_N, 4  @ Bit 4 USART1LPEN: USART1 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: USART1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_USART1LPEN, 1<<4 @ 1: USART1 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_USART6LPEN_N, 5  @ Bit 5 USART6LPEN: USART6 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: USART6 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_USART6LPEN, 1<<5 @ 1: USART6 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_ADC1LPEN_N, 8    @ Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: ADC1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_ADC1LPEN, 1<<8   @ 1: ADC1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SDIOLPEN_N, 11   @ Bit 11 SDIOLPEN: SDIO clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: SDIO module clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SDIOLPEN, 1<<11  @ 1: SDIO module clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_SPI1LPEN_N, 12   @ Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
                                     @ Set and cleared by software.
                                     @ 0: SPI1 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SPI1LPEN, 1<<12  @ 1: SPI1 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_SPI4LPEN_N, 13   @ Bit 13 SPI4LPEN: SPI4 clock enable during sleep mode
                                     @ Set and reset by software.
                                     @ 0: SPI4 clock disabled during sleep mode
.EQU  RCC_APB2LPENR_SPI4LPEN, 1<<13  @ 1: SPI4 clock enabled during sleep mode
.EQU  RCC_APB2LPENR_SYSCFGLPEN_N, 14 @ Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: System configuration controller clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_SYSCFGLPEN, 1<<14 @ 1: System configuration controller clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM9LPEN_N, 16    @ Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
                                      @ Set and cleared by software.
                                      @ 0: TIM9 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM9LPEN, 1<<16   @ 1: TIM9 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM10LPEN_N, 17   @ Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: TIM10 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM10LPEN, 1<<17  @ 1: TIM10 clock enabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM11LPEN_N, 18   @ Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
                                      @ Set and cleared by software.
                                      @ 0: TIM11 clock disabled during Sleep mode
.EQU  RCC_APB2LPENR_TIM11LPEN, 1<<18  @ 1: TIM11 clock enabled during Sleep mode
@.END

@.ITEM     RCC_BDCR
.EQU  RCC_BDCR_LSEON_N, 0             @ Bit 0 LSEON: External low-speed oscillator enable
                                      @ Set and cleared by software.
                                      @ 0: LSE clock OFF
.EQU  RCC_BDCR_LSEON, 1               @ 1: LSE clock ON
.EQU  RCC_BDCR_LSERDY_N, 1            @ Bit 1 LSERDY: External low-speed oscillator ready
                                      @ Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
                                      @ the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
                                      @ cycles.
                                      @ 0: LSE clock not ready
.EQU  RCC_BDCR_LSERDY, 1<<1           @ 1: LSE clock ready
.EQU  RCC_BDCR_LSEBYP_N, 2            @ Bit 2 LSEBYP: External low-speed oscillator bypass
                                      @ Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
                                      @ when the LSE clock is disabled.
                                      @ 0: LSE oscillator not bypassed
.EQU  RCC_BDCR_LSEBYP, 1<<2           @ 1: LSE oscillator bypassed
.EQU  RCC_BDCR_RTCSEL_N, 8            @ Bits 9:8 RTCSEL[1:0]: RTC clock source selection
                                      @ Set by software to select the clock source for the RTC. Once the RTC clock source has been
                                      @ selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit
                                      @ can be used to reset them.
.EQU  RCC_BDCR_RTCSEL_NO_CLOCK, 0     @ 00: No clock
.EQU  RCC_BDCR_RTCSEL_LSE, 1 << 8     @ 01: LSE oscillator clock used as the RTC clock
.EQU  RCC_BDCR_RTCSEL_LSI, 2 << 8     @ 10: LSI oscillator clock used as the RTC clock
.EQU  RCC_BDCR_RTCSEL_HSE, 3 << 8     @ 11: HSE oscillator clock divided by a programmable prescaler (selection through the
                                      @ RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
                                      @ clock
.EQU  RCC_BDCR_RTCEN_N, 15            @ Bit 15 RTCEN: RTC clock enable
                                      @ Set and cleared by software.
                                      @ 0: RTC clock disabled
.EQU  RCC_BDCR_RTCEN, 1<<15           @ 1: RTC clock enabled
.EQU  RCC_BDCR_BDRST_N, 16            @ Bit 16 BDRST: Backup domain software reset
                                      @ Set and cleared by software.
                                      @ 0: Reset not activated
.EQU  RCC_BDCR_BDRST, 1<<16           @ 1: Resets the entire Backup domain
@.END

@.ITEM     RCC_CSR
.EQU  RCC_CSR_LSION_N, 0              @ Bit 0 LSION: Internal low-speed oscillator enable
                                      @ Set and cleared by software.
                                      @ 0: LSI RC oscillator OFF
.EQU  RCC_CSR_LSION , 1               @ 1: LSI RC oscillator ON
.EQU  RCC_CSR_LSIRDY_N, 1             @ Bit 1 LSIRDY: Internal low-speed oscillator ready
                                      @ Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
                                      @ After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.
                                      @ 0: LSI RC oscillator not ready
.EQU  RCC_CSR_LSIRDY, 1<<1            @ 1: LSI RC oscillator ready
.EQU  RCC_CSR_RMVF_N, 24              @ Bit 24 RMVF: Remove reset flag
                                      @ Set by software to clear the reset flags.
                                      @ 0: No effect
.EQU  RCC_CSR_RMVF  , 1<<24           @ 1: Clear the reset flags
.EQU  RCC_CSR_BORRSTF_N, 25           @ Bit 25 BORRSTF: BOR reset flag
                                      @ Cleared by software by writing the RMVF bit.
                                      @ Set by hardware when a POR/PDR or BOR reset occurs.
                                      @ 0: No POR/PDR or BOR reset occurred
.EQU  RCC_CSR_BORRSTF, 1<<25          @ 1: POR/PDR or BOR reset occurred
.EQU  RCC_CSR_PINRSTF_N, 26           @ Bit 26 PINRSTF: PIN reset flag
                                      @ Set by hardware when a reset from the NRST pin occurs.
                                      @ Cleared by writing to the RMVF bit.
                                      @ 0: No reset from NRST pin occurred
.EQU  RCC_CSR_PINRSTF, 1<<26          @ 1: Reset from NRST pin occurred
.EQU  RCC_CSR_PORRSTF_N, 27           @ Bit 27 PORRSTF: POR/PDR reset flag
                                      @ Set by hardware when a POR/PDR reset occurs.
                                      @ Cleared by writing to the RMVF bit.
                                      @ 0: No POR/PDR reset occurred
.EQU  RCC_CSR_PORRSTF, 1<<27          @ 1: POR/PDR reset occurred
.EQU  RCC_CSR_SFTRSTF_N, 28           @ Bit 28 SFTRSTF: Software reset flag
                                      @ Set by hardware when a software reset occurs.
                                      @ Cleared by writing to the RMVF bit.
                                      @ 0: No software reset occurred
.EQU  RCC_CSR_SFTRSTF, 1<<28          @ 1: Software reset occurred
.EQU  RCC_CSR_WDGRSTF_N, 29           @ Bit 29 IWDGRSTF: Independent watchdog reset flag
                                      @ Set by hardware when an independent watchdog reset from VDD domain occurs.
                                      @ Cleared by writing to the RMVF bit.
                                      @ 0: No watchdog reset occurred
.EQU  RCC_CSR_WDGRSTF, 1<<29          @ 1: Watchdog reset occurred
.EQU  RCC_CSR_WWDGRSTF_N, 30          @ Bit 30 WWDGRSTF: Window watchdog reset flag
                                      @ Set by hardware when a window watchdog reset occurs.
                                      @ Cleared by writing to the RMVF bit.
                                      @ 0: No window watchdog reset occurred
.EQU  RCC_CSR_WWDGRSTF, 1<<30         @ 1: Window watchdog reset occurred
.EQU  RCC_CSR_LPWRRSTF_N, 31          @ Bit 31 LPWRRSTF: Low-power reset flag
                                      @ Set by hardware when a Low-power management reset occurs.
                                      @ Cleared by writing to the RMVF bit.
                                      @ 0: No Low-power management reset occurred
.EQU  RCC_CSR_LPWRRSTF, 1<<31         @ 1: Low-power management reset occurred
                                      @ For further information on Low-power management reset, refer to Low-power management
                                      @ reset.
@.END

@.ITEM     RCC_SSCGR
.EQU  RCC_SSCGR_MODPER_N, 0      @ Bits 12:0 MODPER: Modulation period
                                 @ Set and cleared by software. To write before setting CR[24]=PLLON bit.
                                 @ Configuration input for modulation profile period.
.EQU  RCC_SSCGR_INCSTEP_N, 13    @ Bits 27:13 INCSTEP: Incrementation step
                                 @ Set and cleared by software. To write before setting CR[24]=PLLON bit.
                                 @ Configuration input for modulation profile amplitude.
.EQU  RCC_SSCGR_SPREADSEL_N, 30  @ Bit 30 SPREADSEL: Spread Select
                                      @ Set and cleared by software.
                                      @ To write before to set CR[24]=PLLON bit.
                                      @ 0: Center spread
.EQU  RCC_SSCGR_SPREADSEL, 1<<30      @ 1: Down spread
.EQU  RCC_SSCGR_SSCGEN_N, 31     @ Bit 31 SSCGEN: Spread spectrum modulation enable
                                 @ Set and cleared by software.
                                 @ 0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)
.EQU  RCC_SSCGR_SSCGEN, 1<<31    @ 1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)
@.END

@.ITEM     RCC_PLLI2SCFGR
.EQU  RCC_PLLI2SCFGR_PLLI2SN_N, 6    @ Bits 14:6 PLLI2SN: PLLI2S multiplication factor for VCO
                                     @ Set and cleared by software to control the multiplication factor of the VCO. These bits can
                                     @ be written only when the PLLI2S is disabled. Only half-word and word accesses are allowed
                                     @ to write these bits.
                            @ Caution: The software has to set these bits correctly to ensure that the VCO output
                                     @ frequency is between 192 and 432 MHz. With VCO input frequency ranges from 1
                                     @ to 2 MHz (refer to Figure 13 and divider factor M of the RCC PLL configuration
                                     @ register (RCC_PLLCFGR))
                                     @ VCO output frequency = VCO input frequency Ч PLLI2SN with 192  PLLI2SN  432
                                     @ 000000000: PLLI2SN = 0, wrong configuration
                                     @ 000000001: PLLI2SN = 1, wrong configuration
                                     @ ...
                                     @ 011000000: PLLI2SN = 192
                                     @ 011000001: PLLI2SN = 193
                                     @ 011000010: PLLI2SN = 194
                                     @ ...
                                     @ 110110000: PLLI2SN = 432
                                     @ 110110000: PLLI2SN = 433, wrong configuration
                                     @ ...
                                     @ 111111111: PLLI2SN = 511, wrong configuration
.EQU  RCC_PLLI2SCFGR_PLLI2SR_N, 28   @ Bits 30:28 PLLI2SR: PLLI2S division factor for I2S clocks
                                     @ Set and cleared by software to control the I2S clock frequency. These bits should be written
                                     @ only if the PLLI2S is disabled. The factor must be chosen in accordance with the prescaler
                                     @ values inside the I2S peripherals, to reach 0.3% error when using standard crystals and 0%
                                     @ error with audio crystals. For more information about I2S clock frequency and precision,
                                     @ refer to Section 20.4.4: Clock generator in the I2S chapter.
                                     @ Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
                                     @ I2S clock frequency = VCO frequency / PLLR with 2  PLLR  7
                                     @ 000: PLLR = 0, wrong configuration
                                     @ 001: PLLR = 1, wrong configuration
                                     @ 010: PLLR = 2
                                     @ ...
                                     @ 111: PLLR = 7
@.END

@.ITEM     RCC_DCKCFGR
.EQU  RCC_DCKCFGR_TIMPRE_N, 24    @ Bit 24  TIMPRE: Timers clocks prescalers selection
                                  @ Set and reset by software to control the clock frequency of all the timers connected to APB1
                                  @ and APB2 domain.
                                  @ 0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register)  is configured to a
                                  @ division factor of 1, TIMxCLK = HCKL . Otherwise, the timer clock frequencies are set to
                                  @ twice to the frequency of the APB domain to which the timers are connected:
                                  @ TIMxCLK = 2xPCLKx.
.EQU  RCC_DCKCFGR_TIMPRE, 1 << 24 @ 1:If the APB prescaler ( PPRE1, PPRE2 in the RCC_CFGR register)  is configured to a
                                  @ division factor of 1 or 2, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to
                                  @ four times to the frequency of the APB domain to which the timers are connected:
                                  @ TIMxCLK = 4xPCLKx.
@.END
