@.ITEM     TIM9A12_BASE TIM9 TIM12_BASE TIM12
.EQU  TIM9A12_CR1           , 0x00    @ TIM9A12 control register 1 (TIMx_CR1)
.EQU  TIM9A12_SMCR          , 0x08    @ TIM9A12 slave mode control register (TIMx_SMCR)
.EQU  TIM9A12_DIER          , 0x0C    @ TIM9A12 Interrupt enable register (TIMx_DIER)
.EQU  TIM9A12_SR            , 0x10    @ TIM9A12 status re gister (TIMx_SR)
.EQU  TIM9A12_EGR           , 0x14    @ TIM9A12 event g eneration register (TIMx_EGR)
.EQU  TIM9A12_CCMR1         , 0x18    @ TIM9A12 capture/compare m ode register 1 (TIMx_CCMR1)
.EQU  TIM9A12_CCER          , 0x20    @ TIM9A12 capture/compare e nable register (TIMx_CCER)
.EQU  TIM9A12_CNT           , 0x24    @ TIM9A12 counter (TIMx_CNT)
.EQU  TIM9A12_PSC           , 0x28    @ TIM9A12 prescaler (TIMx_PSC)
.EQU  TIM9A12_ARR           , 0x2C    @ TIM9A12 auto-reload register (TIMx_ARR)
.EQU  TIM9A12_CCR1          , 0x34    @ TIM9A12 capture/compare register 1 (TIMx_CCR1)
.EQU  TIM9A12_CCR2          , 0x38    @ TIM9A12 c apture/compare register 2 (TIMx_CCR2)
@.end

@.ITEM     TIM9A12_CR1
.EQU  TIM9A12_CR1_CKD_N     , 8          @ Bits 9:8 CKD: Clock division
                                      @ This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
                                      @ sampling clock used by the digital filters (TIx),
.EQU  TIM9A12_CR1_CKD_1     , 0          @ 00: tDTS = tCK_INT
.EQU  TIM9A12_CR1_CKD_2     , 1 << 8     @ 01: tDTS = 2 x tCK_INT
.EQU  TIM9A12_CR1_CKD_4     , 2 << 8     @ 10: tDTS = 4 x tCK_INT
.EQU  TIM9A12_CR1_APRE      , 1 << 7     @ Bit 7 ARPE: Auto-reload preload enable
                                      @ 0: TIMx_ARR register is not buffered.
                                      @ 1: TIMx_ARR register is buffered.
.EQU  TIM9A12_CR1_OPM       , 1 << 3     @ Bit 3 OPM: One-pulse mode
                                      @  0: Counter is not stopped on the update event
                                      @ 1: Counter stops counting on the next update event (clearing the CEN bit).
.EQU  TIM9A12_CR1_URS       , 1 << 2     @ Bit 2 URS: Update request source
                                      @ This bit is set and cleared by software to select the UEV event sources.
                                      @ 0: Any of the following events generates an update interrupt if enabled:
                                      @ – Counter overflow
                                      @ – Setting the UG bit
                                      @ 1: Only counter overflow generates an update interrupt if enabled
.EQU  TIM9A12_CR1_UDIS      , 1 << 1     @ Bit 1 UDIS: Update disable
                                      @ This bit is set and cleared by software to enable/disable update event (UEV) generation.
                                      @ 0: UEV enabled. An UEV is generated by one of the following events:
                                      @ – Counter overflow
                                      @ – Setting the UG bit
                                      @ Buffered registers are then loaded with their preload values.
                                      @ 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
                                      @ CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
.EQU  TIM9A12_CR1_CEN       , 1          @ Bit 0 CEN: Counter enable
                                      @ 0: Counter disabled
                                      @ 1: Counter enabled
                                      @ CEN is cleared automatically in one-pulse mode, when an update event occurs.
@.end

@.ITEM     TIM9A12_SMCR
.EQU  TIM9A12_SMCR_MSM      , 1 << 7    @ Bit 7 MSM: Master/Slave mode
                                     @ 0: No action
                                     @ 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
                                     @ synchronization between the current timer and its slaves (through TRGO). It is useful in
                                     @ order to synchronize several timers on a single external event.
.EQU  TIM9A12_SMCR_TS_N     , 4         @ Bits 6:4 TS: Trigger selection
                                     @ This bit field selects the trigger input to be used to synchronize the counter.
.EQU  TIM9A12_SMCR_TS_ITR0  , 0         @ Internal Trigger 0 (ITR0
.EQU  TIM9A12_SMCR_TS_ITR1  , 1 << 4    @ Internal Trigger 1 (ITR1)
.EQU  TIM9A12_SMCR_TS_ITR2  , 2 << 4    @ Internal Trigger 2 (ITR2)
.EQU  TIM9A12_SMCR_TS_ITR3  , 3 << 4    @Internal Trigger 3 (ITR3)
.EQU  TIM9A12_SMCR_TS_TI1F_ED, 4 << 4   @ TI1 Edge Detector (TI1F_ED)
.EQU  TIM9A12_SMCR_TS_TI1FP1, 5 << 4    @  Filtered Timer Input 1 (TI1FP1)
.EQU  TIM9A12_SMCR_TS_TI2FP2, 6 << 4    @ Filtered Timer Input 2 (TI2FP2)
.EQU  TIM9A12_SMCR_SMS_N    , 0         @ Bits 2:0 SMS: Slave mode selection
                                     @ When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
                                     @ the polarity selected on the external input (see Input control register and Control register
                                     @ descriptions.
.EQU  TIM9A12_SMCR_SMS_SMD  , 0         @ Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock
.EQU  TIM9A12_SMCR_SMS_ENCM1, 1         @ reserved
.EQU  TIM9A12_SMCR_SMS_ENCM2, 2         @ reserved
.EQU  TIM9A12_SMCR_SMS_ENCM3, 3         @ reserved
.EQU  TIM9A12_SMCR_SMS_RSTM , 4         @ 100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
                                     @ and generates an update of the registers
.EQU  TIM9A12_SMCR_SMS_GTDM , 5         @ 101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
                                     @ counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops
                                     @ are both controlled
.EQU  TIM9A12_SMCR_SMS_TRGM , 6         @ 110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
                                     @ reset). Only the start of the counter is controlled
.EQU  TIM9A12_SMCR_SMS_EXTCLK, 7        @ 111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter
                               @ Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
                                     @ (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
                                     @ Gated mode checks the level of the trigger signal.
                               @ Note: The clock of the slave timer must be enabled prior to receive events from the master
                                     @ timer, and must not be changed on-the-fly while triggers are received from the master
                                     @ timer.
@
@ Table 57. TIMx internal trigger connection (STM32F401)
@ +-----------+-----------------+-----------------+-----------------+-----------------+
@ | Slave TIM | ITR0 (TS = 000) | ITR1 (TS = 001) | ITR2 (TS = 010) | ITR3 (TS = 011) |
@ +-----------+-----------------+-----------------+-----------------+-----------------+
@ |  TIM 9    |    TIM2_TRGO    |   TIM3_TRGO     |    TIM10_OC     |   TIM11_OC      |
@ +-----------+-----------------+-----------------+-----------------+-----------------+
@
@ Table 101. TIMx internal trigger connection (STM32F405\407\415\417)
@ +-----------+-----------------+-----------------+-----------------+-----------------+
@ | Slave TIM | ITR0 (TS = 000) | ITR1 (TS = 001) | ITR2 (TS = 010) | ITR3 (TS = 011) |
@ +-----------+-----------------+-----------------+-----------------+-----------------+
@ |  TIM 9    |    TIM2_TRGO    |   TIM3_TRGO     |    TIM10_OC     |   TIM11_OC      |
@ +-----------+-----------------+-----------------+-----------------+-----------------+
@ |  TIM 12   |    TIM4_TRGO    |   TIM5_TRGO     |    TIM13_OC     |   TIM14_OC      |
@ +-----------+-----------------+-----------------+-----------------+-----------------+

@.end

@.ITEM     TIM9A12_DIER
.EQU  TIM9A12_DIER_TIE   , 1 << 6     @ Bit 6 TIE: Trigger interrupt enable
                                   @ 0: Trigger interrupt disabled.
                                   @ 1: Trigger interrupt enabled.
.EQU  TIM9A12_DIER_CC2IE , 1 << 2     @ Bit 2 CC2IE: Capture/Compare 2 interrupt enable
                                   @ 0: CC2 interrupt disabled.
                                   @ 1: CC2 interrupt enabled
.EQU  TIM9A12_DIER_CC1IE , 1 << 1     @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
                                   @ 0: CC1 interrupt disabled.
                                   @ 1: CC1 interrupt enabled.
.EQU  TIM9A12_DIER_UIE   , 1          @ Bit 0 UIE: Update interrupt enable
                                   @ 0: Update interrupt disabled.
                                   @ 1: Update interrupt enabled.
@.end

@.ITEM     TIM9A12_SR
.EQU  TIM9A12_SR_CC2OF       , 1 << 10    @ Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description
.EQU  TIM9A12_SR_CC1OF       , 1 << 9     @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
                                       @ This flag is set by hardware only when the corresponding channel is configured in input
                                       @ capture mode. It is cleared by software by writing it to ‘0’.
                                       @ 0: No overcapture has been detected.
                                       @ 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
                                       @ already set
.EQU  TIM9A12_SR_TIF         , 1 << 6     @ Bit 6 TIF: Trigger interrupt flag
                                       @ This flag is set by hardware on trigger event (active edge detected on TRGI input when the
                                       @ slave mode controller is enabled in all modes but gated mode. It is set when the counter
                                       @ starts or stops when gated mode is selected. It is cleared by software.
                                       @ 0: No trigger event occurred.
                                       @ 1: Trigger interrupt pending.
.EQU  TIM9A12_SR_CC2IF       , 1 << 2     @ Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description
.EQU  TIM9A12_SR_CC1IF       , 1 << 1     @ Bit 1 CC1IF: Capture/compare 1 interrupt flag
                                       @ If channel CC1 is configured as output:
                                       @ This flag is set by hardware when the counter matches the compare value. It is cleared by
                                       @ software.
                                       @ 0: No match.
                                       @ 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
                                       @ When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
                                       @ bit goes high on the counter overflow.
                                       @ If channel CC1 is configured as input:
                                       @ This bit is set by hardware on a capture. It is cleared by software or by reading the
                                       @ TIMx_CCR1 register.
                                       @ 0: No input capture occurred.
                                       @ 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
                                       @ on IC1 which matches the selected polarity).
.EQU  TIM9A12_SR_UIF         , 1          @ Bit 0 UIF: Update interrupt flag
                                       @ This bit is set by hardware on an update event. It is cleared by software.
                                       @ 0: No update occurred.
                                       @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                       @ – At overflow and if UDIS=’0’ in the TIMx_CR1 register.
                                       @ – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and
                                       @ UDIS=’0’ in the TIMx_CR1 register.
                                       @ – When CNT is reinitialized by a trigger event (refer to the synchro control register
                                       @ description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.
@.end

@.ITEM     TIM9A12_EGR
.EQU  TIM9A12_EGR_TG      , 1 << 6     @ Bit 6 TG: Trigger generation
                                    @ This bit is set by software in order to generate an event, it is automatically cleared by
                                    @ hardware.
                                    @ 0: No action
                                    @ 1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled
.EQU  TIM9A12_EGR_CC2G    , 1 << 2     @ Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description
.EQU  TIM9A12_EGR_CC1G    , 1 << 1     @ Bit 1 CC1G: Capture/compare 1 generation
                                    @ This bit is set by software to generate an event, it is automatically cleared by hardware.
                                    @ 0: No action
                                    @ 1: A capture/compare event is generated on channel 1:
                                    @ If channel CC1 is configured as output:
                                    @ the CC1IF flag is set, the corresponding interrupt is sent if enabled.
                                    @ If channel CC1 is configured as input:
                                    @ The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
                                    @ corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
                                    @ already high.
.EQU  TIM9A12_EGR_UG      , 1          @ Bit 0 UG: Update generation
                                    @ This bit can be set by software, it is automatically cleared by hardware.
                                    @ 0: No action
                                    @ 1: Re-initializes the counter and generates an update of the registers. The prescaler counter
                                    @ is also cleared and the prescaler ratio is not affected. The counter is cleared.
@.end

@.ITEM     TIM9A12_CCMR1
.EQU  TIM9A12_CCMR1_OUTPUT_COMPARE_MODE, 0
.EQU  TIM9A12_CCMR1_INPUT_CAPTURE_MODE, 0
.EQU  TIM9A12_CCMR1_CC2S_N   , 8          @ Capture/Compare 2 selection
.EQU  TIM9A12_CCMR1_CC2S_OUT , 0          @ CC2 channel is configured as output
.EQU  TIM9A12_CCMR1_CC2S_TI2 , 1 << 8     @ 01: CC2 channel is configured as input, IC2 is mapped on TI2
.EQU  TIM9A12_CCMR1_CC2S_TI1 , 2 << 8     @ 10: CC2 channel is configured as input, IC2 is mapped on TI1
.EQU  TIM9A12_CCMR1_CC2S_TRC , 3 << 8     @ 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
                                          @ internal trigger input is selected through the TS bit (TIMx_SMCR register
                                          @ Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
.EQU  TIM9A12_CCMR1_CC1S_N   , 0
.EQU  TIM9A12_CCMR1_CC1S_OUT , 0          @ CC1 channel is configured as output
.EQU  TIM9A12_CCMR1_CC1S_TI1 , 1          @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM9A12_CCMR1_CC1S_TI2 , 2          @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM9A12_CCMR1_CC1S_TRC , 3          @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an
                                          @ internal trigger input is selected through the TS bit (TIMx_SMCR register)
                                          @ Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
@.end

@.ITEM     TIM9A12_CCMR1_OUTPUT_COMPARE_MODE
.EQU  TIM9A12_CCMR1_OC2M_N   , 12         @ Output compare 2 mode
.EQU  TIM9A12_CCMR1_OC2M_FROZEN, 0        @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter     TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM9A12_CCMR1_OC2M_ACT , 1 << 12    @ Set channel 2 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM9A12_CCMR1_OC2M_INACT, 2 << 12    @ Set channel 2 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM9A12_CCMR1_OC2M_TOGGLE, 3 << 12    @ Toggle - OC2REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM9A12_CCMR1_OC2M_FORSEINACT, 4 << 12    @ Force inactive level - OC2REF is forced low.
.EQU  TIM9A12_CCMR1_OC2M_FORSEACT, 5 << 12    @ Force active level - OC2REF is forced high.
.EQU  TIM9A12_CCMR1_OC2M_PWM1, 6 << 12    @  PWM mode 1 - In upcounting, channel 2 is active as long as TIMx_CNT<TIMx_CCR1  else        inactive. In downcounting, channel 1 is inactive ( OC1REF = �0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM9A12_CCMR1_OC2M_PWM2, 7 << 12    @ PWM mode 2 - In upcounting, channel 2 is inactive as long as TIMx_CNT<TIMx_CCR1 else        active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM9A12_CCMR1_OC2PE    , 1 << 11    @ Output compare 2 preload enable
.EQU  TIM9A12_CCMR1_OC2FE    , 1 << 10    @ Output compare 2 fast enable
.EQU  TIM9A12_CCMR1_OC1M_N   , 4          @  Output compare 1 mode
.EQU  TIM9A12_CCMR1_OC1M_FROZEN, 0        @ Frozen - The comparison between the output compare register TIMx_CCR1 and the counter     TIMx_CNT has no effect on the outputs. ( this mode is used to generate a timing base )
.EQU  TIM9A12_CCMR1_OC1M_ACT , 1 << 4     @ Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM9A12_CCMR1_OC1M_INACT, 2 << 4    @ Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM9A12_CCMR1_OC1M_TOGGLE, 3 << 4    @ Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM9A12_CCMR1_OC1M_FORSEINACT, 4 << 4    @ Force inactive level - OC1REF is forced low.
.EQU  TIM9A12_CCMR1_OC1M_FORSEACT, 5 << 4    @ Force active level - OC1REF is forced high.
.EQU  TIM9A12_CCMR1_OC1M_PWM1, 6 << 4     @  PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1  else        inactive. In downcounting, channel 1 is inactive ( OC1REF = �0 ) as long as TIMx_CNT > TIMx_CCR1 else active ( OC1REF = 1 ) .
.EQU  TIM9A12_CCMR1_OC1M_PWM2, 7 << 4     @ PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else        active. In downcounting, channel 1 is active as long as TIMx_CNT > TIMx_CCR1 else inactive.
.EQU  TIM9A12_CCMR1_OC1PE    , 1 << 3     @ Output compare 1 preload enable
.EQU  TIM9A12_CCMR1_OC1FE    , 1 << 2     @ Output compare 1 fast enable
@.end

@.ITEM     TIM9A12_CCMR1_INPUT_CAPTURE_MODE
.EQU  TIM9A12_CCMR1_IC2F_N   , 12         @ Input capture 2 filter
.EQU  TIM9A12_CCMR1_IC2F_NOF , 0          @ No filter, sampling is done at fDTS
.EQU  TIM9A12_CCMR1_IC2F_N2  , 1 << 12    @ fSAMPLING=fCK_INT, N=2
.EQU  TIM9A12_CCMR1_IC2F_N4  , 2 << 12    @ fSAMPLING=fCK_INT, N=4
.EQU  TIM9A12_CCMR1_IC2F_N8  , 3 << 12    @ fSAMPLING=fCK_INT, N=8
.EQU  TIM9A12_CCMR1_IC2F_2N6 , 4 << 12    @ fSAMPLING=fDTS/2, N=6
.EQU  TIM9A12_CCMR1_IC2F_2N8 , 5 << 12    @ fSAMPLING=fDTS/2, N=8
.EQU  TIM9A12_CCMR1_IC2F_4N6 , 6 << 12    @ fSAMPLING=fDTS/4, N=6
.EQU  TIM9A12_CCMR1_IC2F_4N8 , 7 << 12    @ fSAMPLING=fDTS/4, N=8
.EQU  TIM9A12_CCMR1_IC2F_8N6 , 8 << 12    @ fSAMPLING=fDTS/8, N=6
.EQU  TIM9A12_CCMR1_IC2F_8N8 , 9 << 12    @ fSAMPLING=fDTS/8, N=8
.EQU  TIM9A12_CCMR1_IC2F_16N5, 10 << 12    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM9A12_CCMR1_IC2F_16N6, 11 << 12    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM9A12_CCMR1_IC2F_16N8, 12 << 12    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM9A12_CCMR1_IC2F_32N5, 13 << 12    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM9A12_CCMR1_IC2F_32N6, 14 << 12    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM9A12_CCMR1_IC2F_32N8, 15 << 12    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM9A12_CCMR1_IC2PSC_N , 8          @ Input capture 2 prescaler
.EQU  TIM9A12_CCMR1_IC2PSC_1 , 0          @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM9A12_CCMR1_IC2PSC_2 , 1 << 8     @ capture is done once every 2 events
.EQU  TIM9A12_CCMR1_IC2PSC_4 , 2 << 8     @ capture is done once every 4 events
.EQU  TIM9A12_CCMR1_IC2PSC_8 , 3 << 8     @ capture is done once every 8 events
.EQU  TIM9A12_CCMR1_IC1F_N   , 4          @ Input capture 1 filter
.EQU  TIM9A12_CCMR1_IC1F_NOF , 0          @ No filter, sampling is done at fDTS
.EQU  TIM9A12_CCMR1_IC1F_N2  , 1 << 4     @ fSAMPLING=fCK_INT, N=2
.EQU  TIM9A12_CCMR1_IC1F_N4  , 2 << 4     @ fSAMPLING=fCK_INT, N=4
.EQU  TIM9A12_CCMR1_IC1F_N8  , 3 << 4     @ fSAMPLING=fCK_INT, N=8
.EQU  TIM9A12_CCMR1_IC1F_2N6 , 4 << 4     @ fSAMPLING=fDTS/2, N=6
.EQU  TIM9A12_CCMR1_IC1F_2N8 , 5 << 4     @ fSAMPLING=fDTS/2, N=8
.EQU  TIM9A12_CCMR1_IC1F_4N6 , 6 << 4     @ fSAMPLING=fDTS/4, N=6
.EQU  TIM9A12_CCMR1_IC1F_4N8 , 7 << 4     @ fSAMPLING=fDTS/4, N=8
.EQU  TIM9A12_CCMR1_IC1F_8N6 , 8 << 4     @ fSAMPLING=fDTS/8, N=6
.EQU  TIM9A12_CCMR1_IC1F_8N8 , 9 << 4     @ fSAMPLING=fDTS/8, N=8
.EQU  TIM9A12_CCMR1_IC1F_16N5, 10 << 4    @ fSAMPLING=fDTS/16, N=5
.EQU  TIM9A12_CCMR1_IC1F_16N6, 11 << 4    @ fSAMPLING=fDTS/16, N=6
.EQU  TIM9A12_CCMR1_IC1F_16N8, 12 << 4    @ fSAMPLING=fDTS/16, N=8
.EQU  TIM9A12_CCMR1_IC1F_32N5, 13 << 4    @ fSAMPLING=fDTS/32, N=5
.EQU  TIM9A12_CCMR1_IC1F_32N6, 14 << 4    @ fSAMPLING=fDTS/32, N=6
.EQU  TIM9A12_CCMR1_IC1F_32N8, 15 << 4    @ fSAMPLING=fDTS/32, N=8
.EQU  TIM9A12_CCMR1_IC1PSC_N , 2          @ Input capture 3 prescaler
.EQU  TIM9A12_CCMR1_IC1PSC_1 , 0          @ no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM9A12_CCMR1_IC1PSC_2 , 1 << 2     @ capture is done once every 2 events
.EQU  TIM9A12_CCMR1_IC1PSC_4 , 2 << 2     @ capture is done once every 4 events
.EQU  TIM9A12_CCMR1_IC1PSC_8 , 3 << 2     @ capture is done once every 8 events
@.end

@.ITEM     TIM9A12_CCER
.EQU  TIM9A12_CCER_CC2NP     , 1 << 7     @ Capture/Compare 2 output Polarity refer to CC1NP description
.EQU  TIM9A12_CCER_CC2P      , 1 << 5     @ Capture/Compare 2 output Polarity refer to CC1P description
.EQU  TIM9A12_CCER_CC2E      , 1 << 4     @ Capture/Compare 2 output Polarity refer to CC1E description
.EQU  TIM9A12_CCER_CC1NP     , 1 << 3     @ Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity
                                       @ CC1 channel configured as output: CC1NP must be kept cleared
                                       @ CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define
                                       @ TI1FP1/TI2FP1 polarity (refer to CC1P description).
.EQU  TIM9A12_CCER_CC1P      , 1 << 1     @ Bit 1 CC1P: Capture/Compare 1 output Polarity.
                                       @ CC1 channel configured as output:
                                       @ 0: OC1 active high.
                                       @ 1: OC1 active low.
                                       @ CC1 channel configured as input:
                                       @ CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
                                       @ 00: noninverted/rising edge
                                       @ Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
                                       @ mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
                                       @ 01: inverted/falling edge
                                       @ Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
                                       @ mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
                                       @ 10: reserved, do not use this configuration.
                                       @ Note: 11: noninverted/both edges
                                       @ Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,
                                       @ external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This
                                       @ configuration must not be used for encoder mode.
.EQU  TIM9A12_CCER_CC1E      , 1 << 0     @ Bit 0 CC1E: Capture/Compare 1 output enable.
                                       @ CC1 channel configured as output:
                                       @ 0: Off - OC1 is not active.
                                       @ 1: On - OC1 signal is output on the corresponding output pin.
                                       @ CC1 channel configured as input:
                                       @ This bit determines if a capture of the counter value can actually be done into the input
                                       @ capture/compare register 1 (TIMx_CCR1) or not.
                                       @ 0: Capture disabled.
                                       @ 1: Capture enabled.
@.end

