@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                       Константы Flash control                    |
@ |                   для STM32F401xB/C и STM32F401xD/E              |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@ базовые константы микроконтроллера

@.item AHB1PERIPH_BASE
.EQU  FLASH_R_BASE  , AHB1PERIPH_BASE + 0x3C00
@.END

@.ITEM     FLASH_R_BASE
.EQU  FLASH_ACR     , 0x00       @ Flash access control register (FLASH_ACR)
.EQU  FLASH_KEYR    , 0x04       @ Flash key register (FLASH_KEYR)
.EQU  FLASH_OPTKEYR , 0x08       @ Flash option key register (FLASH_OPTKEYR)
.EQU  FLASH_SR      , 0x0C       @ Flash st atus re gister (FLASH_SR)
.EQU  FLASH_CR      , 0x10       @ Flash control register (FLASH_CR)
.EQU  FLASH_OPTCR   , 0x14       @ Flash option control register (FLASH_OPTCR)
@.END

@.item FLASH_ACR
.EQU  FLASH_ACR_LATENCY_N, 0     @ Bits 3:0 LATENCY: Latency
                                 @ These bits represent the ratio of the CPU clock period to the Flash memory access time
.EQU  FLASH_ACR_LATENCY_0, 0     @ 0000: Zero wait state
.EQU  FLASH_ACR_LATENCY_1, 1     @ 0001: One wait state
.EQU  FLASH_ACR_LATENCY_2, 2     @ 0010: Two wait states
.EQU  FLASH_ACR_LATENCY_3, 3     @ ...
.EQU  FLASH_ACR_LATENCY_4, 4     @ ...
.EQU  FLASH_ACR_LATENCY_5, 5     @ ...
.EQU  FLASH_ACR_LATENCY_6, 6     @ ...
.EQU  FLASH_ACR_LATENCY_7, 7     @ ...
.EQU  FLASH_ACR_LATENCY_8, 8     @ ...
.EQU  FLASH_ACR_LATENCY_9, 9     @ ...
.EQU  FLASH_ACR_LATENCY_10, 10   @ ...
.EQU  FLASH_ACR_LATENCY_11, 11   @ ...
.EQU  FLASH_ACR_LATENCY_12, 12   @ ...
.EQU  FLASH_ACR_LATENCY_13, 13   @ ...
.EQU  FLASH_ACR_LATENCY_14, 14   @ 1110: Fourteen wait states
.EQU  FLASH_ACR_LATENCY_15, 15   @ 1111: Fifteen wait states
.EQU  FLASH_ACR_PRFTEN_N, 8      @ Bit 8 PRFTEN: Prefetch enable
.EQU  FLASH_ACR_PRFTEN, 1 << 8   @ 1: Prefetch is enabled
                                 @ 0: Prefetch is disabled
.EQU  FLASH_ACR_ICEN_N, 9        @ Bit 9 ICEN: Instruction cache enable
                                 @ 0: Instruction cache is disabled
.EQU  FLASH_ACR_ICEN, 1 << 9     @ 1: Instruction cache is enabled
.EQU  FLASH_ACR_DCEN_N, 10       @ Bit 10 DCEN: Data cache enable
                                 @ 0: Data cache is disabled
.EQU  FLASH_ACR_DCEN, 1 << 10    @ 1: Data cache is enabled
.EQU  FLASH_ACR_ICRST_N, 11      @ Bit 11 ICRST: Instruction cache reset
                                 @ 0: Instruction cache is not reset
.EQU  FLASH_ACR_ICRST, 1 << 11   @ 1: Instruction cache is reset
                                 @ This bit can be written only when the I cache is disabled.
.EQU  FLASH_ACR_DCRST_N, 12      @ Bit 12 DCRST: Data cache reset
                                 @ 0: Data cache is not reset
.EQU  FLASH_ACR_DCRST, 12        @ 1: Data cache is reset
                                 @ This bit can be written only when the D cache is disabled
@.END

@.item FLASH_KEYR
.equ FLASH_KEYR_FKEYR_K1        ,  0x45670123 @ Key1
.equ FLASH_KEYR_FKEYR_K2        ,  0xCDEF89AB @ Key2
@.END

@.item FLASH_OPTKEYR
.equ FLASH_OPTKEYR_OPTKEYR_K1   ,  0x08192A3B @ OPTKEY1
.equ FLASH_OPTKEYR_OPTKEYR_K2   ,  0x4C5D6E7F @ OPTKEY2
@.END

@.item FLASH_SR
.EQU  FLASH_SR_EOP_N, 0          @ Bit 0 EOP: End of operation
                                 @ Set by hardware when one or more Flash memory operations (program/erase) has/have
                                 @ completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE = 1).
.EQU  FLASH_SR_EOP  , 1          @ Cleared by writing a 1.
.EQU  FLASH_SR_OPERR_N, 1        @ Bit 1 OPERR: Operation error
.EQU  FLASH_SR_OPERR, 1 << 1     @ Set by hardware when a flash operation (programming / erase /read) request is detected and
                                 @ can not be run because of parallelism, alignment, or write protection error. This bit is set only if
                                 @ error interrupts are enabled (ERRIE = 1).
.EQU  FLASH_SR_WRPERR_N, 4       @ Bit 4 WRPERR: Write protection error
                                 @ Set by hardware when an address to be erased/programmed belongs to a write-protected part
                                 @ of the Flash memory.
.EQU  FLASH_SR_WRPERR, 1 << 4    @ Cleared by writing 1.
.EQU  FLASH_SR_PGAERR_N, 5       @ Bit 5 PGAERR: Programming alignment error
                                 @ Set by hardware when the data to program cannot be contained in the same 128-bit Flash
                                 @ memory row.
.EQU  FLASH_SR_PGAERR, 1 << 5    @ Cleared by writing 1.
.EQU  FLASH_SR_PGPERR_N, 6       @ Bit 6 PGPERR: Programming parallelism error
                                 @ Set by hardware when the size of the access (byte, half-word, word, double word) during the
                                 @ program sequence does not correspond to the parallelism configuration PSIZE (x8, x16, x32,
                                 @ x64).
.EQU  FLASH_SR_PGPERR, 1 << 6    @ Cleared by writing 1.
.EQU  FLASH_SR_PGSERR_N, 7       @ Bit 7 PGSERR: Programming sequence error
                                 @ Set by hardware when a write access to the Flash memory is performed by the code while the
                                 @ control register has not been correctly configured.
.EQU  FLASH_SR_PGSERR, 1 << 7    @ Cleared by writing 1
.EQU  FLASH_SR_RDERR_N, 8        @ Bit 8 RDERR: Read Protection Error (pcrop)
                                 @ Set by hardware when an address to be read through the Dbus belongs to a read protected
                                 @ part of the flash.
.EQU  FLASH_SR_RDERR, 1 << 8     @ Reset by writing 1.
.EQU  FLASH_SR_BSY_N, 16         @ Bit 16 BSY: Busy
                                 @ This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
                                 @ Flash memory operation and cleared when the operation finishes or an error occurs.
                                 @ 0: no Flash memory operation ongoing
.EQU  FLASH_SR_BSY  , 1 << 16    @ 1: Flash memory operation ongoing
@.END

@.item FLASH_CR
.EQU  FLASH_CR_Reset_Value, 0x80000000    @ Значение регистра по умолчанию
.EQU  FLASH_CR_PG_N , 0          @ Bit 0 PG: Programming
.EQU  FLASH_CR_PG   , 1          @ Flash programming activated.
.EQU  FLASH_CR_SER_N, 1          @ Bit 1 SER: Sector Erase
.EQU  FLASH_CR_SER  , 1 << 1     @ Sector Erase activated.
.EQU  FLASH_CR_MER_N, 2          @ Bit 2 MER: Mass Erase
.EQU  FLASH_CR_MER  , 1 << 2     @ Erase activated for all user sectors.
.EQU  FLASH_CR_SNB_N, 3          @ Bits 6:3 SNB[3:0]: Sector number
                                 @ These bits select the sector to erase.
                                 @ 0000 sector 0
                                 @ 0001 sector 1
                                 @ ...
                                 @ 0101 sector 5
                                 @ 0110 sector 6 (STM32F401xD/E devices only)
                                 @ 0111 sector 7 (STM32F401xE devices only)
                                 @ 1000 not allowed
                                 @ ...
                                 @ 1011 not allowed
                                 @ 1100 user specific sector
                                 @ 1101 user configuration sector
                                 @ 1110 not allowed
                                 @ 1111 not allowed
.EQU  FLASH_CR_PSIZE_N, 8        @ Bits 9:8 PSIZE[1:0]: Program size
                                 @ These bits select the program parallelism.
.EQU  FLASH_CR_PSIZE_8, 0        @ 00 program x8
.EQU  FLASH_CR_PSIZE_16, 1 << 8  @ 01 program x16
.EQU  FLASH_CR_PSIZE_32, 2 << 8  @ 10 program x32
.EQU  FLASH_CR_PSIZE_64, 3 << 8  @ 11 program x64
.EQU  FLASH_CR_STRT_N, 16        @ Bit 16 STRT: Start
.EQU  FLASH_CR_STRT , 1 << 16    @ This bit triggers an erase operation when set. It is set only by software and cleared when the
                                 @ BSY bit is cleared.
.EQU  FLASH_CR_EOPIE_N, 24       @ Bit 24 EOPIE: End of operation interrupt enable
                                 @ This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1.
                                 @ 0: Interrupt generation disabled
.EQU  FLASH_CR_EOPIE, 1 << 24    @ 1: Interrupt generation enabled
.EQU  FLASH_CR_ERRIE_N, 25       @ Bit 25 ERRIE: Error interrupt enable
                                 @ This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set
                                 @ to 1.
                                 @ 0: Error interrupt generation disabled
.EQU  FLASH_CR_ERRIE, 1 << 25    @ 1: Error interrupt generation enabled
.EQU  FLASH_CR_LOCK_N, 31        @ Bit 31 LOCK: Lock
.EQU  FLASH_CR_LOCK , 1 << 31    @ Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
                                 @ cleared by hardware after detecting the unlock sequence.
                                 @ In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
@.END

@.item FLASH_OPTCR
.equ FLASH_OPTCR_Reset_Value    , 0x0FFFAAED @ Значение регистра по умолчанию
.EQU  FLASH_OPTCR_OPTLOCK_N, 0   @ Bit 0 OPTLOCK: Option lock
.EQU  FLASH_OPTCR_OPTLOCK, 1     @ Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This
                                 @ bit is cleared by hardware after detecting the unlock sequence.
                                 @ In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
.EQU  FLASH_OPTCR_OPTSTRT_N, 1    @ Bit 1 OPTSTRT: Option start
                                  @ This bit triggers a user option operation when set. It is set only by software and cleared when
.EQU  FLASH_OPTCR_OPTSTRT, 1 << 1 @ the BSY bit is cleared.
.EQU  FLASH_OPTCR_BOR_LEV_N, 2    @ Bits 3:2 BOR_LEV[1:0]: BOR reset Level
                                  @ These bits contain the supply level threshold that activates/releases the reset. They can be
                                  @ written to program a new BOR level. By default, BOR is off. When the supply voltage (VDD)
                                  @ drops below the selected BOR level, a device reset is generated.
.EQU  FLASH_OPTCR_BOR_LEV_0, 0      @ 00: BOR Level 3 (VBOR3), brownout threshold level 3
.EQU  FLASH_OPTCR_BOR_LEV_1, 1 << 2 @ 01: BOR Level 2 (VBOR2), brownout threshold level 2
.EQU  FLASH_OPTCR_BOR_LEV_2, 2 << 2 @ 10: BOR Level 1 (VBOR1), brownout threshold level 1
.EQU  FLASH_OPTCR_BOR_LEV_3, 3 << 2 @ 11: BOR off, POR/PDR reset threshold level is applied
                            @ Note: For full details about BOR characteristics, refer to the “Electrical characteristics” section
                                 @ in the device datasheet.
.EQU  FLASH_OPTCR_USER_N, 5      @ Bits 7:5 USER[2:0]: User option bytes
                                 @ These bits contain the value of the user option byte after reset. They can be written to program
                                 @ a new user option byte value into Flash memory.
.EQU  FLASH_OPTCR_USER_STDBY, 1 << 7  @ Bit 7: nRST_STDBY
.EQU  FLASH_OPTCR_USER_STOP, 1 << 6   @ Bit 6: nRST_STOP
.EQU  FLASH_OPTCR_USER_SW, 1 << 5     @ Bit 5: WDG_SW
                         @ @ Note: When changing the WDG mode from hardware to software or from software to
                                 @ hardware, a system reset is required to make the change effective.
.EQU  FLASH_OPTCR_RDP_N, 8       @ Bits 15:8 RDP[7:0]: Read protect
                                 @ These bits contain the value of the read-protection option level after reset. They can be written
                                 @ to program a new read protection value into Flash memory.
                                 @ 0xAA: Level 0, read protection not active
                                 @ 0xCC: Level 2, chip read protection active
                                 @ Others: Level 1, read protection of memories active
.EQU  FLASH_OPTCR_nWRP16_N, 16   @ Bits 21:16 nWRP[5:0]: Not write protect
                                 @ These bits contain the value of the write-protection option bytes of sectors after reset. They
                                 @ can be written to program a new write protect value into Flash memory.
                                 @ 0: Write protection active on selected sector
                                 @ 1: Write protection not active on selected sector
                                 @ These bits contain the value of the write-protection and read-protection (PCROP) option
                                 @ bytes for sectors 0 to 5 after reset. They can be written to program a new write-protect or
                                 @ PCROP value into Flash memory.
                                 @ If SPRMOD is reset:
                                 @ 0: Write protection active on sector i
                                 @ 1: Write protection not active on sector i
                                 @ If SPRMOD is set:
                                 @ 0: PCROP protection not active on sector i
                                 @ 1: PCROP protection active on sector i
.EQU  FLASH_OPTCR_nWRP22_N, 22   @ Bits 23:22 nWRP[7:6]: Not write protect
                                 @ For STM32F401xB/C:
                                 @ Reserved, must be kept cleared.
                                 @ For STM32F401xD/E:
                                 @ These bits contain the value of the write-protection and read-protection (PCROP) option
                                 @ bytes for sectors 6 and 7 after reset. (Refer to Bits 21:16 for more details)
.EQU  FLASH_OPTCR_SPRMOD_N, 31   @ Bit 31 SPRMOD: Selection of Protection Mode of nWPRi bits
                                 @ 0: PCROP disabled, nWPRi bits used for Write Protection on sector i
.EQU  FLASH_OPTCR_SPRMOD, 1 << 31    @ 1: PCROP enabled, nWPRi bits used for PCROP Protection on sector i
@.END

