@.CHARSET CP1251

@ +----------------------------------------------------+
@ |             Оределения PWR (раздел 6.4)            |
@ |             STM32F030xCx / STM32F070xBx            |
@ +----------------------------------------------------+

.include "/src/inc/base.inc"

@.ITEM     APBPERIPH_BASE
.EQU  PWR_BASE      , APBPERIPH_BASE + 0x7000
.EQU  PWR           , PERIPH_BASE + PWR_BASE
@.END

@.ITEM     PWR_BASE  PWR
.EQU  PWR_CR        , 0x00    @ Power control register (PWR_CR)
.EQU  PWR_CSR       , 0x04    @ Power control/status register (PWR_CSR)
@.END

@.ITEM     PWR_CR
.EQU  PWR_CR_DBP    , 1 << 8    @ Bit 8 DBP: Disable RTC domain write protection.
                                @ In reset state, the RTC registers are protected against parasitic write access. This bit must be
                                @ set to enable write access to these registers.
                                @ 0: Access to RTC disabled
                                @ 1: Access to RTC enabled
.EQU  PWR_CR_CSBF   , 1 << 3    @ Bit 3 CSBF: Clear standby flag.
                                @ This bit is always read as 0.
                                @ 0: No effect
                                @ 1: Clear the SBF Standby Flag (write).
.EQU  PWR_CR_CWUF   , 1 << 2    @ Bit 2 CWUF: Clear wakeup flag.
                                @ This bit is always read as 0.
                                @ 0: No effect
                                @ 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
.EQU  PWR_CR_PDDS   , 1 << 1    @ Bit 1 PDDS: Power down deepsleep.
                                @ This bit is set and cleared by software. It works together with the LPDS bit.
                                @ 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
                                @ LPDS bit.
                                @ 1: Enter Standby mode when the CPU enters Deepsleep.
.EQU  PWR_CR_LPDS   , 1       @ Bit 0 LPDS: Low-power deepsleep.
                              @ This bit is set and cleared by software. It works together with the PDDS bit.
                              @ 0: Voltage regulator on during Stop mode
                              @ 1: Voltage regulator in low-power mode during Stop mode
@ Note: When a peripheral that can work in STOP mode requires a clock, the Power controller
@ automatically switch the voltage regulator from Low-power mode to Normal mode and
@ remains in this mode until the request disappears.
@.END

@.ITEM PWR_CSR
@ Bits 14:11 EWUPx: Enable WKUPx pin (available only on STM32F070xB and STM32F030xC devices)
@ These bits are set and cleared by software.
@ 0: WKUPx pin is used for general purpose I/O. An event on the WKUPx pin does not wakeup
@ the device from Standby mode.
@ 1: WKUPx pin is used for wakeup from Standby mode and forced in input pull down
@ configuration (rising edge on WKUPx pin wakes-up the system from Standby mode).
@ Note: These bits are reset by a system Reset.
.EQU  PWR_CSR_EWUP7 , 1 << 14     @ @ Bit 14 EWUPx: Enable WKUP14 pin
.EQU  PWR_CSR_EWUP6 , 1 << 13     @ @ Bit 13 EWUPx: Enable WKUP13 pin
.EQU  PWR_CSR_EWUP5 , 1 << 12     @ @ Bit 12 EWUPx: Enable WKUP12 pin
.EQU  PWR_CSR_EWUP4 , 1 << 11     @ @ Bit 11 EWUPx: Enable WKUP11 pin
@ Bits 9:8 EWUPx: Enable WKUPx pin
@ These bits are set and cleared by software.
@ 0: WKUPx pin is used for general purpose I/O. An event on the WKUPx pin does not wakeup
@ the device from Standby mode.
@ 1: WKUPx pin is used for wakeup from Standby mode and forced in input pull down
@ configuration (rising edge on WKUPx pin wakes-up the system from Standby mode).
@ Note: These bits are reset by a system Reset.
.EQU  PWR_CSR_EWUP  , 1 << 9      @ @ Bit 9 EWUPx: Enable WKUP9 pin
.EQU  PWR_CSR_EWUP  , 1 << 8      @ @ Bit 8 EWUPx: Enable WKUP8 pin
.EQU  PWR_CSR_SBF   , 1 << 2 @ Bit 1 SBF: Standby flag
                             @ This bit is set by hardware when the device enters Standby mode and it is cleared only by a
                             @ POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control
                             @ register (PWR_CR)
                             @ 0: Device has not been in Standby mode
                             @ 1: Device has been in Standby mode
.EQU  PWR_CSR_WUF   , 1       @ Bit 0 WUF: Wakeup flag
                             @ This bit is set by hardware to indicate that the device received a wakeup event. It is cleared by
                             @ a system reset or by setting the CWUF bit in the Power control register (PWR_CR)
                             @ 0: No wakeup event occurred
                             @ 1: A wakeup event was received from one of the enabled WKUPx pins or from the RTC
                             @ alarm.
                             @ Note: An additional wakeup event is detected if one WKUPx pin is enabled (by setting the
                             @ EWUPx bit) when its pin level is already high.
@.END



