@GNU AS
@.CharSet=CP1251 (Cyrillic)
@.desc type=module
@ +------------------------------------------------------------------+
@ |                     Базовые константы TIM2 - TIM5                |
@ +------------------------------------------------------------------+
@.enddesc

.include "/src/inc/base.inc"

@.ITEM     APB1PERIPH_BASE
.EQU  TIM6_BASE          , APB1PERIPH_BASE + 0x1000
.EQU  TIM7_BASE          , APB1PERIPH_BASE + 0x1400
.EQU  TIM6               , PERIPH_BASE + TIM6_BASE
.EQU  TIM7               , PERIPH_BASE + TIM7_BASE

@.ITEM     TIM6_BASE TIM7_BASE TIM6 TIM7
.EQU  TIM6_7_CR1         , 0x00
.EQU  TIM6_7_CR2         , 0x04
.EQU  TIM6_7_DIER        , 0x0C
.EQU  TIM6_7_SR          , 0x10
.EQU  TIM6_7_EGR         , 0x14
.EQU  TIM6_7_CNT         , 0x24
.EQU  TIM6_7_PSC         , 0x28
.EQU  TIM6_7_ARR         , 0x2C


@.ITEM     TIM6_7_CR1
.EQU  TIM6_7_CR1_APRE    , 1 << 7     @ Auto-reload preload enable
.EQU  TIM6_7_CR1_OPM     , 1 << 3     @ One-pulse mode
.EQU  TIM6_7_CR1_URS     , 1 << 2     @ Update request source
.EQU  TIM6_7_CR1_UDIS    , 1 << 1     @ Update disable
.EQU  TIM6_7_CR1_CEN     , 1          @ Counter enable

@.ITEM     TIM6_7_CR2
.EQU  TIM6_7_CR2_MMS_N   , 1 << 4     @  Master mode selection
.EQU  TIM6_7_CR2_MMS_RST , 0          @ Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input ( slave mode controller configured in reset mode ) then the signal on TRGO is delayed compared to the actual reset
.EQU  TIM6_7_CR2_MMS_ENB , 1 << 4     @  Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
.EQU  TIM6_7_CR2_MMS_UPD , 2 << 4     @ Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer

@.ITEM     TIM6_7_DIER
.EQU  TIM6_7_DIER_UDE    , 1 << 8     @ Update DMA request enable
.EQU  TIM6_7_DIER_UIE    , 1          @ Update interrupt enable

@.ITEM     TIM6_7_SR
.EQU  TIM6_7_SR_UIF      , 1          @  Update interrupt flag

@.ITEM     TIM6_7_EGR
.EQU  TIM6_7_EGR_UG      , 1          @ Update generation



