@GNU AS
@.CharSet=CP1251 (Cyrillic)

@.ITEM     TIM6_BASE TIM7_BASE TIM6 TIM7
.EQU  TIM6T7_CR1         , 0x00      @ TIM6/TIM7 control register 1 (TIMx_CR1)
.EQU  TIM6T7_DIER        , 0x0C      @ TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)
.EQU  TIM6T7_SR          , 0x10      @ TIM6/TIM7 status register (TIMx_SR)
.EQU  TIM6T7_EGR         , 0x14      @ TIM6/TIM7 event generation register (TIMx_EGR)
.EQU  TIM6T7_CNT         , 0x24      @ TIM6/TIM7 counter (TIMx_CNT)
.EQU  TIM6T7_PSC         , 0x28      @ TIM6/TIM7 prescaler (TIMx_PSC)
.EQU  TIM6T7_ARR         , 0x2C      @ TIM6/TIM7 auto-reload register (TIMx_ARR)


@.ITEM     TIM6T7_CR1
.EQU  TIM6T7_CR1_APRE    , 1 << 7     @ Bit 7 ARPE: Auto-reload preload enable
                                      @ 0: TIMx_ARR register is not buffered.
                                      @ 1: TIMx_ARR register is buffered.
.EQU  TIM6T7_CR1_OPM     , 1 << 3     @ Bit 3 OPM: One-pulse mode
                                      @ 0: Counter is not stopped at update event
                                      @ 1: Counter stops counting at the next update event (clearing the CEN bit).
.EQU  TIM6T7_CR1_URS     , 1 << 2     @ Bit 2 URS: Update request source
                                      @ This bit is set and cleared by software to select the UEV event sources.
                                      @ 0: Any of the following events generates an update interrupt or DMA request if enabled.
                                      @ These events can be:
                                      @  Counter overflow/underflow
                                      @  Setting the UG bit
                                      @  Update generation through the slave mode controller
                                      @ 1: Only counter overflow/underflow generates an update interrupt or DMA request if
                                      @ enabled.
.EQU  TIM6T7_CR1_UDIS    , 1 << 1     @ Bit 1 UDIS: Update disable
                                      @ This bit is set and cleared by software to enable/disable UEV event generation.
                                      @ 0: UEV enabled. The Update (UEV) event is generated by one of the following events:
                                      @  Counter overflow/underflow
                                      @  Setting the UG bit
                                      @  Update generation through the slave mode controller
                                      @ Buffered registers are then loaded with their preload values.
                                      @ 1: UEV disabled. The Update event is not generated, shadow registers keep their value
                                      @ (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
                                      @ a hardware reset is received from the slave mode controller.
.EQU  TIM6T7_CR1_CEN     , 1          @ Bit 0 CEN: Counter enable
                                      @ 0: Counter disabled
                                      @ 1: Counter enabled
                                      @ Note: Gated mode can work only if the CEN bit has been previously set by software.
                                      @ However trigger mode can set the CEN bit automatically by hardware.
                                      @ CEN is cleared automatically in one-pulse mode, when an update event occurs.
@.end

@.ITEM     TIM6T7_DIER
.EQU  TIM6T7_DIER_UDE    , 1 << 8     @ Bit 8 UDE: Update DMA request enable
                                      @ 0: Update DMA request disabled.
                                      @ 1: Update DMA request enabled.
.EQU  TIM6T7_DIER_UIE    , 1          @ Bit 0 UIE: Update interrupt enable
                                      @ 0: Update interrupt disabled.
                                      @ 1: Update interrupt enabled.
@.end

@.ITEM     TIM6T7_SR
.EQU  TIM6T7_SR_UIF      , 1          @  Bit 0 UIF: Update interrupt flag
                                      @ This bit is set by hardware on an update event. It is cleared by software.
                                      @ 0: No update occurred.
                                      @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                      @ At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
                                      @ TIMx_CR1 register.
                                      @ When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if
                                      @ URS = 0 and UDIS = 0 in the TIMx_CR1 register.
@.end

@.ITEM     TIM6T7_EGR
.EQU  TIM6T7_EGR_UG      , 1          @ Bit 0 UG: Update generation
                                      @ This bit can be set by software, it is automatically cleared by hardware.
                                      @ 0: No action.
                                      @ 1: Re-initializes the timer counter and generates an update of the registers. Note that the
                                      @ prescaler counter is cleared too (but the prescaler ratio is not affected).
@.end



