@GNU AS
@.CharSet=CP1251 (Cyrillic)

@.desc type=module
@ +------------------------------------------------------------------+
@ |                Определения Trace Port Interface                  |
@ |                            CORTEX-M4                             |
@ +------------------------------------------------------------------+
@.enddesc

.include    "/src/inc/base.inc"

@.item MCU_IDCODE
.equ MCU_IDCODE_DEV_ID_N             , 0
.equ MCU_IDCODE_DEV_ID_M             , 0x0FFF << MCU_IDCODE_DEV_ID_N
.equ MCU_IDCODE_DEV_ID_low_density   , 0x0412
.equ MCU_IDCODE_DEV_ID_medium_density, 0x0410
.equ MCU_IDCODE_DEV_ID_high_density  , 0x0414
.equ MCU_IDCODE_DEV_ID_XL_density    , 0x0430
.equ MCU_IDCODE_DEV_ID_connectivity  , 0x0418
.equ MCU_IDCODE_REV_ID_N                       , 16
.equ MCU_IDCODE_REV_ID_M                       , 0xFFFF << MCU_IDCODE_REV_ID_N
.equ MCU_IDCODE_REV_ID_low_density_Rev_A       , 0x10000000
.equ MCU_IDCODE_REV_ID_medium_density_Rev_A    , 0x0
.equ MCU_IDCODE_REV_ID_medium_density_Rev_B    , 0x20000000
.equ MCU_IDCODE_REV_ID_medium_density_Rev_Z    , 0x20010000
.equ MCU_IDCODE_REV_ID_medium_density_Rev_123XY, 0x20030000
.equ MCU_IDCODE_REV_ID_high_density_Rev_A1     , 0x10000000
.equ MCU_IDCODE_REV_ID_high_density_Rev_Z      , 0x10010000
.equ MCU_IDCODE_REV_ID_high_density_Rev123XY   , 0x10030000
.equ MCU_IDCODE_REV_ID_XL_density_Rev_A1       , 0x10000000
.equ MCU_IDCODE_REV_ID_connectivity_Rev_A      , 0x10000000
.equ MCU_IDCODE_REV_ID_connectivity_Rev_Z      , 0x10010000
@.end


@.item TPI_BASE
.equ TPI_SSPSR     , 0x000   @ (R)  Supported Parallel Port Size Register
.equ TPI_CSPSR     , 0x004   @ (R/W)  Current Parallel Port Size Register
.equ TPI_ACPR      , 0x010   @ (R/W)  Asynchronous Clock Prescaler Register
.equ TPI_SPPR      , 0x0F0   @ (R/W)  Selected Pin Protocol Register
.equ TPI_FFSR      , 0x300   @ (R)  Formatter and Flush Status Register
.equ TPI_FFCR      , 0x304   @ (R/W)  Formatter and Flush Control Register
.equ TPI_FSCR      , 0x308   @ (R)  Formatter Synchronization Counter Register
.equ TPI_TRIGGER   , 0xEE8   @ (R)  TRIGGER Register
.equ TPI_FIFO0     , 0xEEC   @ (R)  Integration ETM Data
.equ TPI_ITATBCTR2 , 0xEF0   @ (R)  ITATBCTR2
.equ TPI_ITATBCTR0 , 0xEF8   @ (R)  ITATBCTR0
.equ TPI_FIFO1     , 0xEFC   @ (R)  Integration ITM Data
.equ TPI_ITCTRL    , 0xF00   @ (R/W)  Integration Mode Control
.equ TPI_CLAIMSET  , 0xFA0   @ (R/W)  Claim tag set
.equ TPI_CLAIMCLR  , 0xFA4   @ (R/W)  Claim tag clear
.equ TPI_DEVID     , 0xFC8   @ (R)  TPIU_DEVID
.equ TPI_DEVTYPE   , 0xFCC   @ (R)  TPIU_DEVTYPE
@.end

@.item TPI_ACPR
.equ TPI_ACPR_PRESCALER_N     , 0
.equ TPI_ACPR_PRESCALER_M     , 0x1FFF << TPI_ACPR_PRESCALER_N
@.end

@.item TPI_SPPR
.equ TPI_SPPR_TXMODE_N        , 0
.equ TPI_SPPR_TXMODE_M        , 3 << TPI_SPPR_TXMODE_N
@.end

@.item TPI_FFSR
.equ TPI_FFSR_FtNonStop_N     , 3
.equ TPI_FFSR_FtNonStop       , 1 << TPI_FFSR_FtNonStop_N
.equ TPI_FFSR_TCPresent_N     , 2
.equ TPI_FFSR_TCPresent       , 1 << TPI_FFSR_TCPresent_N
.equ TPI_FFSR_FtStopped_N     , 1
.equ TPI_FFSR_FtStopped       , 1 << TPI_FFSR_FtStopped_N
.equ TPI_FFSR_FlInProg_N      , 0
.equ TPI_FFSR_FlInProg        , 1 << TPI_FFSR_FlInProg_N
@.end

@.item TPI_FFCR
.equ TPI_FFCR_TrigIn_N        , 8
.equ TPI_FFCR_TrigIn          , 1 << TPI_FFCR_TrigIn_N
.equ TPI_FFCR_EnFCont_N       , 1
.equ TPI_FFCR_EnFCont         , 1 << TPI_FFCR_EnFCont_N
@.end

@.item TPI_TRIGGER
.equ TPI_TRIGGER_TRIGGER_N    , 0
.equ TPI_TRIGGER_TRIGGER      , 1 << TPI_TRIGGER_TRIGGER_N
@.end

@.item TPI_FIFO0
.equ TPI_FIFO0_ITM_ATVALID_N  , 29
.equ TPI_FIFO0_ITM_ATVALID_M  , 3 << TPI_FIFO0_ITM_ATVALID_N
.equ TPI_FIFO0_ITM_bytecount_N, 27
.equ TPI_FIFO0_ITM_bytecount_M, 3 << TPI_FIFO0_ITM_bytecount_N
.equ TPI_FIFO0_ETM_ATVALID_N  , 26
.equ TPI_FIFO0_ETM_ATVALID_M  , 3 << TPI_FIFO0_ETM_ATVALID_N
.equ TPI_FIFO0_ETM_bytecount_N, 24
.equ TPI_FIFO0_ETM_bytecount_M, 3 << TPI_FIFO0_ETM_bytecount_N
.equ TPI_FIFO0_ETM2_N         , 16
.equ TPI_FIFO0_ETM2_M         , 0xFF << TPI_FIFO0_ETM2_N
.equ TPI_FIFO0_ETM1_N         , 8
.equ TPI_FIFO0_ETM1_M         , 0xFF << TPI_FIFO0_ETM1_N
.equ TPI_FIFO0_ETM0_N         , 0
.equ TPI_FIFO0_ETM0_M         , 0xFF << TPI_FIFO0_ETM0_N
@.end

@.item TPI_ITATBCTR2
.equ TPI_ITATBCTR2_ATREADY2_N , 0
.equ TPI_ITATBCTR2_ATREADY2   , 1 << TPI_ITATBCTR2_ATREADY2_N
.equ TPI_ITATBCTR2_ATREADY1_N , 0
.equ TPI_ITATBCTR2_ATREADY1   , 1 << TPI_ITATBCTR2_ATREADY1_N
@.end

@.item TPI_FIFO1
.equ TPI_FIFO1_ITM_ATVALID_N  , 29
.equ TPI_FIFO1_ITM_ATVALID_M  , 3 << TPI_FIFO1_ITM_ATVALID_N
.equ TPI_FIFO1_ITM_bytecount_N, 27
.equ TPI_FIFO1_ITM_bytecount_M, 3 << TPI_FIFO1_ITM_bytecount_N
.equ TPI_FIFO1_ETM_ATVALID_N  , 26
.equ TPI_FIFO1_ETM_ATVALID_M  , 3 << TPI_FIFO1_ETM_ATVALID_N
.equ TPI_FIFO1_ETM_bytecount_N, 24
.equ TPI_FIFO1_ETM_bytecount_M, 3 << TPI_FIFO1_ETM_bytecount_N
.equ TPI_FIFO1_ITM2_N         , 16
.equ TPI_FIFO1_ITM2_M         , 0xFF << TPI_FIFO1_ITM2_N
.equ TPI_FIFO1_ITM1_N         , 8
.equ TPI_FIFO1_ITM1_M         , 0xFF << TPI_FIFO1_ITM1_N
.equ TPI_FIFO1_ITM0_N         , 0
.equ TPI_FIFO1_ITM0_M         , 0xFF << TPI_FIFO1_ITM0_N
@.end

@.item TPI_ITATBCTR0
.equ TPI_ITATBCTR0_ATREADY2_N , 0
.equ TPI_ITATBCTR0_ATREADY2   , 1 << TPI_ITATBCTR0_ATREADY2_N
.equ TPI_ITATBCTR0_ATREADY1_N , 0
.equ TPI_ITATBCTR0_ATREADY1   , 1 << TPI_ITATBCTR0_ATREADY1_N
@.end

@.item TPI_ITCTRL
.equ TPI_ITCTRL_Mode_N        , 0
.equ TPI_ITCTRL_Mode_M        , 3 << TPI_ITCTRL_Mode_N
@.end

@.item TPI_DEVID
.equ TPI_DEVID_NRZVALID_N     , 11
.equ TPI_DEVID_NRZVALID       , 1 << TPI_DEVID_NRZVALID_N         @ Asynchronous Serial Wire Output (NRZ)
.equ TPI_DEVID_MANCVALID_N    , 10
.equ TPI_DEVID_MANCVALID      , 1 << TPI_DEVID_MANCVALID_N        @ Asynchronous Serial Wire Output (Manchester)
.equ TPI_DEVID_PTINVALID_N    , 9
.equ TPI_DEVID_PTINVALID      , 1 << TPI_DEVID_PTINVALID_N        @ Trace data and clock modes
.equ TPI_DEVID_MinBufSz_N     , 6
.equ TPI_DEVID_MinBufSz_M     , 0x7 << TPI_DEVID_MinBufSz_N       @ Minimum buffer size
.equ TPI_DEVID_AsynClkIn_N    , 5
.equ TPI_DEVID_AsynClkIn      , 1 << TPI_DEVID_AsynClkIn_N        @ Asynchronous TRACECLKIN
.equ TPI_DEVID_NrTraceInput_N , 0
.equ TPI_DEVID_NrTraceInput_M , 0x1F << TPI_DEVID_NrTraceInput_N  @ Number of trace inputs
@.end

@.item TPI_DEVTYPE
.equ TPI_DEVTYPE_SubType_N    , 4
.equ TPI_DEVTYPE_SubType_M    , 0xF << TPI_DEVTYPE_SubType_N    @ Sub type
.equ TPI_DEVTYPE_MajorType_N  , 0
.equ TPI_DEVTYPE_MajorType_M  , 0xF << TPI_DEVTYPE_MajorType_N  @ Major type
@.end
