@.CHARSET =CP1251 ( Cyrillic )
@GNU AS

@.desc type=module
@ +------------------------------------------------------------------+
@ |                  Áàçîâûå êîíñòàíòû TIMER 16 - 17                 |
@ |                             STM32F0x0                            |
@ +------------------------------------------------------------------+
@.enddesc

.INCLUDE   "/src/inc/base.inc"

@.ITEM     APBPERIPH_BASE
.EQU  TIM16_BASE    , APBPERIPH_BASE + 0x014400
.EQU  TIM16         , PERIPH_BASE + TIM16_BASE
.EQU  TIM17_BASE    , APBPERIPH_BASE + 0x014800
.EQU  TIM17         , PERIPH_BASE + TIM17_BASE
@.end

@.ITEM     TIM16 TIM16_BASE TIM17 TIM17_BASE
.EQU  TIM16T17_CR1  , 0x00    @ TIM16T17 control register 1 (TIMx_CR1)
.EQU  TIM16T17_CR2  , 0x04    @ TIM16T17 control register 2 (TIMx_CR2)
.EQU  TIM16T17_DIER , 0X0C    @ TIM16T17 DMA/interrupt enable register (TIMx_DIER)
.EQU  TIM16T17_SR   , 0X10    @ TIM16T17 status register (TIMx_SR)
.EQU  TIM16T17_EGR  , 0X14    @ TIM16T17 event generation register (TIMx_EGR)
.EQU  TIM16T17_CCMR1, 0X18    @ TIM16T17 capture/compare mode register 1 (TIMx_CCMR1)
.EQU  TIM16T17_CCER , 0X20    @ TIM16T17 capture/compare enable register (TIMx_CCER)
.EQU  TIM16T17_CNT  , 0X24    @ TIM16T17 counter ( TIMx_CNT)
.EQU  TIM16T17_PSC  , 0X28    @ TIM16T17 prescaler ( TIMx_PSC)
.EQU  TIM16T17_ARR  , 0X2C    @ TIM16T17 auto-reload register (TIMx_ARR)
.EQU  TIM16T17_RCR  , 0X30    @ TIM16T17 repetition counter register (TIMx_RCR)
.EQU  TIM16T17_CCR1 , 0X34    @ TIM16T17 capture/compare register 1 (TIMx_CCR1)
.EQU  TIM16T17_BDTR , 0X44    @ TIM16T17 break and dead-time register (TIMx_BDTR)
.EQU  TIM16T17_DCR  , 0X48    @ TIM16T17 DMA control register (TIMx_DCR)
.EQU  TIM16T17_DMAR , 0X4C    @ TIM16T17 DMA address for full transfer (TIMx_DMAR)
@.end

@.ITEM     TIM16T17_CR1
.EQU  TIM16T17_CR1_CKD_N    , 8           @ Bits 9:8 CKD[1:0]: Clock division
                                       @ This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
                                       @ dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
                                       @ (ETR, TIx),
.EQU  TIM16T17_CR1_CKD_CK   , 0           @ 00: tDTS=tCK_INT
.EQU  TIM16T17_CR1_CKD_2CK  , 1 << 8      @ 01: tDTS=2*tCK_INT
.EQU  TIM16T17_CR1_CKD_4CK  , 2 << 8      @ 10: tDTS=4*tCK_INT
.EQU  TIM16T17_CR1_ARPE     , 1 << 7      @ Bit 7 ARPE: Auto-reload preload enable
                                       @ 0: TIMx_ARR register is not buffered
                                       @ 1: TIMx_ARR register is buffered
.EQU  TIM16T17_CR1_OPM      , 1 << 3      @ Bit 3 OPM: One-pulse mode
                                       @ 0: Counter is not stopped at update event
                                       @ 1: Counter stops counting at the next update event (clearing the bit CEN)
.EQU  TIM16T17_CR1_URS      , 1 << 2      @ Bit 2 URS: Update request source
                                       @ This bit is set and cleared by software to select the UEV event sources.
                                       @ 0: Any of the following events generate an update interrupt or DMA request if enabled.
                                       @ These events can be:
                                       @ – Counter overflow/underflow
                                       @ – Setting the UG bit
                                       @ – Update generation through the slave mode controller
                                       @ 1: Only counter overflow/underflow generates an update interrupt or DMA request if
                                       @ enabled.
.EQU  TIM16T17_CR1_UDIS     , 1 << 1      @ Bit 1 UDIS: Update disable
                                       @ This bit is set and cleared by software to enable/disable UEV event generation.
                                       @ 0: UEV enabled. The Update (UEV) event is generated by one of the following events:
                                       @ – Counter overflow/underflow
                                       @ – Setting the UG bit
                                       @ – Update generation through the slave mode controller
                                       @ Buffered registers are then loaded with their preload values.
                                       @ 1: UEV disabled. The Update event is not generated, shadow registers keep their value
                                       @ (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
                                       @ set or if a hardware reset is received from the slave mode controller.
.EQU  TIM16T17_CR1_CEN      , 1           @ Bit 0 CEN: Counter enable
                                       @ 0: Counter disabled
                                       @ 1: Counter enabled
                                 @ Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
                                       @ previously set by software. However trigger mode can set the CEN bit automatically by
                                       @ hardware.
                                       @ CEN is cleared automatically in one-pulse mode, when an update event occurs
@.end


@.ITEM     TIM16T17_CR2
.EQU  TIM16T17_CR2_OIS1N  , 1 << 9       @ Bit 9 OIS1N: Output Idle state 1 (OC1N output)
                                      @ 0: OC1N=0 after a dead-time when MOE=0
                                      @ 1: OC1N=1 after a dead-time when MOE=0
                                @ Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
                                      @ (LOCK bits in TIMx_BKR register).
.EQU  TIM16T17_CR2_OIS1   , 1 << 8       @ Bit 8 OIS1: Output Idle state 1 (OC1 output)
                                      @ 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
                                      @ 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
                                @ Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
                                      @ (LOCK bits in TIMx_BKR register).
.EQU  TIM16T17_CR2_CCDS     , 1 << 3      @ Bit 3 CCDS: Capture/compare DMA selection
                                      @ 0: CCx DMA request sent when CCx event occurs
                                      @ 1: CCx DMA requests sent when update event occurs
.EQU  TIM16T17_CR2_CCUS     , 1 << 2      @ Bit 2 CCUS: Capture/compare control update selection
                                      @ 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
                                      @ the COMG bit only.
                                      @ 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting
                                      @ the COMG bit or when an rising edge occurs on TRGI.
                                      @ Note: This bit acts only on channels that have a complementary output.
.EQU  TIM16T17_CR2_CCPC    , 1            @ Bit 0 CCPC: Capture/compare preloaded control
                                      @ 0: CCxE, CCxNE and OCxM bits are not preloaded
                                      @ 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated
                                      @ only when COM bit is set.
                                      @ Note: This bit acts only on channels that have a complementary output.
@.end


@.ITEM     TIM16T17_DIER
.EQU  TIM16T17_DIER_CC1DE   , 1 << 9      @ Bit 9 CC1DE: Capture/Compare 1 DMA request enable
                                      @ 0: CC1 DMA request disabled
                                      @ 1: CC1 DMA request enabled
.EQU  TIM16T17_DIER_UDE     , 1 << 8     @ Bit 8 UDE: Update DMA request enable
                                      @ 0: Update DMA request disabled
                                      @ 1: Update DMA request enabled
.EQU  TIM16T17_DIER_BIE    , 1 << 7      @ Bit 7 BIE: Break interrupt enable
                                      @ 0: Break interrupt disabled
                                      @ 1: Break interrupt enabled
.EQU  TIM16T17_DIER_COMIE   , 1 << 5      @ Bit 5 COMIE: COM interrupt enable
                                      @ 0: COM interrupt disabled
                                      @ 1: COM interrupt enabled
.EQU  TIM16T17_DIER_CC1IE   , 1 << 1      @ Bit 1 CC1IE: Capture/Compare 1 interrupt enable
                                      @ 0: CC1 interrupt disabled
                                      @ 1: CC1 interrupt enabled
.EQU  TIM16T17_DIER_UIE     , 1           @ Bit 0 UIE: Update interrupt enable
                                      @ 0: Update interrupt disabled
                                      @ 1: Update interrupt enabled
@.end


@.ITEM     TIM16T17_SR
.EQU  TIM16T17_SR_CC1OF    , 1 << 9      @ Bit 9 CC1OF: Capture/Compare 1 overcapture flag
                                      @ This flag is set by hardware only when the corresponding channel is configured in input
                                      @ capture mode. It is cleared by software by writing it to ‘0’.
                                      @ 0: No overcapture has been detected.
                                      @ 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
                                      @ already set
.EQU  TIM16T17_SR_BIF      , 1 << 7      @ Bit 7 BIF: Break interrupt flag
                                      @ This flag is set by hardware as soon as the break input goes active. It can be cleared by
                                      @ software if the break input is not active.
                                      @ 0: No break event occurred
                                      @ 1: An active level has been detected on the break input
.EQU  TIM16T17_SR_COMIF    , 1 << 5      @ Bit 5 COMIF: COM interrupt flag
                                      @ This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE,
                                      @ CCxNE, OCxM– have been updated). It is cleared by software by writing it to ‘0’.
                                      @ 0: No COM event occurred
                                      @ 1: COM interrupt pending
.EQU  TIM16T17_SR_CO1IF     , 1 << 1      @ Bit 1 CC1IF: Capture/Compare 1 interrupt flag
                                      @ If channel CC1 is configured as output:
                                      @ This flag is set by hardware when the counter matches the compare value, with some
                                      @ exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
                                      @ It is cleared by software.
                                      @ 0: No match.
                                      @ 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
                                      @ When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
                                      @ bit goes high on the counter overflow (in upcounting and up/down-counting modes) or
                                      @ underflow (in downcounting mode)
                                      @ If channel CC1 is configured as input:
                                      @ This bit is set by hardware on a capture. It is cleared by software or by reading the
                                      @ TIMx_CCR1 register.
                                      @ 0: No input capture occurred
                                      @ 1: The counter value has been captured in TIMx_CCR1 register (An edge has been
                                      @ detected on IC1 which matches the selected polarity)
.EQU  TIM16T17_SR_UIF        , 1          @ Bit 0 UIF: Update interrupt flag
                                      @ This bit is set by hardware on an update event. It is cleared by software.
                                      @ 0: No update occurred.
                                      @ 1: Update interrupt pending. This bit is set by hardware when the registers are updated:
                                      @ –At overflow or underflow regarding the repetition counter value (update if repetition
                                      @ counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
                                      @ –When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
                                      @ and UDIS=0 in the TIMx_CR1 register.
                                      @ –When CNT is reinitialized by a trigger event (refer to Section 13.4.3: TIM1 slave mode
                                      @ control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
@.end


@.ITEM     TIM16T17_EGR
.EQU  TIM16T17_EGR_BG   , 1 << 7         @ Bit 7 BG: Break generation
                                      @ This bit is set by software in order to generate an event, it is automatically cleared by
                                      @ hardware.
                                      @ 0: No action
                                      @ 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
                                      @ DMA transfer can occur if enabled.
.EQU  TIM16T17_EGR_COMG    , 1 << 5       @ Bit 5 COMG: Capture/Compare control update generation
                                       @ This bit can be set by software, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
                                       @ Note: This bit acts only on channels that have a complementary output.
.EQU  TIM16T17_EGR_CC1G    , 1 << 1       @ Bit 1 CC1G: Capture/Compare 1 generation
                                       @ This bit is set by software in order to generate an event, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: A capture/compare event is generated on channel 1:
                                       @ If channel CC1 is configured as output:
                                       @ CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
                                       @ If channel CC1 is configured as input:
                                       @ The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the
                                       @ corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF
                                       @ flag was already high.
.EQU  TIM16T17_EGR_UG      , 1            @ Bit 0 UG: Update generation
                                       @ This bit can be set by software, it is automatically cleared by hardware.
                                       @ 0: No action
                                       @ 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
                                       @ counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
                                       @ the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
                                       @ value (TIMx_ARR) if DIR=1 (downcounting).
@.end


@.ITEM     TIM16T17_CCMR1
.EQU  TIM16T17_CCMR1_OC1M_N , 4           @ Bits 6:4 OC1M: Output Compare 1 mode
                                       @ These bits define the behavior of the output reference signal OC1REF from which OC1 and
                                       @ OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on
                                       @ CC1P and CC1NP bits.
.EQU  TIM16T17_CCMR1_OC1M_FROZEN, 0       @ 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
                                       @ counter TIMx_CNT has no effect on the outputs (this mode is used to generate a timing
                                       @ base).
.EQU  TIM16T17_CCMR1_OC1M_SET_CH1A, 1 <<4 @ 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
                                       @ TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM16T17_CCMR1_OC1M_SET_CH1I, 2 <<4 @ 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
                                       @ counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
.EQU  TIM16T17_CCMR1_OC1M_TOGGLE, 3 << 4  @ 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
.EQU  TIM16T17_CCMR1_OC1M_FORCE_INACT, 4<<4 @ 100: Force inactive level - OC1REF is forced low.
.EQU  TIM16T17_CCMR1_OC1M_FORCE_ACT, 5<<4 @ 101: Force active level - OC1REF is forced high.
.EQU  TIM16T17_CCMR1_OC1M_PWM1, 6 << 4    @ 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
                                       @ else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as
                                       @ TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
.EQU  TIM16T17_CCMR1_OC1M_PWM2, 7 << 4    @ 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
                                       @ else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
                                       @ inactive.
                              @ Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
                                       @ (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
                                       @ output).
                                       @ 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
                                       @ comparison changes or when the output compare mode switches from “frozen” mode
                                       @ to “PWM” mode.
.EQU  TIM16T17_CCMR1_OC1PE  , 1 << 3      @ Bit 3 OC1PE: Output Compare 1 preload enable
                                       @ 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
                                       @ new value is taken in account immediately.
                                       @ 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
                                       @ register. TIMx_CCR1 preload value is loaded in the active register at each update event.
                              @ Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed
                                       @ (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
                                       @ output).
                                       @ 2: The PWM mode can be used without validating the preload register only in one
                                       @ pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
.EQU  TIM16T17_CCMR1_OC1FE  , 1 << 2      @ Bit 2 OC1FE: Output Compare 1 fast enable
                                       @ This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
                                       @ 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
                                       @ ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
                                       @ 5 clock cycles.
                                       @ 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is
                                       @ set to the compare level independently from the result of the comparison. Delay to sample
                                       @ the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
                                       @ the channel is configured in PWM1 or PWM2 mode.
.EQU  TIM16T17_CCMR1_CC1S_N , 0           @ Bits 1:0 CC1S: Capture/Compare 1 selection
                                       @ This bit-field defines the direction of the channel (input/output) as well as the used input.
.EQU  TIM16T17_CCMR1_CC1S_OUT, 0          @ 00: CC1 channel is configured as output
.EQU  TIM16T17_CCMR1_CC1S_TI1, 1 << 0     @ 01: CC1 channel is configured as input, IC1 is mapped on TI1
.EQU  TIM16T17_CCMR1_CC1S_TI2, 2 << 0     @ 10: CC1 channel is configured as input, IC1 is mapped on TI2
.EQU  TIM16T17_CCMR1_CC1S_TRC, 3 << 0     @ 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
                                       @ an internal trigger input is selected through TS bit (TIMx_SMCR register)
                                 @ Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).
@
@  Input capture mode
@
.EQU  TIM16T17_CCMR1_IC1F_N , 4           @ Bits 7:4 IC1F[3:0]: Input capture 1 filter
                                       @ This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to
                                       @ TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate
                                       @ a transition on the output:
.EQU  TIM16T17_CCMR1_IC1F_NOF, 0          @ 0000: No filter, sampling is done at fDTS
.EQU  TIM16T17_CCMR1_IC1F_N2, 1 << 4      @ 0001: fSAMPLING = fCK_INT, N = 2
.EQU  TIM16T17_CCMR1_IC1F_N4, 2 << 4      @ 0010: fSAMPLING = fCK_INT, N = 4
.EQU  TIM16T17_CCMR1_IC1F_N8, 3 << 4      @ 0011: fSAMPLING = fCK_INT, N = 8
.EQU  TIM16T17_CCMR1_IC1F_2N6, 4 << 4     @ 0100: fSAMPLING = fDTS / 2, N = 6
.EQU  TIM16T17_CCMR1_IC1F_2N8, 5 << 4     @ 0101: fSAMPLING = fDTS / 2, N = 8
.EQU  TIM16T17_CCMR1_IC1F_4N6, 6 << 4     @ 0110: fSAMPLING = fDTS / 4, N = 6
.EQU  TIM16T17_CCMR1_IC1F_4N8, 7 << 4     @ 0111: fSAMPLING = fDTS / 4, N = 8
.EQU  TIM16T17_CCMR1_IC1F_8N6, 8 << 4     @ 1000: fSAMPLING = fDTS / 8, N = 6
.EQU  TIM16T17_CCMR1_IC1F_8N8, 9 << 4     @ 1001: fSAMPLING = fDTS / 8, N = 8
.EQU  TIM16T17_CCMR1_IC1F_16N5, 10 << 4   @ 1010: fSAMPLING = fDTS / 16, N = 5
.EQU  TIM16T17_CCMR1_IC1F_16N6, 11 << 4   @ 1011: fSAMPLING = fDTS / 16, N = 6
.EQU  TIM16T17_CCMR1_IC1F_16N8, 12 << 4   @ 1100: fSAMPLING = fDTS / 16, N = 8
.EQU  TIM16T17_CCMR1_IC1F_32N5, 13 << 4   @ 1101: fSAMPLING = fDTS / 32, N = 5
.EQU  TIM16T17_CCMR1_IC1F_32N6, 14 << 4   @ 1110: fSAMPLING = fDTS / 32, N = 6
.EQU  TIM16T17_CCMR1_IC1F_32N8, 15 << 4   @ 1111: fSAMPLING = fDTS / 32, N = 8
                                          @ Note: Care must be taken that fDTS is replaced in the formula by CK_INT when ICxF[3:0] = 1, 2 or 3
.EQU  TIM16T17_CCMR1_IC1PSC_N, 2          @ Bits 3:2 IC1PSC: Input capture 1 prescaler
                                          @ This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
                                          @ The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
.EQU  TIM16T17_CCMR1_IC1PSC_1, 0          @ 00: no prescaler, capture is done each time an edge is detected on the capture input
.EQU  TIM16T17_CCMR1_IC1PSC_2, 1 << 2     @ 01: capture is done once every 2 events
.EQU  TIM16T17_CCMR1_IC1PSC_4, 2 << 2     @ 10: capture is done once every 4 events
.EQU  TIM16T17_CCMR1_IC1PSC_8, 3 << 2     @ 11: capture is done once every 8 events
@.END


@.ITEM     TIM16T17_CCER
.EQU  TIM16T17_CCER_CC1NP   , 1 << 3      @ Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
                                       @ CC1 channel configuration as output:
                                       @ 0: OC1N active high.
                                       @ 1: OC1N active low.
                                 @ Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
                                       @ in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).
.EQU  TIM16T17_CCER_CC1NE   , 1 << 2      @ Bit 2 CC1NE: Capture/Compare 1 complementary output enable
                                       @ 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
                                       @ and CC1E bits.
                                       @ 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,
                                       @ OSSR, OIS1, OIS1N and CC1E bits.
.EQU  TIM16T17_CCER_CC1P    , 1 << 1      @ Bit 1 CC1P: Capture/Compare 1 output polarity
                                       @ CC1 channel configured as output:
                                       @ 0: OC1 active high
                                       @ 1: OC1 active low
                                       @ CC1 channel configured as input:
                                       @ CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture
                                       @ operations.
                                       @ 00: non-inverted/rising edge
                                       @ The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external
                                       @ clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).
                                       @ 01: inverted/falling edge
                                       @ The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external
                                       @ clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
                                       @ 10: reserved, do not use this configuration.
                                       @ 11: non-inverted/both edges
                                       @ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations
                                       @ in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated
                                       @ mode). This configuration must not be used in encoder mode.
                                 @ Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
                                       @ in TIMx_BDTR register).
.EQU  TIM16T17_CCER_CC1E    , 1           @ Bit 0 CC1E: Capture/Compare 1 output enable
                                       @ CC1 channel configured as output:
                                       @ 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N
                                       @ and CC1NE bits.
                                       @ 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,
                                       @ OSSR, OIS1, OIS1N and CC1NE bits.
                                       @ CC1 channel configured as input:
                                       @ This bit determines if a capture of the counter value can actually be done into the input
                                       @ capture/compare register 1 (TIMx_CCR1) or not.
                                       @ 0: Capture disabled.
                                       @ 1: Capture enabled.
                                 @ Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is
                                       @ set in the TIMx_CR2 register then the CC1E active bit takes the new value from the
                                       @ preloaded bits only when a Commutation event is generated.
@.END


@.ITEM     TIM16T17_BDTR
.EQU  TIM16T17_BDTR_MOE , 1 << 15         @ Bit 15 MOE: Main output enable
                                       @ This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by
                                       @ software or automatically depending on the AOE bit. It is acting only on the channels which are
                                       @ configured in output.
                                       @ 0: OC and OCN outputs are disabled or forced to idle state
                                       @ 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
                                       @ TIMx_CCER register)
                                       @ See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
                                       @ enable register (TIM15_CCER) on page 440).
.EQU  TIM16T17_BDTR_AOE , 1 << 14         @ Bit 14 AOE: Automatic output enable
                                       @ 0: MOE can be set only by software
                                       @ 1: MOE can be set by software or automatically at the next update event (if the break input is
                                       @ not be active)
                                       @ Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
                                       @ in TIMx_BDTR register).
.EQU  TIM16T17_BDTR_BKP , 1 << 13         @ Bit 13 BKP: Break polarity
                                       @ 0: Break input BRK is active low
                                       @ 1: Break input BRK is active high
                                 @ Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
                                       @ in TIMx_BDTR register).
                                 @ Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
.EQU  TIM16T17_BDTR_BKE , 1 << 12         @ Bit 12 BKE: Break enable
                                       @ 0: Break inputs (BRK and CCS clock failure event) disabled
                                       @ 1; Break inputs (BRK and CCS clock failure event) enabled
                                 @ Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
                                       @ TIMx_BDTR register).
                                       @ Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
.EQU  TIM16T17_BDTR_OSSR, 1 << 11         @ Bit 11 OSSR: Off-state selection for Run mode
                                       @ This bit is used when MOE=1 on channels having a complementary output which are
                                       @ configured as outputs. OSSR is not implemented if no complementary output is implemented
                                       @ in the timer.
                                       @ See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
                                       @ enable register (TIM15_CCER) on page 440).
                                       @ 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
                                       @ 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1
                                       @ or CCxNE=1. Then, OC/OCN enable output signal=1
                                       @ Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
                                       @ bits in TIMx_BDTR register).
.EQU  TIM16T17_BDTR_OSSI, 1 << 10         @ Bit 10 OSSI: Off-state selection for Idle mode
                                       @ This bit is used when MOE=0 on channels configured as outputs.
                                       @ See OC/OCN enable description for more details (Section 17.5.8: TIM15 capture/compare
                                       @ enable register (TIM15_CCER) on page 440).
                                       @ 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
                                       @ 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or
                                       @ CCxNE=1. OC/OCN enable output signal=1)
                                       @ Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
                                       @ bits in TIMx_BDTR register).
.EQU  TIM16T17_BDTR_LOCK_N, 8             @ Bits 9:8 LOCK[1:0]: Lock configuration
                                       @ These bits offer a write protection against software errors
.EQU  TIM16T17_BDTR_LOCK_OFF, 0           @ 00: LOCK OFF - No bit is write protected
.EQU  TIM16T17_BDTR_LOCK_LEV1, 1 << 8     @ 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
                                       @ register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
.EQU  TIM16T17_BDTR_LOCK_LEV2, 2 << 8     @ 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
                                       @ register, as long as the related channel is configured in output through the CCxS bits) as well
                                       @ as OSSR and OSSI bits can no longer be written.
.EQU  TIM16T17_BDTR_LOCK_LEV3, 3 << 8     @ 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
                                       @ TIMx_CCMRx registers, as long as the related channel is configured in output through the
                                       @ CCxS bits) can no longer be written.
                                 @ Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
                                       @ has been written, their content is frozen until the next reset.
.EQU  TIM16T17_BDTR_DTG_N, 0              @ Bits 7:0 DTG[7:0]: Dead-time generator setup
                                       @ This bit-field defines the duration of the dead-time inserted between the complementary
                                       @ outputs. DT correspond to this duration.
                                       @ DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS
                                       @ DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
                                       @ DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
                                       @ DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
                                       @ Example if TDTS=125ns (8MHz), dead-time possible values are:
                                       @ 0 to 15875 ns by 125 ns steps,
                                       @ 16 µs to 31750 ns by 250 ns steps,
                                       @ 32 µs to 63 µs by 1 µs steps,
                                       @ 64 µs to 126 µs by 2 µs steps
                                 @ Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
                                       @ (LOCK bits in TIMx_BDTR register).
@.end


@.ITEM     TIM16T17_DCR
.EQU  TIM16T17_DCR_DBL_N, 8               @ Bits 12:8 DBL[4:0]: DMA burst length
                                       @ This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
                                       @ when a read or a write access is done to the TIMx_DMAR address).
                                       @ 00000: 1 transfer,
                                       @ 00001: 2 transfers,
                                       @ 00010: 3 transfers,
                                       @ ...
                                       @ 10001: 18 transfers.
.EQU  TIM16T17_DCR_DBL_MIN, 0             @ 1 transfer
.EQU  TIM16T17_DCR_DBL_MAX, 18            @ 18 transfers
.EQU  TIM16T17_DCR_DBA_N, 0               @ Bits 4:0 DBA[4:0]: DMA base address
                                       @ This 5-bits vector defines the base-address for DMA transfers (when read/write access are
                                       @ done through the TIMx_DMAR address). DBA is defined as an offset starting from the
                                       @ address of the TIMx_CR1 register.
                                       @ Example:
                                       @ 00000: TIMx_CR1,
                                       @ 00001: TIMx_CR2,
                                       @ 00010: TIMx_SMCR,
                                       @ ...
.EQU  TIM16T17_DCR_DBA_M, 0x1F            @ DBA Mask
@.end



